RISC Architecture An Overview

Typical questions
• Explain how pipelining improves the speed of operation?
• What are Register windows and how are they implemented in
RISC
• List three major features characteristics of a RISC and
describe how each of these features helps produce faster
execution.
• Discuss the structure of Pipelined RISC processor.
• Explain the different characteristics of RISC architecture.
• Describe the development of RISC processor.
• Write the use of large register file in RISC.
• List the technique to implement RISC processor.
• Give the similarities and differences between RISC and CISC
 What is RISC
• RISC, or Reduced Instruction Set Computer. is a type of
microprocessor architecture that utilizes a small, highly-
optimized set of instructions, rather than a more
specialized set of instructions often found in other types
of architectures.
• Every instruction in a single clock after fetch and decode.
• Smaller, less energy consumption.
• Sun Sparc, IBM Power series both have RISC
• Risc allows branch prediction and Pipelining because
they require fixed length instructions.
 Advantages of RISC over CISC
• RISC instructions being simple can be hardwired whereas CISC
are micro-prgmed.
• Reduced complexity of control unit and data path – thus it can
work at higher clock freq and thus with higher speeds.
• Thus, memory management and floating pt arthmetic units can
also be placed.
• Cost reduction because of simpler chip
• High Level Language compilers more eff. Codes in RISC than CISC
• Shorter design cycles
• Easier codes and instructions to handle.
• Fixed length instructions, so piplelining is easier.
 Features of RISC
• Simple instruction set
• Fixed length instructions
• Single machine cycle instructions
• Pipelining
• Very few addressing modes
• Large number of registers to prevent large interactions
with memory.
• Microcoding or microprogramming not required so
instructions can be hardwired.
• Load and Store architecture for memory
Design issues for RISC – register windowing

• Register Windowing – one sees 32 registers at

one time, which is just a window out of a
bigger pool of physical registers. When
subroutines called – no stack, but registers
rotate to get a fresh set of registers with some
overlap. Drawback – finite number of
registers will get exhausted and then to
handle that situation it takes more cycles.
 Design issues for RISC- pipelining
• Pipelining : a techique that allows for simultaneous
execution of parts, or stages, of instructions to
more efficiently process them.
– Fetch
– Read registers and decode instruction
– Execute or calculate address
– Access an operand in mem
– Write result to a register
– While one instruction is in stage one other is being done
parallel
 Design Issues in RISC - pipelining
• Data Dependencies and Branch Instructions
have to be handled carefully. Data
dependency – next instruction depends on
result of last one which has not taken place
due to previous one in pipeline.
• Conditional jumps may be problem if last
stage in pipeline and condition changes later
after jump has been processed.
 Design issues – single cycle instruction

• Mp stalled when instruction stage does not

take one clock cycle.
• Stalling can be because of delays in reading
from mem, poor instruction set design,
dependencies between instructions.
Performance issues in Pipelined systems

• Memory speed – caches. Fast mem b/w

processor and slower mem.
• Copy from main mem also kept in cache – to
speed up further references.
• Caches – problem of coherency. Results kept
in cache must go to main before it is read or
deleted in cache.
 Performance issues in pipelining
• Instruction Latency: Poor instructions that may
take more than one clock should be avoided.
– Highly encoded instructions that use complex
decoders
– Variable length instructions with multiple ref to mem
– Instructions that access main mem
– Complex instructions that require multiple clocks like
floating point mult.
 Performance Issues
• Dependency Issues – If one instruction sets the
conditions in the condition code register and next
tries to read those bits, 2nd has to wait for 1st to
complete.
• Instruction scheduling – and common
subexpression elimination
• F = a + b * c/d and g = a / (a+b*c/d)) calculates
(b*c/d) first, and uses its value for both f and g.
• Loop Unrolling, function inlining
 Cautions on RISC
• Code quality has to be good – o/w stalling
• Scheduling – depends on choice of compiler
• Debugging can be difficult with scheduling
• Code expansion
• They require large on chip cache.
 Comparison RISC - CISC
Characteristics of RISC architecture:
1. Relatively few instructions mostly register-to- CISC
register operations
2. Relatively few addressing modes (because of 1)
• 1. A large instruction set.
3. Memory access limited to load and store • 2. Instructions that perform
instructions. special tasks and are used
4. All operations done within the register of the infrequently.
CPU.
• 3. A large variety of addressing
5. Fixed-length, easily decoded instruction format
aligned to word boundaries simplifies control
modes (5-20 different modes).
logic • 4. Variable-length instruction
6. Single-cycle instruction execution fetch, formats.
decode, and execute phases for two to three • 5. Instructions that manipulate
instructions overlap: pipelining. Memory
references may take more clock cycles. operands in memory.
7. Hardwired rather than microprogrammed
control (faster).
 Other RISC characteristics

• 1. A large number of register useful for storing

intermediate results and for optimizing operand
references: much faster than memory references.
most frequent accessed operands are kept in registers.
2. Use of overlapped register windows to speed-up
procedure call and return.
3. Efficient instruction pipeline
4. Compiler support for efficient translation of high-level
language programs into machine language programs.
• Nowadays – RISC-CISC hybrids, a decoder
converts CISC to RISC, but power consumption
is still high.
• RISC allows more General Purpose registers
for more instructions to be processed
simultaneously.