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You are on page 1of 34

Branches, Control Structures,

Abstraction & Refinement

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-1

Agenda

Recap

Debugging

I/O

o Switch and LED interfacing

C Programming

o Random number generator, NOT gate in Keil

Outline

Arithmetic Overflow

Conditional Branches

Conditional and Iterative Statements

o if, while, for (In assembly and C)

Abstraction & Refinement

o Device Driver

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-2

Condition Codes

Bit Name Meaning after add or sub

N negative result is negative

Z zero result is zero

V overflow signed overflow

C carry unsigned overflow

is wrong

C cleared after an unsigned subtract if the

answer is wrong

V set after a signed addition or subtraction if

the answer is wrong

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-3

8-bit unsigned number wheel

96+64 224+64

+64

255 0 255 0

224

32

192 64 192 64

160 96

128 128

C bit Cleared

The carry bit, C, is set after an unsigned addition when the result is

incorrect.

The carry bit, C, is clear after an unsigned subtraction when the result is

incorrect.

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-4

8-bit unsigned number wheel

160-64 32-64

-64

255 0 255 0

224

32

192 64 192 64

160 96

128 128

-64

The carry bit, C, is set after an unsigned addition when the result is

incorrect.

The carry bit, C, is clear after an unsigned subtraction when the result is

incorrect.

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-5

Algorithm (unsigned)

1. Find values of both numbers

interpreted as unsigned

2. Perform addition or subtraction

3. Does the result fit as an unsigned?

• No -> addition C=1,

subtraction C=0

• Yes -> addition C=0,

subtraction C=1

the actual answer is 260-256 = 4

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-6

8-bit signed number wheel

-32+64 96+64

+64

-1 0 -1 0

-32

32

-64 64 -64 64

-96 96

-128 127 -128 127

+64

The overflow bit, V, is set after a signed addition or subtraction when the

result is incorrect.

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-7

8-bit signed number wheel

32-64 -96-64

-1 0 -64 -1 0

-32

32

-64 64 -64 64

-96 96

-128 127 -128 127

-64

V bit Cleared V bit Set

The overflow bit, V, is normally set when we cross over from 127 to -128

while adding or cross over from -128 to 127 while subtracting.

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-8

Algorithm (signed)

interpreted as signed

2. Perform addition or subtraction

3. Does the result fit as a signed?

• No -> V=1

• Yes -> V=0

8-bit

Examples: 10 – 5 = 5, V=0

-100 – 100 = -200, V=1

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-9

Addition Summary

Let the 32-bit result R be the result of the 32-bit addition X+Y.

N bit is set

if unsigned result is above 231-1 or

if signed result is negative.

N = R31

Z bit is set if result is zero

V bit is set after a signed addition if result is incorrect

V X 31.M 31.R31 X 31.M 31.R31

C bit is set after an unsigned addition if result is incorrect

C X 31.M 31 M 31.R31 R31. X 31

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-10

Subtraction Summary

Let the 32-bit result R be the result of the 32-bit subtraction X-Y.

N bit is set

if unsigned result is above 231-1 or

if signed result is negative.

N = R31

Z bit is set if result is zero

V bit is set after a signed subtraction if result is incorrect

C bit is clear after an unsigned subtraction if result is incorrect

C X 31 & M 31 | M 31 & R31 | R31 & X 31

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-11

Trick Question

When the Answer = 159

subtraction (32 –

129) is performed NZVC = 1010

in an 8-bit system

what is the result

and the status of

the NZVC bits?

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-12

Unsigned Promotion

Promotion involves increasing the

precision of the input numbers, and

performing the operation at that higher

precision

Decimal 8-bit 32-bit

224 1110,0000 0000,0000,0000,0000,0000,0000,1110,0000

+ 64 +0100,0000 +0000,0000,0000,0000,0000,0000,0100,0000

288 0010,0000 0000,0000,0000,0000,0000,0001,0010,0000

original precision

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-13

Unsigned Ceiling and Floor

Promote A to A 32 Promote A to A 32

Promote B to B32 Promote B to B32

R32=A32+B 32 R32=A32-B 32

ok overflow ok underflow

R32 < 255 R32 >255 R32 > 0 R 32 < 0

R32 R32

R=R32 R=255 R=R32 R=0

end end

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-14

Signed Promotion

duplicate the sign bit

-96 1010,0000 1111,1111,1111,1111,1111,1111,1010,0000

-64 -0100,0000 -0000,0000,0000,0000,0000,0000,0100,0000

-160 0110,0000 1111,1111,1111,1111,1111,1111,0110,0000

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-15

Signed Ceiling and Floor

Signed add Signed sub

Promote A to A 32 Promote A to A 32

Promote B to B 32 Promote B to B 32

R32=A32+B 32 R32=A32-B 32

underflow overflow underflow overflow

R32 < -128 R32 >127 R32 < -128 R32 >127

R32 R32

R = -128 R=127 R = -128 R=127

R=R32 R=R32

end end

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-16

Conditional Branch Instructions

Unsigned conditional branch

follow SUBS CMN or CMP

BLO target ; Branch if unsigned less than (if C=0, same as BCC)

BLS target ; Branch if unsigned less than or equal to (if C=0 or Z=1)

BHS target ; Branch if unsigned greater than or equal to

(if C=1, same as BCS)

BHI target ; Branch if unsigned greater than (if C=1 and Z=0)

CMP R0,R1

R0<R1

BLO

R0≥R1 target

Next instruction

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-17

Conditional Branch Instructions

follow SUBS CMN or CMP

BLT target ; if signed less than (if (~N&V | N&~V)=1, i.e. if N≠V)

BGE target ; if signed greater than or equal to (if (~N&V | N&~V)=0, i.e. if N=V)

BGT target ; if signed greater than (if (Z | ~N&V | N&~V)=0, i.e. if Z=0 and N=V)

BLE target ; if signed less than or equal to

(if (Z | ~N&V | N&~V)=1, i.e. if Z=1 or N≠V)

CMP R0,R1

R0<R1

BLT

R0≥R1 target

Next instruction

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-18

Equality Test

LDR R2, =G ; R2 = &G uint32_t G;

LDR R0, [R2] ; R0 = G if(G == 7){

CMP R0, #7 ; is G == 7 ? GEqual7();

BNE next1 ; if not, skip }

BL GEqual7 ; G == 7

next1

LDR R2, =G ; R2 = &G

LDR R0, [R2] ; R0 = G if(G != 7){

CMP R0, #7 ; is G != 7 ? GNotEqual7();

BEQ next2 ; if not, skip }

BL GNotEqual7 ; G != 7

next2

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-19

Unsigned

Assembly code

Conditional Structures

C code

LDR R2, =G ; R2 = &G uint32_t G;

LDR R0, [R2] ; R0 = G if(G > 7){

CMP R0, #7 ; is G > 7? GGreater7();

BLS next1 ; if not, skip }

BL GGreater7 ; G > 7

next1

LDR R2, =G ; R2 = &G

LDR R0, [R2] ; R0 = G if(G >= 7){

CMP R0, #7 ; is G >= 7? GGreaterEq7();

BLO next2 ; if not, skip }

BL GGreaterEq7 ; G >= 7

next2

LDR R2, =G ; R2 = &G

LDR R0, [R2] ; R0 = G if(G < 7){

CMP R0, #7 ; is G < 7? GLess7();

BHS next3 ; if not, skip }

BL GLess7 ; G < 7

next3

LDR R2, =G ; R2 = &G

LDR R0, [R2] ; R0 = G if(G <= 7){

CMP R0, #7 ; is G <= 7? GLessEq7();

BHI next4 ; if not, skip }

BL GLessEq7 ; G <= 7

next4

Program 5.9. Unsigned conditional structures.

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-20

Signed Conditional Structures

Assembly code C code

LDR R2, =G ; R2 = &G int32_t G;

LDR R0, [R2] ; R0 = G if(G > 7){

CMP R0, #7 ; is G > 7? GGreater7();

BLE next1 ; if not, skip }

BL GGreater7 ; G > 7

next1

LDR R2, =G ; R2 = &G

LDR R0, [R2] ; R0 = G if(G >= 7){

CMP R0, #7 ; is G >= 7? GGreaterEq7();

BLT next2 ; if not, skip }

BL GGreaterEq7 ; G >= 7

next2

LDR R2, =G ; R2 = &G

LDR R0, [R2] ; R0 = G if(G < 7){

CMP R0, #7 ; is G < 7? GLess7();

BGE next3 ; if not, skip }

BL GLess7 ; G < 7

next3

LDR R2, =G ; R2 = &G

LDR R0, [R2] ; R0 = G if(G <= 7){

CMP R0, #7 ; is G <= 7? GLessEq7();

BGT next4 ; if not, skip }

BL GLessEq7 ; G <= 7

next4

Program 5.11. Signed conditional structures.

4-21

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

If-then-else

G1<=G2 G1>G2

isLessEq isGreater

LDR R0, [R2] ; R0 = G1 if(G1>G2){

LDR R2, =G2 ; R2 = &G2 isGreater();

LDR R1, [R2] ; R1 = G2 }

CMP R0, R1 ; is G1 > G2 ? else{

BHI high ; if so, skip to high isLessEq();

low BL isLessEq ; G1 <= G2 }

B next ; unconditional

high BL isGreater ; G1 > G2

next

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-22

While Loops

G2>G1

G2<=G1

Body

LDR R5, =G2 ; R5 -> G2 while(G2 > G1){

loop LDR R0, [R5] ; R0 = G2 Body();

LDR R1, [R4] ; R1 = G1 }

CMP R0, R1 ; is G2 <= G1?

BLS next ; if so, skip to next

BL Body ; body of the loop

B loop

next

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-23

For Loops

Process(); Process();

} }

i=0 i = 100

i < 100 i != 0

i i

i = i+1 i = i-1

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-24

For Loops

loop CMP R4, #100 ; index >= 100? Process();

BHS done ; if so, skip to done }

BL Process ; process function*

ADD R4, R4, #1 ; R4 = R4 + 1

B loop

done

Count up

loop BL Process ; process function Process();

SUBS R4, R4, #1 ; R4 = R4 - 1 }

BNE loop

done

Count down

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-25

System Design

What does being in a state mean?

List state parameters

What is the starting state of the system?

Define the initial state

What information do we need to collect?

List the input data

What information do we need to generate?

List the output data

How do we move from one state to another?

Actions we could do

What is the desired ending state?

Define the ultimate goal

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-26

System Design

Successive Refinement

Stepwise Refinement

Systematic Decomposition

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-27

System Design

Start with a task and decompose the

task into a set of simpler subtasks

Subtasks are decomposed into even

simpler sub-subtasks

Each subtask is simpler than the task

itself

Make design decisions

document decisions and subtask

requirements

Ultimately, subtask is so simple, it can

be converted to software

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-28

System Design

Four building blocks:

“do A then do B” → sequential

“do A and B in either order” → sequential

(parallel)

“if A, then do B” → conditional

“for each A, do B” → iterative

“do A until B” → iterative

“repeat A over & over forever” → iterative

(condition always true)

“on external event do B” → interrupt

“every t msec do B” → interrupt

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-29

Successive Refinement

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-30

Successive Refinement

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-31

Abstraction - Device Driver

Abstraction allows us to modularize our code and give us

the option to expose what we want users to see and hide

what we don’t want them to see.

A Device Driver is a good example where abstraction is

used to expose public routines that we want users of the

driver to call and use private routines to hide driver

internals from the user (more on private routines later)

LED Driver (PE0)

LED_Init

A user simply has to know

LED_Off what a routine expects and

what it returns in order to

LED_On

call it (calling convention).

LED_Toggle Internals do not matter to caller

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-32

Port E LED Abstraction

PE0 EQU 0x4005C004 ;bit-specific address Port E bit 0

LED_Init

LDR R1, =SYSCTL_RCGCGPIO_R ; R1 -> SYSCTL_RCGCGPIO_R

LDR R0, [R1] ; previous value

ORR R0, R0, #0x00000010 ; activate clock for Port E

STR R0, [R1]

NOP

NOP ; allow time to finish activating

LDR R1, =GPIO_PORTE_DIR_R ; R1 -> GPIO_PORTE_DIR_R

LDR R0, [R1] ; previous value

ORR R0, R0, #0x01 ; PE0 output

STR R0, [R1] ; set direction register

LDR R1, =GPIO_PORTE_AFSEL_R ; R1 -> GPIO_PORTE_AFSEL_R

LDR R0, [R1] ; previous value

BIC R0, R0, #0x01 ; disable alt funct

STR R0, [R1] ; set alternate function register

LDR R1, =GPIO_PORTE_DEN_R ; R1 -> GPIO_PORTE_DEN_R

LDR R0, [R1] ; previous value

ORR R0, R0, #0x01 ; enable PE0 digital port

STR R0, [R1] ; set digital enable register

BX LR

Program 4.3. Software interface for an LED on PE0 (SSR_xxx.zip).

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-33

Port E LED Abstraction

LED_Off

LDR R1, =PE0 ; R1 is 0x4005C004

MOV R0, #0

STR R0, [R1] ; affect just PE0

BX LR

LED_On

LDR R1, =PE0 ; R1 is 0x4005C004

MOV R0, #1

STR R0, [R1] ; affect just PE0

BX LR

LED_Toggle

LDR R1, =PE0 ; R1 is 0x4005C004

LDR R0, [R1] ; previous value

EOR R0, R0, #1 ; flip bit 0

STR R0, [R1] ; affect just PE0

BX LR

Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari 4-34

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