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Predication Predication Registers Speculation Control Data Software Pipelining Prolog, Kernel, & Epilog phases Automatic Register Naming
Chapter 16 Control Unit Operation
No HW problems on this chapter. It is important to understand this material on the architecture of computer control units, and microprogrammed control units.
Basic Elements of Processor ALU Registers Internal data paths External data paths Control Unit
A Simple Computer & its Control Unit
± Execute.Instruction Micro-Operations A computer executes a program of instructions (or instruction cycles) Each instruction cycle has a number to steps or phases: ± Fetch. ± Interrupt (if requested) These can be seen as micro-operations ²Each step does a modest amount of work ²Atomic operation of CPU . ± Indirect (if specified).
Constituent Elements of its Program Execution .
Types of Micro-operation Transfer data between registers Transfer data from register to external Transfer data from external to register Perform arithmetic or logical ops .
Control Signals Clock ² One micro-instruction (or set of parallel microinstructions) per clock cycle Instruction register ² Op-code for current instruction ² Determines which micro-instructions are performed Flags ² State of CPU ² Results of previous operations From control bus ² Interrupts ² Acknowledgements .
Control Signals .output Within CPU ²Cause data movement ²Activate specific functions Via control bus ²To memory ²To I/O modules .
Flowchart for Instruction Cycle .
4 ´Controlµ Registers Utilized Program Counter (PC) ²Holds address of next instruction to be fetched Memory Address Register (MAR) ²Connected to address bus ²Specifies address for read or write op Memory Buffer Register (MBR) ²Connected to data bus ²Holds data to write or last data read Instruction Register (IR) ²Holds last instruction fetched .Fetch .
Fetch Cycle Address of next instruction is in PC Address (MAR) is placed on address bus t1: MAR (PC) Control unit issues READ command Result (data from memory) appears on data bus Data from data bus copied into MBR t2: MBR (memory) PC incremented by 1 (in parallel with data fetch from memory) PC (PC) +1 Data (instruction) moved from MBR to IR t3: IR (MBR) MBR is now free for further data fetches .
Fetch Cycle Fetch Cycle: t1: MAR t2: MBR PC t3: IR (PC) (memory) (PC) +1 (MBR) .
Then: (PC) (memory) (PC) +1 (MBR) Why? Is this equally correct? t1: t2: t3: MAR MBR PC IR (PC) (memory) (PC) +1 (MBR) .Fetch Cycle Let Tx be the t1: MAR t2: MBR PC t3: IR time unit of the clock.
Basic Rules for Clock Cycle Grouping Proper sequence must be followed ² MAR (PC) must precede MBR (memory) Conflicts must be avoided ² Must not read & write same register at same time ² MBR (memory) & IR (MBR) must not be in same cycle Also: PC (PC) +1 involves addition ² Use ALU ? ² May need additional micro-operations .
Indirect Cycle Indirect Cycle: t1: MAR t2: MBR t3: IRaddress (IRaddress) (memory) (MBRaddress) IR is now in same state as if direct addressing had been used (What does this say about IR size?) .
Interrupt Cycle Interrupt Cycle: t1: t2: MBR (PC) MAR save-address PC routine-address t3: memory (MBR) This is a minimum. saving context is done by interrupt handler routine.B. not microops . May be additional micro-ops to get addresses N.
X t1: t2: t3: MAR (IRaddress) MBR (memory) R1 R1 + (MBR) Different for each instruction Note no overlap of micro-operations . memory Execute Cycle: ADD R1.Execute Cycle: ADD R1.
Execute Cycle: ISZ X Execute Cycle: ISZ X t1: t2: t3: t4: (inc and skip if zero) MAR (IRaddress) MBR (memory) MBR (MBR) + 1 memory (MBR) if (MBR) == 0 then PC (PC) + 1 Notes: ³if´ is a single micro-operation Micro-operations done during t4 .
Execute Cycle: BSA X Execute: BSA X t1: MAR MBR t2: PC memory t3: PC (Branch and Save Address) BSA X .Branch and save address Address of instruction following BSA is saved in X Execution continues from X+1 (IRaddress) (PC) (IRaddress) (MBR) (PC) + 1 .
Control Signals .
Internal Organization Usually a single internal bus Gates control movement of data onto and off the bus Control signals control data transfer to and from external systems bus Temporary registers needed for proper operation of ALU .
Hard Wired Control Unit The Cycles (Fetch. All instructions share it . Interrupt) are constructed as a State Machine The Individual instruction executions can be constructed as State Machines ² Common sections can be shared. Indirect. Execute. There is a lot of similarity One ALU is implemented.
and test Resultant design is inflexible. .Problems With Hard Wired Designs Sequencing & micro-operation logic gets complex Difficult to design. multiple computation units. etc. prototype.) Adding new instructions requires major design and adds complexity quickly. and difficult to build upon (Pipeline.
Chapter 17 Micro-programmed Control .
How is this possible? . Indirect. Tasks of Control Unit: Microinstruction sequencing Microinstruction execution May be expected to complete instruction execution in ³1´ clock cycle.Control Unit Organization The Control Memory contains sequences of microinstructions that provide the control signals to execute instruction cycles.g. Execute. and Interrupt. Fetch. e.
Recall: Micro-sequencing .
Example of Control Memory Organization Microinstructions: Generate Control Signals Provide Branching Do both .
Horizontal vs Vertical Microprogramming Horizontal Microprogrammed ² Unpacked ² Hard ² Direct Vertical Microprogrammed ² Packed ² Soft ² Indirect .
Example Microprogramming Formats MicroProgram Counter Subroutines Stack Control Register (MicroProgram Format) .
Microinstruction Encoding Direct Encoding .
Microinstruction Encoding Indirect Encoding .
Horizontal Micro-programming Wide control memory word High degree of parallel operations possible Little encoding of control information Fast .
Vertical Micro-programming Width can be much narrower Control signals encoded into function codes ± need to be decoded More complex. more complicated to program. less flexibility More difficult to modify Slower .
Typical Microinstruction Formats .
Next Address Decision Depending on ALU flags and control buffer register: ²Get next instruction ± Add 1 to control address register ²Jump to new routine based on jump microinstruction ± Load address field of control buffer register into control address register ²Jump to machine instruction routine ± Load control address register based on opcode in IR .
Microprogrammed Control Unit .
Advantages and Disadvantages of Microprogramming Advantage: Simplifies design of control unit ² Cheaper ² Less error-prone ² Easier to modify Disadvantage: Slower .
condition flags.Design Considerations Necessity of speed Size of microinstructions Address generation ²Branches ± Both conditional and unconditional ± Based on current microinstruction. contents of IR ± Based on format of address information + Two address fields + Single address field + Variable format .
Address Generation Explicit Two-field Unconditional Branch Conditional branch Mapping Addition Implicit Residual control .
Branch Control: Two Address Fields Branch based upon: Instruction Opcode Address 1 Address 2 Does require a wide microinstruction. but no address calculation is needed .
g. e.Branch Control: Single Address Field Branch based upon: Next instruction Address Opcode Does require more circuitry. adder .
and is slowest.Branch Control: Variable Format One bit determines microinstruction format: Control signal format Branch format Does require even more circuitry. .
State Machine Inputs Combinational Logic Circuit Outputs Clock Storage Elements . Storage elements ²Maintain state representation.State Machine Combinational logic ²Determine outputs at each state. ²Determine next state.
.State Diagram Shows states and actions that cause transitions between states.
Example State Machine Inputs Outputs Next States Master-slave flipflops .
Control Unit with Decoded Inputs .
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