Guided by:

P. Satyanarayana
Assistant professor
G. Gopal
148R1D5703
VLSI-SD
1st year 2nd sem
Contents:
 Aim
 Introduction
 Literature survey
 DAC’S
 Existing methods
 Proposed method
 Results
 Conclusion
AIM:
 The main aim of this paper is to present a successive
approximation register and ADC based on charge
sharing principle.
 ADC uses a new background calibration technique
INTRODUCTION:
 SAR:
 A successive approximation register subcircuit designed to
supply an approximate digital code of Vin to the internal
DAC.
 ADC:
 An analog -to-digital converter (ADC, A/D, or A to D) is a
device that converts a continuous physical to a digital
number that represents the quantity's amplitude.
 The conversion involves quantization of the input, so it
necessarily introduces a small amount of error.
LITERATURE SURVEY:
 H.-Y. Tai, H.-W. Chen, and H.-S. Chen, “A 3.2 fJ/c.-s. 0.35 V 10b 100 kS/s SAR
ADC in 90 nm CMOS,” in Proc. IEEE Symp. VLSI Circuits (VLSIC), Jun. 2012, pp.
92–93.

 C.-Y. Liou and C.-C. Hsieh, “A 2.4-to-5.2 fJ/conversion-step 10b 0.5-to-4

MS/s SAR ADC with charge-average switching DAC in 90 nm CMOS,” in
Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), Feb. 2013, pp. 280–281.

 J. Craninckx and G. van der Plas, “A 65 fJ/conversion-step 0-to-50 MS/s 0-to-0.7

mW 9b charge-sharing SAR ADC in 90 nm digital CMOS,” in Proc. IEEE Int.
Solid-State Circuits Conf. (ISSCC), Feb. 2007, pp. 246–247.

 P. M. Figueiredo et al., “A 90 nm CMOS 1.2 V 6b 1 GS/s two-step subranging

ADC,” in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), Feb. 2006, pp. 2320–
2321.
DAC’S
 DAC is based on charge redistribution (CR)
 In CR DAC each capacitor is connected to ground or ref
voltage  req. low impedance source  leads to negative
power impact on power consumption.
 Hence charge sharing (CS) process has alleviated to overcome
these drawbacks.
ADC TOPOLOGY DIAGRAM
 In CS SAR a conversion is
requested when reset signal
is pulled to 1.
 Switches sp and sn are
closed and i/p signal is
tracked by cp and cn and
DAC capacitors C7 to C1 are
charged to VDD.
 When reset returns to 0, sp
and sn are opened and
voltage is held on vp and vn
and DAC capacitors hold
VDD.
CS SAR WITH BACKGROUND
COMPARATOR
CALIBRATION: Then SAR starts by sending
request to comparison trigger
that activates the comparator.
 Depending on comparison
result the controller adds or
removes charge from TH, by
closing corresponding switches
in DAC.
 This process is repeated for all
bits and as difference between
vp and vn is reduced towards
zero and results are stored by
controller
BACKGROUND COMPARATOR
CALIBRATION
 The comparator calibration takes place only after
ADC output is already available (EOC=1) & happens
only at random cycles of binary generator.
 If random output is 1, the switch shorts vp and vn,
redistributing the residual charge .
 As differential voltage at comparator input =0,
comparator detects offset is =ve or –ve.
 The comparator o/p feeds calibration block which
increases or reduces vcal by delta vcal.
 The comparator & calibration block comprise a –ve
feedback loop & offset ends to zero after some cycles.
 The process stops after comparator o/p calibrates
between 0 and 1
SELF-CALIBRATED COMPARATOR
 Works for low voltages as offset calibrations works
better at slowering branch.
 The vth of p-type in 130nm technology is very close to
VDD at 250nm.
 Due to +ve feedback all the transistors were drawn
with minimum size.
 Comparator size yields to input referred noise.
 Initially cal and cal’ are When calibration goes 1, the
assumed to be discharged and differential input of comparator
Vcal and Vcal’ are at VDD. is forced to 0.
 Pcal and P’cal are cutoff and  The circuit behaves as in
have reduced effect on convebtional latched
calibration threshold. cmparator and after
 Here calibration is zero hence comparision is ready results
pmos Pres- and nmos nres+ are are propagated to NOR
ON. gates.
 Capacitor Ncap- is discarded
and Ncap+ is charged to VDD.
LOCAL VOLTAGE BOOSTING
 This happens for the DAC
reset and TH switches, and
the two switches in the DAC
that connect a given
capacitor in parallel and the
 The ADC operation at very low two that connect in
antiparallel.
 Therefore, for this particular
 voltages is enabled by the 8-bit ADC, 24 VBs are
use of a VB circuit that required, including those
doubles the gate voltage for used by comparator self
all the MOS switches inside calibration scheme.
the TH, the DAC, and the
comparator calibration
circuit.
PROCESS:
 When i/p is high, o/p of inverter I1 connects the bottom plate of
Cb to VDD.
 Node A is shorted to ground by transistor N1.
 P2=ON & precharge Cb to VDD, thus forcing node A to
2VDD.
 This voltage is maintained since A is a high impedance node.
 Circuit has no static power consumption and dynamic power
required is only totie transistors to supply rails
 ADC safely operates with a max supply of 600mv.
RESULTS:
CONCLUSION:
 We discussed the implementation of a SAR ADC based on a
CS-based DAC. A novel background self- calibration method
was proposed to mitigate the effect of comparator offset on the
overall ADC linearity. Differently from previous
implementations, this technique is able to work under very
low-supply voltages, not demanding any pre amplifier, thus
requiring no static power consumption.
 The operation was limited to a minimum supply voltage of 350
mV, mainly because we have employed a custom controller.
THANK YOU