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Digital Controller For Power

Electronic Systems

Renji Chacko, Scientist ‘D’
Power Electronics Group

CDAC (formerly ERDCI), Thiruvanathapuram.
Web Site:

Emergence of Power Electronics Systems

DC drives, AC drives, UPS systems
Automotive applications - EV, HEV
Non conventional energy converters
- Solar, wind etc.
Power quality systems
- STATCOM, Harmonic compensators
Vector control techniques for AC systems
Implemented with digital controller

Control Hardware

Analog Controller
Discrete Digital Logics
Digital Signal Processor

Hardware Selection depends on
Application, Circuit complexity, Speed,

To Summarize on Analog

Susceptible to EMI
High band-width Sensitive to Component

High resolution
Sensitive to
Easy to design Temperature
Simple circuit for Hardwired Design
small systems Limited to Classical
Control System

Digital Systems Data Processing Control Application Large memory Minimum memory Data storage No external data storage High level user interface Minimum user interface Keyboard/ display Keypad and LCD display interface Industrial fieldbus Standard networking networking Data processing delay Computational delay acceptable critical Non real time Real time .

16-bit TIMER Sampling Intervals and Delays INT. Functional Requirements of a Digital Controller CPU Arithmetic and logic operations. Current Driven OUT 8/12-bit Data for Display DIGITAL IN Optically Isolated OUT Optically Isolated. Fast Conversion. Interrupts for Real Time Control Functions Elements USART Serial to Parallel and Parallel to Serial Conversion and Transmission ANALOG IN 12-bit. Transistor/Relay Driven .


The CPU 16 bit CPU with 2 Timers Interrupt Data Controller clock Bus Data Bus 8-bit 20 bit Address Int. write. etc control 80C188 80C188 control Clock 24MHz in Bus Control for DMA. address Bus Control lines for Read. Tim Timer etc out Internal Decoders I/o Built-in I/Os cs .

To summarize on Micro-Controller Large Dynamic Range Creates Numerical DISADVANTAGES Insensitive to Time Patterns in an Analog ADVANTAGES and Temperature World Common Hardware Minimum Hardware for many Applications even for Simple Algorithmic Applications Implementation Design is Time Repeatable Consuming Remote Computer Computational Delay is Interface Critical Self Diagnostics .


Real Time Control Reacts in deterministic way Several tasks executed concurrently .

Comparison between DSP and Micro-Processor High Performance On-chip Peripherals Signal Processing Supervisory functions Micro-controller Architecture Familiar Architecture Advanced Control DSP Techniques Additional functions Low Performance Computation Delay Numerical Problems Limited Peripherals .

15) 256x16 288x16 4Kx16 32Kx16 D(0.15) I/O CPU 64Kx16 16-Bit TREG 16-Bit x 16-Bit Multiply Software 32-Bit PREG WSG ShiftL Timer 32-Bit ALU 32-Bit ACC Serial Port 8 Auxiliary Registers (sync) 8 Level Hardware Stack Repeat Instruction Counter Serial Port 2 Status REG (async) . Architecture of TMS320F206 DSP D/P RAM D RAM D/P RAM P FLASH A(0.

DSP Features Features Benefits Single Cycle Instruction Advanced Algorithm Pipelined Architecture High Band Width Harvard Architecture Parallel Data & Program Hardware Multiplier Min. Minimize Hardware Serial I/O . Truncation Error Hardware Stack Fast Int. Computation Delay Hardware Shifters Large Dynamic Range 16-Bit Word Min. Wait State. Processing Saturation Mode Prevents Wrap-Around Built-in Timer. Quantization Errors 32-Bit Registers Min.

Comparison between Floating Point and Fixed Point Digital Controllers Less Expensive Programmable Less Hardware Software Development Floating Point Fixed Point Cost Low Software Development in High Development Cost High Level Language Truncation and Overflow Errors Effective codes Expensive and Costly through Assembly Components Language .

Real time DSP Controller for PE Clock Reset Fault Interlock Analog Gate Signal Sensors Gate Driver Interface Generation DSP ( AC Drive FPGA Algorithm ) User Digital Analog output Interface Logic (Debug) Serial Development Network JTAG Interface System Interface .

Stand Alone Medium Power Systems for Industrial Drives.DSP based PE Controllers Stand Alone Small Systems for UPS. small AC Drives etc. PC Based Controller for large systems. . UPS etc.

P Flash Fb. RS232C ADC USART Ckt TxD RxD DSP Circuits for PE . Stand Alone Small Systems Ref. To Gate Isolation CPU FPGA Ckt Timer Int. RAM Fb.


Stand Alone Medium Power Systems To AD DP DSP Gat C RAM Ckt e DA CPU s C Digital I/O RS232C 888888 RS485 .


Keyboard. VDU. HDD. Keyboard. PC Based Controller Features  Standard Hardware  One PCB PE Specific  Upto to date Hardware PCBs  Cost High On PC MB  All software resource easily adaptable  Fast development Industrial PC All PC Elements such as PC SMPS. VDU. Mouse Used during design FDD. Mouse Removed SMPS by small one and HDD by Flash Replaced . FDD.

PE Specific Hardware on PC DSP To 888888 Ckt Gat s e DP RAM I/O PC interfa Bus ce DP DSP To RAM Ckt Gat s e .

PC Add-on System .

Control Hardware Flow Diagram .

Digital Controller Hardware Features Multi layer PCB with Dedicated digital and ground planes On board digital power supply regulator Proper isolation from power circuit Proper placement/ shielding to reduce EMI/EMC effect Placement of components : No mixing of high frequency low frequency/ analog signals Local decoupling for digital circuits Isolation for I/O signals .

Electromechanical devices and PFC . Design Techniques for EMC Most preferred techniques  Circuit design and choice of components  Cables and Connectors  Filters and Transient suppressors  Shielding  PCB layout  ESD.

Preventing demodulation problem  Switch-mode design Topology.Protocols  Choice of passive components .Circuit design and choice of components  Digital components and circuit design Choosing components.Bad IC sockets. Spread spectrum clocking  Analog components and circuit design Choosing components. Communication.Snubbing. Rectifiers.Optoisolation.Heat sinks. Magnetics  Signal communication components and circuit design Non-metallic communication.

…. Sensor Sensor Drive Drive nn Elements Elements nn .Distributed Control Architecture Asyn link Syn link Drive1 Actuators Actuators Drive1 Sensor Sensor Drive Drive 22 Elements Elements 11 …..

Variable or logic Data Address. 16-bit. S-to-M. no of data. 8-bit. Controller Networking Mod Bus Address Function Data Checksum EOF Address Is the Address of the Controller Function M-to-S. RS-485 . data Checksum If no error acknowledge or skip Master – Slave configuration Message oriented protocol Can be implemented on standard hardware like RS-232.

Mod Bus Protocol Master Slave 1 Slave 2 Slave n Query Update a variable value Master Slave Acknowledge Response (Value updated) Data exchange in write mode Query Read a variable value Master Slave Value of the variable Response Data exchange in read mode .

Error detection and signaling  Automatic retransmission of corrupted messages. Controller Area Network(CAN) S R I A I Idle O Identifier T D r0 DLC Data CRC C EOF F Idle F R E K S Message Frame Format CAN efficiently supports distributed real-time control applications  Producer/Consumer broadcast model  Prioritization of messages. message identifiers instead of node address  Configuration flexibility  High reliability . multiple-access-with-collision-resolution (CSMA/CR) protocol Non-destructive bit-wise arbitration Message oriented broadcast communication .  Autonomous switching off of defect nodes Carrier-sense.

CAN Protocol .

3 V JTAG RS232 12V Processor based CAN CAN Controller interface Bus SMPS 14V DC 15V. Digital Controller for Automotive Application PC 3. 5V Bus (Optional) 42V Peripheral Interface GATE 42V DC drive SMPS Bus Digital Analog GATE I/O I/O Signals .

System Design  Formulate the Specification  Develop the Overall Block Diagram  Develop the Control Block  Develop the Flow Chart  Develop the Flow Diagram  Select an Appropriate Hardware  Develop the Functional Software Modules  Appropriately Cascade the Functional Modules  Scale and Debug .

Common Software Functional Modules • Digital/ Analog input interface • Space vector PWM • PID controller • d-q Transformation and Re-transformation • 3–phase to 2–phase transformation and vice versa • Machine model implementation • Calculation of machine torque • Calculation of speed • Calculation of stator flux • Delay elements • Integrator • Sin and cos function generators •Digital/ Analog output interface .

Functional Module Identification Look up table based function input output f(n) generator Integrator t = kts 0 kts u (kts ) = ∫ e(t )dt = ∫ e(t )dt + ∫ e(t )dt t = −∝ −∝ 0 input output u (kts ) = u[(k − 1)ts ] + Ts * e[kts ] Delay element input output du (t ) Td + u (t ) = e(t ) dt u (kts ) = u[(k − 1)ts ] + [(Ts Td ) * {e(kts ) − u (k − 1)ts}] .

5 * isr (kts ) input 3φ output 2φ isβ (kts ) = ( 3 ) * [isy (kts ) − isb(kts )] 2 d-q transformation isα (kts ) = [isd (kts ) * cos(kts)] − [isq (kts ) * sin(kts )] input 2φ output isβ (kts ) = [isd (kts ) * sin(kts )] + [isq (kts ) * cos(kts )] d-q . Functional Module Identification PI controller u (t ) = kpe(t ) + ki ∫ e(t )dt input output u (kts) = kpe(kts ) + ki ∫ e(kts ) 3-Phase to 2-Phase conversion isα (kts ) = 1.

T z + 1   z − 1  . E (z). 2  T U (z). ∫ e(t) dt S = T 2 ( z +1 z −1 ) K I U (s) = K P .(1 + z ) 2 . E (s) S U (z) = K P . . E (s) + .( z + 1) 2 −1 −1 T −1 U (z). E (z). (1 − z ) + K I . E (z) + K I . ( z − 1) + K I . E (z). . (1 − z ) = K P . ( z − 1) = K P . PI Controller Equation u (t) = K P . E (z). E (z). e (t) + K I .

E (z). ). 2 T K 2 = −K P + K I . E T 2 P T 2 I − 1 − 1 u (k) = u (k − 1) + (K P + KI . E + (− K + K .. T 2 ). e(k) + ( − K P + KI . 2 . e (k − 1) T K1 = K P + K I . T 2 ). e (k) + K 2 . e(k − 1) u (k) = u (k − 1) + K 1 . E (z) + ( − K + K + KI . T 2 ). 2 T P I .z − 1 U = U + (K P + KI .z − 1 + (K P ). U (z) = U (z). PI Controller Equation cont. ).

sp0Error skipSpError: •---------------------------------------------------------- LT sp0Error MPY kpSp .LT SPLK #kpSpeedLimit.sp0Error B skipSpError negSpError: ADD #kpSpeedLimit BCND skipSpError.LT SUB #kpSpeedLimit BCND skipSpError.e[k]*Kp PAC SACL tempA . PI Controller Software module piSpeed: SETC OVM LACC softSpeed SUB wFb .GT SPLK #-kpSpeedLimit.rotorSpeed SACL sp0Error * ---------------------------------------------------------- BCND negSpError.

16 SACH tempA LT tempA MPY Tmax PAC SACH piTorqRef.T=e[k]+e[k+1] MPY kiTorq .1 CLRC OVM RET .acc=Icon[k] LTD torq0Error . volt1Error=volt0Error SACL piTorqILo SACH piTorqIHi .P={e[k]+e[k+1]}*Ki*T/2 LACL piTorqILo ADD piTorqIHi.tempB=e[k]+e[k+1] LT tempB .16 . T=sp0Err0r.acc=e[k] ADD torq1Error .acc=e[k]+e[k+1] SACL tempB .Icon[k+1] ADD tempA.acc=Icon[k]+{e[k]+e[k+1]}*Ki*T/2.PI Controller Software module LACC torq0Error .

Structuring DSP For Power Electronics Control Timer Int. Routine Main Routine . Initialization Sampling time Sampling time Timer output To the interrupt Int.

C++. Assembly Cross compiler/ assembler Target Memory allocation for software modules Downloading and running in RAM Debugging Firmware into Flash/ EPROM .Software Development phases PC based software development C.

Software development Support Simulator – Software programs that simulate the operation of the processor No target hardware required Monitor debugger- Serial port. RS 232C Intel iaPX 86/88 .

Software development Support In Circuit Emulator. Parallel port Emulator header in target board .Emulation processor replaces Actual processor In circuit Target Emulator Board JTAG (IEEE 1149.1) Emulator – PC Add on Card.

if any Complete system working on Single supply Reduced power supply requirement Built in industrial field bus network interface CAN. Higher speed High End Integration ADC.3V instead of conventional 5V Higher level of integration.Trends in digital control Hardware Low voltage design: 3. low power. DAC. I2C . PWM .Minimize the external interface for speed compatibility No External data/ address bus and associated control lines Flash / EEPROM memory Power Down features in idle and fault condition External Lower frequency crystal 10Mhz for 40-125 Mhz Serial interface through SPI and SCI Minimum I/O s for interface.

Power Electronics Group C-DAC ( Centre for Development of Advanced Computing ) Thiruvananthapuram .