MPMC Unit 3 Latest

UNIT - III
INTERFACING WITH 8086
1
MEMORYINTERFACING WITH 8086
2
P.SATHYANARAYANA EEE SNIST
RAM(Random Access Memory)
It is a Volatile memory
Used for temporary storage
Two types
Static RAM
Dynamic RAM
Static RAM
Uses flip flops to store bit of information
Dynamic RAM
Bits stored as charge in capacitors
ROM(Read Only Memory )
It is non volatile memory and retains its content when the

power is removed
– Programmable ROM (PROM)
it is used to store programs permanently
– Erasable programmable ROM (EPROM)

– Erased by UV rays
Electrically erasable PROM (EEPROM)

– Electrically erased its content byte by byte
Flash memory
– Erase whole memory electrically

DIMENSIONS OF MEMORY
• Memory is usually measured by two numbers: its length

and its width (Length x Width)
• The length is the total number of locations
• The width is the number of bits in each location
Eg: 2048 x 8
1024 x 8
2048 x 8
NO. OF MEMORY LOCATIONS

SIZE OF EACH MEMORY LOCATION
in terms of bits

MEMORY STRUCTURE
CS CHIP SELECT
INPUT DATA
INPUT BUFFER o WR
o CS
INTERNAL DECODER
R/W MEMORY 4096 x 8 (4K x 8)

Address Lines
4096 x 8
NO. OF LOCATIONS
o
OUTPUT BUFFER
o RD
OUTPUT DATA
P.SATHYANARAYANA LOGIC
EEE DIAGRAM OF SRAM
SNIST
MEMORY STRUCTURE
2048 x 8 (2K x 8)
INTERNAL DECODER
NO. OF LOCATIONS
EPROM
Address Lines 2048 x 8
o RD
OUTPUT BUFFER
o CS
CS CHIP SELECT
OUTPUT DATA LOGIC DIAGRAM OF EPROM
MEMORY BANKS OF 8086

MEMORY BANKS IN 8086
BHE A0 ODD BANK EVEN BANK DATA LINES USED

0 0 ENABLED ENABLED D0-D15
0 1 ENABLED DISABLED D8-D15
1 0 DISABLED ENABLED D0-D7
1 1 DISABLED DISABLED HI-Z

MEMORY BANKS IN 8086

MEMORY INTERFACING TO 8086
(Static RAM and EPROM)

BASIC CONCEPTS OF MEMORY INTERFACING
Select the chip ( Enable CS )
Identify the Memory Location
Enable the appropriate buffer ( Read or Write )

Interface a 64 KB memory using the 32x 8 static RAM with the
microprocessor 8086
STEP - I
IC Available = 32K x 8
No of Address lines are Required For 64KB = 16 ( A15 – A0)
64 KB
32 KB 32 KB

A17
A18
A19
BHE
GND
M/IO
A17
A18
A19
Interface a 64 KB memory using the 32x 8
A0 static RAM with the microprocessor 8086
GND
M/IO P.SATHYANARAYANA EEE SNIST
8255 PPI
PROGRAMMABLE PERIPHERAL INTERFACE

8255 PPI (PROGRAMMABLE PERIPHERAL INTERFACE)
It is also called as programmable parallel input/output device
I/O
8255 PERIPHERAL
MICROPROCESSOR
PPI
Eg: Keyboard,
Display, ADC
DAC etc…

FEATURES OF 8255 PPI
It Requires 5v power supply
It has 2 Address Lines(A0 and A1)
It has 8 Data Lines(D0 – D7)
It has 8 bit Control word Register(CWR)
It has 24 I/O Programmable pins, which are arranged as three 8 bit ports,
those are PORT A, PORT B, PORT C
PORT A - 8 PINS/LINES(PA0 – PA7)
PORT B - 8 PINS/LINES(PB0 – PB7)
PORT C - 8 PINS/LINES(PC0 – PC7)
These 24pins are divided into 2 groups Group A and Group B and each
group has 12pins
PA0 - PA7 PB0 – PB7

Group A Group B
PC4 – PC7 PC0 – PC3

INTERNAL ARCHITECTURE OF 8255 PPI

ADDRESS LINES ALONG WITH READ ,WRITE AND CHIP SELECTION SIGNALS
RD WR A1 A0 CS INPUT OPERATION (READ)

0 1 0 0 0 PORT A to Data Bus
0 1 0 1 0 PORT B to Data Bus
0 1 1 0 0 PORT C to Data Bus
0 1 1 1 0 Illegal operation
NOTE : READ OPERATION IS NOT ALLOWED FOR CWR
ADDRESS LINES ALONG WITH READ ,WRITE AND CHIP SELECTION SIGNALS
RD WR A1 A0 CS OUTPUT OPERATION (WRITE)

1 0 0 0 0 Data Bus to PORT A
1 0 0 1 0 Data Bus to PORT B
1 0 1 0 0 Data Bus to PORT C
1 0 1 1 0 Data Bus to CWR
PIN CONFIGURATION
OF 8255 PPI

MODES OF OPERATION OF 8255 PPI
MODES OF THE 8255 PPI
BSR MODE PARALLEL I/O MODE

( PORT C )
MODE 0 MODE 1 MODE 2

( PORTS A, B, C ) ( PORTS A, B) ( PORT A)
BSR MODE Bit Set / Reset Mode

CONTROL WORD REGISTER
CWR( 8 BIT REGISTER)
D7 D6 D5 D4 D3 D2 D1 D0
D7 = 0 Bit Set Reset Mode
D7 = 1 Parallel I/O Mode

BSR MODE (Bit Set Reset Mode)
0 X X X D3 D2 D1 S/R
0 0 0 1/0 PC0
0 0 1 1/0 PC1
NOT USED 0 1 0 1/0 PC2
0 1 1 1/0 PC3
BIT SET RESET MODE 1 0 0 1/0 PC4
1 0 1 1/0 PC5
1 1 0 1/0 PC6
1 1 1 1/0 PC7
S/R SET/RESET
Write a set of instructions to set PC7 pin of the 8255 PPI having
Control word register address at 48H
Control word of 8255 PPI in BSR mode

D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 1 1 1 1 0FH
PC7
0FH 0FH
8
ACCUMULATOR CWR
8086 8255
MOV AL, 0F H ; Initialization of control word to set PC7

OUT 48H, AL ; Transfer on control word
INT 3
Write a set of instructions to set bit 4 of PORT C Assume the
address of PORT C is 16H

D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 1 0 0 1 09H
PC4
09H 09H
8
ACCUMULATOR CWR
8086 8255
MOV AL, 09 H ; Initialization of control word to set PC4

OUT 16H, AL ; Transfer on control word
INT 3
Write a set of instructions to set PC6, PC4, PC2 of PORT C and
reset them
0 x x x D3 D2 D1 S/R
SETTING OF PC6, PC4, PC2

0 0 0 0 1 1 0 1 0DH (PC6)
0 0 0 0 1 0 0 1 09H (PC4)
0 0 0 0 0 1 0 1 05H (PC2)
RESETTING OF PC6, PC4, PC2
0 0 0 0 1 1 0 0 0CH (PC6)
0 0 0 0 1 0 0 0 08H (PC4)
0 0 0 0 0 1 0 0 04H (PC2)

PARALLEL I/O MODE
D7 D6 D5 D4 D3 D2 D1 D0
1 MA1 MA0 PA PCUP MB PB PCLOW
PARALLEL I/O MODE GROUP ‘B’ CONTROL
GROUP ‘A’ MODE SELECTION PCLOW PC3 - PC0

MA1 MA0 MODE 1 INPUT
0 0 MODE 0 0 OUTPUT
0 1 MODE 1 PB PB7 - PB0
1 0 MODE 2 1 INPUT
0 OUTPUT
GROUP ‘A’ CONTROL
PA PA7 - PA0 GROUP ‘B’ MODE SELECTION
1 INPUT MB MODE
0 OUTPUT 0 MODE 0
PCUP PC7 - PC4 1 MODE 1
1 INPUT
0 OUTPUT
Write a set of instructions to perform the following
1. Port A as input in mode 0
2. Port B as output in mode 1
3. Initialize Port CHIGH as output and Port CLOW as input
The 8 bit address of the control word register CWR is 08H
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 1 0 1 0 1 95H
95H 95H
8
ACCUMULATOR CWR
8086 8255
MOV AL, 95H

OUT 08H, AL ; Initialization of control word
INT 3
Initialize the 8255 PPI to define
1. Port A output in mode 1
2. Port B input in mode 0
3. Port CLOW as output
D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 0 0 0 1 0 A2H
A2H A2H
8
ACCUMULATOR CWR
8086 8255
MOV AL, A2 H
OUT 06H, AL ; Initialization of control word
INT 3
Write an initialization sequence to define
1. Port A output in mode 0
2. Port B output in mode 1
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 0 1 0 0 84H
84H C4H
8
ACCUMULATOR CWR
8086 8255
MOV DX, 2006

MOV AL, 84 H
OUT DX, AL ; Initialization of control word
INT 3
MODE 0 OF 8255 (SIMPLE INPUT/OUTPUT MODE)
This mode is also know as basic input/output mode
In this mode PORT A, PORT B and PORT C can be programmed as

input or output
Data can be simply read from and written to the input and
output ports respectively, after appropriate initialization
8 PA7 – PA0
4 PC7 – PC4
D7 – D0 8255
8 4 PC3 – PC0
PPI
8
PB7 – PB0

8255 MODE 1 - WITH INPUT CONTROL /HAND SHAKE SIGNALS
MODE 1 PORT A
PORT A (PA0 – PA7) INPUT
PORT C (HAND SHAKE SIGNALS)
PC4 STB STROBED INPUT
PC5 IBF INPUT BUFFER FULL
PC3 INTR INTERRUPT REQUEST
PC6, PC7 BOTH PINS ARE IN I/O MODE
MODE 1 PORT B
PORT B (PB0 – PB7) INPUT
PC2 STB STROBED INPUT
PC1 IBF INPUT BUFFER FULL

MODE 1 OF 8255 (Strobed Input / Output )
STB( Strobed Input)-The strobe input loads data into the port latch, which holds the
information until it is input to the microprocessor via the IN instruction..
IBF(Input Buffer Full)-It is a active high output signal and it indicating that the
data has been loaded into the input latch
STB
8255 I/O
MICROPROCESSOR PERIPHERAL
PPI
8086 INTR
Eg: Keyboard
IBF
INPUT CONTROL SIGNAL

IBF is acknowledgment to STB signal
INTR(Interrupt request)- A High on this output can be used to interrupt
the microprocessor when an input device is requesting service
INTR is set by the STB is a one , IBF is a one and INTE is a one
8255 MODE 1 - WITH INPUT CONTROL /HAND SHAKE SIGNALS

8255 MODE 1 - WITH OUTPUT CONTROL /HAND SHAKE SIGNALS
MODE 1 PORT A
PORT A (PA0 – PA7) OUTPUT
PC7 OBF OUTPUT BUFFER FULL
PC6 ACK ACKNOWLEDGE
PC4, PC5 BOTH PINS ARE IN I/O MODE
MODE 1 PORT B
PORT B (PB0 – PB7) OUTPUT
PC2 ACK ACKNOWLEDGE
PC1 OBF OUTPUT BUFFER FULL

MODE 1 OF 8255 (Strobed Input / Output )
OBF (Output Buffer Full ): The OBF output will go “low” to indicate that the CPU
has written data out to the specified port
ACK (Acknowledge Input): A “low” on this input informs the 8255 that the data from
port A or port B has been accepted. In essence, a response from the peripheral device
indicating that it has received the data output by CPU
OBF
WR WR
8255 I/O
MICROPROCESSOR PERIPHERAL
PPI
8086 INTR
Eg: Printer
ACK
OUTPUT CONTROL SIGNAL

INTR (Interrupt Request): A “high” on the output can be used to interrupt
the CPU when an output device has accepted data transmitted by the CPU.
INTR is set when ACK is a “one”, OBF is a “one”, and INTE is a “one”.
It is reset by the falling edge of WR.
2
PC 4,5

MODE 2 OF 8255( BI-DIRECTIONAL OPERATION)
Only group A can be initialized in this mode
Port A can be used for data transfer between I/O device and microprocessor
In this mode PORT A can be used as an input or an output port
In this mode read operation can be followed by write operation or write operation can
be followed by read operation
PORT ‘A’ OF 8255 AS BI DIRECTIONAL PORT

INTERRUPT STRUCTURE OF 8086

INTERRUPT STRUCTURE OF 8086
An interrupt is a process in which microprocessor is asked to suspend

its current operations and has to execute some emergency operations
OR
An interrupt is an asynchronous signal from hardware indicating the

need for attention or a synchronous event in software indicating for a
change in execution
OR
It is a mechanism by which an I/O device ( Hardware interrupt) or an

instruction (software interrupt) can suspend the normal execution of
the processor and get it self serviced
CLASSIFICATION OF INTERRUPTS
1. HARDWARE AND SOFTWARE INTERRUPTS
2. MASKABLE AND NON MASKABLE INTERRUPTS
3. VECTOR INTERRUPTS AND NON VECTOR INTERRUPTS

HARDWARE INTERRUPT (EXTERNAL INTERRUPTS)
It is an asynchronous event
This interrupt is requested by external device
It is used to interface peripheral devices
Example : keyboard , mouse and other peripheral devices
NOTE: 8086 microprocessors support hardware interrupts through two pins

that allow interrupt requests INTR and NMI
SOFTWARE INTERRUPT (INTERNAL INTERRUPTS)

It is as synchronous event
This interrupt is requested by executing instruction
It is used in debugging
Example : INT 3H (Break point)

MASKABLE INTERRUPTS
 The maskable interrupts are the interrupts which can be ignored or masked
These interrupts can be kept pending
These interrupts are generally used to interface the peripheral devices
Example : INTR
NON MASKABLE INTERRUPTS
 A non maskable interrupt(NMI) is an interrupt that cannot be ignored or masked

 It is mostly used for attention of system for non recoverable hardware errors
These errors include power failure, emergency shutdown and data corruption
detected on system and peripheral buses
Example : NMI
VECTOR INTERRUPTS
In vector interrupts, address of interrupt service routine(ISR) is predefined by

the manufacturer of the processor
Example: NMI
NON VECTOR INTERRUPTS
In non vectored interrupts, the address of ISR needs to be supplied externally by

the device
Example: INTR

INTERRUPT SERVICE ROUTINE (ISR)
While the CPU is executing a program, an interrupt breaks the normal sequence
of execution of instructions, diverts its execution to some other program called
“Interrupt Service Routine (ISR)”
INTERRUPT RESPONSE OF 8086

INTERRUPT VECTOR TABLE OR VECTOR INTERRUPT TABLE
FFFFFH
8086 Microprocessor supports up to 256 different
interrupts
These interrupts can be implemented either hard ware

or software interrupts
In 8086 , the first 1 Kbyte of memory, from 00000H

to 003FFH, is set aside as a table for storing the starting 1 MB
addresses of Interrupt Service Routines(ISRs)
Interrupt vector table starts at the location 0000:0000H

ends at 0000:03FFH
003FFH
The 8086 has 256 interrupt vectors and since INTERRUPT
each vector is specified by 4 bytes, it implies VECTOR
TABLE
that 256 x 4 = 1024 (1kb)
( 1KB )
00000H
CS:IP
VECTOR INTERRUPT TABLE FORMAT OF 8086

8086 INTERRUPT VECTOR TABLE OR VECTOR INTERRUPT TABLE

DEDICATED INTERRUPTS
TYPE – 00H DIVIDE BY ZERO INTERRUPT
TYPE –01H SINGLE STEP INTERRUPT
TYPE – 02H NON MASKABLE INTERRUPT
TYPE –0 3H BREAK POINT INTERRUPT
TYPE – 04H OVER FLOW INTERRUPT

INTERRUPT VECTOR TABLE
Find the Physical Address in interrupt vector table associated with
(a) INT 13 (b) INT 08
a) Physical Address of INT 13 is

13*4 = 52 = 34H
Memory Address is 00034H to 00037H
b) Physical Address of INT 08 is

08*4 = 32 = 20H

INTERRUPT VECTOR TABLE
Find the Physical Address in interrupt vector table associated with
INT 61H and ISR corresponding to this vector is 0F00:9872
a) Physical Address of INT 61H = 97(decimal) is

97*4 = 388(decimal) = 184H
00187H 0FH
00186H 00H
00185H 98H
00184H 72H

INTRODUCTION TO DOS AND BIOS INTERRUPTS

INTRODUCTION TO DOS AND BIOS INTERRUPTS
INT 21H - DOS INTERRUPT
INT 10H – BIOS INTERRUPT

INT 21H - DOS FUNCTION CODES

DOS INTERRUPT 21H
FUNCTION 2
– Write a character to standard output device
Registers used:
AH = 2
DL = the character to be displayed.
Example:
MOV AH, 2
MOV DL, ’A’
INT 21H

DOS INTERRUPT 21H
FUNCTION 01
– Read a character from standard input device
Registers used:
AH = 1
Example:
MOV AH, 1
INT 21H
MOV MEM, AL

DOS INTERRUPT 21H
FUNCTION 9
Display the String (terminated by a $ )
Registers used:
AH = 9
DX = the offset address of the data to be displayed.
Example:
STR DB “ EEE_STUDENTS$ ”
MOV DX, OFFSET STR

MOV AH, 09
INT 21H

INT 10H - BIOS FUNCTION CODES

FUNCTION 0
This function is for setting video mode

Function number is placed in AH and video mode is placed in AL
Example :
MOV AH, 00H ; set the function number

MOV AL, 03H ; mode 3, standard text mode
INT 10H

FUNCTION 2H
• It Set the cursor Position

• Registers used:
– AH = 2H
– BH = Page Number
– DH = Row position.
– DL = Column position.
Example:
MOV AH, 2H
MOV BH, 0H
MOV DH,12H
MOV DL, 39H
INT 10H

8259A PROGRAMMABLE INTERRUPT CONTROLLER

FEATURES 8259A PROGRAMMABLE INTERRUPT CONTROLLER
It can handle 8 hardware interrupts

It can Resolve the priority of these 8 hardware interrupts
It can be programmed to accept either level triggered or
edge trigged interrupt request
Interrupts can be masked independently
It provides the status of pending interrupts, masked interrupts and
interrupts being serviced
It does not require any clock signal
It can be cascaded in master slave configuration to implement 64
levels of interrupts
It is compatible with 8-bit as well as 16-bit micro processors

It includes eight blocks
They are:
1.Data bus buffer

2.Read/Write logic
3.Control logic
4.Interrupt Request Register (IRR)
5.In-Service Register (ISR)
6.Interrupt Mask Register (IMR)
7.Priority Resolver (PR)
8.Cascade buffer/Comparator
ARCHITECTURE OF 8259A PROGRAMMABLE INTERRUPT CONTROLLER

INTERRUPT REQUEST REGISTER (IRR)
 It is a 8 bit Register
IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0

1 0 0 1 0 1 0 1
When an interrupt occurs, the interrupt request register(IRR) will set the
corresponding bit
Given example 4 interrupts are occurs ( IR0, IR2, IR4, IR7)

INTERRUPT MASK REGISTER(IMR)
 It is a 8 bit Register
D7 D6 D5 D4 D3 D2 D1 D0
M7 M6 M5 M4 M3 M2 M1 M0
M7 – M0 Represent the eight mask bits for the IR7 – IR0
M = 1 indicates interrupt request(IR) input is masked

M = 0 indicates interrupt request(IR) input is un masked

CASCADING DIAGRAM OF 8259A PROGRAMMABLE INTERRUPT CONTROLLER

PIN CONFIGURATION OF 8259A PROGRAMMABLE INTERRUPT CONTROLLER

OPERATING MODES OF 8259A PIC
FULLY NESTED MODE
SPECIFIC ROTATION PRIORITY MODE
AUTOMATIC ROTATION PRIORITY MODE
SPECIAL FULLY NESTED MODE
POLLED MODE

FULLY NESTED MODE
This mode is also called as default mode or fixed priority mode

The interrupts are arranged from highest to lowest, with IR0 as the highest
priority and IR7 as the lowest priority

7 6 5 4 3 2 1 0
LOWEST PRIORITY HIGHEST PRIORITY

SPECIFIC ROTATION PRIORITY MODE
In this mode a lowest priority level can be selected
Selected lowest priority fixes other priorities
If IR5 is selected as a lowest priority , IR4 will have a next higher priority and
IR6 will have highest priority

1 0 7 6 5 4 3 2
LOWEST PRIORITY
HIGHEST PRIORITY

AUTOMATIC ROTATION PRIORITY MODE
 This mode is used in the applications where all interrupting devices are equal
priority
 In this mode, a device after being serviced, receives the lowest priority
For example:
If IR2 has highest priority, then IR2 is serviced and this serviced IR2
assigns the lowest priority and other priorities are rotate correspondingly

5 4 3 2 1 0 7 6 STARTING
4 3 2 1 0 7 6 5 IR2 SERVICED
3 2 1 0 7 6 5 4 IR3 SERVICED
SPECIAL FULLY NESTED MODE
 The special fully nested mode(SFNM) is used in cascade mode

 It is designed only for the master 8259 PIC
This mode is similar to fully nested mode
When an interrupt request from a slave is being serviced, master will not recognize
further interrupt request on the same input level in case of Fully Nested
Mode(because further interrupts on the same input level are disabled by master)
Special fully nested mode is used to void suchEEEproblem
P.SATHYANARAYANA SNIST
POLLED MODE
 In this mode INT output pin of 8259A is not used

 Microprocessor checks the status of interrupt request by issuing polled command

POLLED MODE
POLLED WORD
D7 D6 D5 D4 D3 D2 D1 D0
I X X X X W2 W1 W0
If I = 1 there is an interrupt Request

I = 0 there is no interrupt Request Binary code of highest
priority level
For example:
IR5 has highest priority, then polled word is
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 0 1 0 1 85H

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UNIT - III

INTERFACING WITH 8086

Used for temporary storage

It is non volatile memory and retains its content when the

– Erasable programmable ROM (EPROM)

Electrically erasable PROM (EEPROM)

P.SATHYANARAYANA EEE SNIST

• Memory is usually measured by two numbers: its length

NO. OF MEMORY LOCATIONS

P.SATHYANARAYANA EEE SNIST

R/W MEMORY 4096 x 8 (4K x 8)

SIZE OF EACH MEMORY LOCATION

P.SATHYANARAYANA EEE SNIST

BHE A0 ODD BANK EVEN BANK DATA LINES USED

P.SATHYANARAYANA EEE SNIST

P.SATHYANARAYANA EEE SNIST

P.SATHYANARAYANA EEE SNIST

Select the chip ( Enable CS )

Identify the Memory Location

Enable the appropriate buffer ( Read or Write )

P.SATHYANARAYANA EEE SNIST

P.SATHYANARAYANA EEE SNIST

P.SATHYANARAYANA EEE SNIST

It is also called as programmable parallel input/output device

P.SATHYANARAYANA EEE SNIST

PA0 - PA7 PB0 – PB7

PC4 – PC7 PC0 – PC3

P.SATHYANARAYANA EEE SNIST

RD WR A1 A0 CS INPUT OPERATION (READ)

RD WR A1 A0 CS OUTPUT OPERATION (WRITE)

P.SATHYANARAYANA EEE SNIST

MODES OF THE 8255 PPI

BSR MODE PARALLEL I/O MODE

MODE 0 MODE 1 MODE 2

BSR MODE Bit Set / Reset Mode

P.SATHYANARAYANA EEE SNIST

CWR( 8 BIT REGISTER)

D7 = 0 Bit Set Reset Mode

D7 = 1 Parallel I/O Mode

P.SATHYANARAYANA EEE SNIST

Control word of 8255 PPI in BSR mode

MOV AL, 0F H ; Initialization of control word to set PC7

Control word of 8255 PPI in BSR mode

MOV AL, 09 H ; Initialization of control word to set PC4

Control word of 8255 PPI in BSR mode

SETTING OF PC6, PC4, PC2

P.SATHYANARAYANA EEE SNIST

PARALLEL I/O MODE GROUP ‘B’ CONTROL

GROUP ‘A’ MODE SELECTION PCLOW PC3 - PC0

MOV AL, 95H

MOV DX, 2006

In this mode PORT A, PORT B and PORT C can be programmed as

P.SATHYANARAYANA EEE SNIST

P.SATHYANARAYANA EEE SNIST

INPUT CONTROL SIGNAL

P.SATHYANARAYANA EEE SNIST

P.SATHYANARAYANA EEE SNIST

OUTPUT CONTROL SIGNAL

P.SATHYANARAYANA EEE SNIST

In this mode PORT A can be used as an input or an output port

PORT ‘A’ OF 8255 AS BI DIRECTIONAL PORT

P.SATHYANARAYANA EEE SNIST

An interrupt is a process in which microprocessor is asked to suspend