Pipeline Hazards: Data

Dependency
Microprocessor & Computer Architecture
Dr. M Faisal Iqbal
Pipelining Issues
• Instruction Pipeline stalls because of the following issues
• Data Dependence
• Memory Delays
• Branch Delays
Data Dependence
• Independent operations
• I1: Add R3, R2, R1
• I2: Add R5, R4, R6

• Dependent Operations
• I1: Add R3, R2, R1
• I2: Sub R4, R3, 30

1 2 3 4 5 6 7 8 9
I1: F D E M W
I2: F D D D D E M W
I3: F F F F D C M
Resolution of Data Dependence
• Software Technique
• Hardware Interlock
• Data Forwarding
Handling Data Dependence in Software
• Compiler detects data dependence between two successive
instructions and inserts explicit NOP (No-operation) instruction
between them
• Following sequence of instructions is generated
• I1: Add R3,R2,R1
• I2: NOP 1 2 3 4 5 6 7 8 9
Add R3,R2,R1 F D C M W
• I3: NOP
NOP F D C M W
• I4: NOP
NOP F D C M W
• I5: Sub R4, R3, 30 NOP F D C M W
• + Simplifies hardware Sub R4, R3, 30 F D C M W
• - code size increases
• - Execution time not reduced
 Hardware Interlock
• Hardware inserts NOP between dependent instructions
• C1: I1 is fetched and put in B1
• C2: I1 moves to B2, I2 moves to B1
• C3: I2 tries to read regs but … should not
• Contents of B1 should not change
• B2 should get a NOP
• PC should not get incremented
PC PC

+
4
Insn Register A
y
I1: Add R3,R2,R1 PC Z
Mem File Data
I2: Sub R4, R3, 30 s1 s2 d
B M
Mem
PC IR
IR
IR IR
B1(D) B2(E) B3(M) B4(W)
Hardware Interlock

PC PC

+
4

Insn Register A
PC y
Mem File Z Data
s1 s2 d B Mem
M
IR
IR IR IR
PC_enable
NOP
B2(E) B3(M) B4(W)

Interlock
Bypassing
A
Register Y
Z a
File B Data
s1 s2 d
M dMem
S
X

IR IR IR IR

add R4,R3,30 add R3,R2,R1

• Bypassing
• Reading a value from an intermediate (marchitectural) source
• Not waiting until it is available from primary source
• Here, we are bypassing the register file
• Also called forwarding
WC Bypassing

A
Register Y
Z a
File B Data
s1 s2 d
M dMem
D C S M
X
W

IR IR IR IR

add R4,R3,R2 add R3,R2,R1

• What about this combination?

• Add another bypass path and MUX (multiplexor) input
• First one was an MC bypass
• This one is a WC bypass
ALUinB Bypassing
A

D Register
Z a Y
File B Data
s1 s2 d
M dMem
C S M W
X

IR IR IR IR

add R4,R2,R3 add R3,R2,R1

• Can also bypass to ALU input B

WM Bypassing?

A
Register Y
Z a
File B Data
s1 s2 d
M dMem
D C S M W
X

IR IR IR IR

store R4,[R3+4] load R3,[R2+8]

• Does WM bypassing work?

• Not to the address input (why not?)
store R4,[R3+4] load R3,[R2+8]
X
• But to the store data input, yes
store R3,[R4+4] load R3,[R2+8]
Bypassing Logic

A
Register Y
Z a
File B Data
s1 s2 d
M dMem
D X S
X
W
M
IR IR IR IR

bypass

• Each multiplexer has its own logic, here it is for ALUinA

(X.IR.RegSrc1 == M.IR.RegDest) => 0
(X.IR.RegSrc1 == W.IR.RegDest) => 1
Else => 2