Getting Started with PICmicro® Mid-Range

Architecture, Instruction Set and Assembly Language Programming

101 ASP

© 2005 Microchip Technology Incorporated. All Rights Reserved.

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Class Objective
When you finish this class you will:
− Understand the basics of the inner workings of a PIC16 − Understand most instructions − Understand memory organization − Understand how to write simple programs
© 2006 Microchip Technology Incorporated. All Rights Reserved. 101 ASP

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Agenda
q q q q q

Architecture Basics Instruction Set Overview Memory Organization and Addressing Modes Special Features Hands-on Exercises

© 2006 Microchip Technology Incorporated. All Rights Reserved.

101 ASP

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All Rights Reserved.Architecture q The high performance of the PICmicro® microcontroller can be attributed to the following architectural features: − Harvard Architecture − Instruction Pipelining − Large Register File − Single Cycle Instructions − Single Word Instructions − Long Word Instructions − Reduced Instruction Set − Orthogonal Instruction Set © 2006 Microchip Technology Incorporated. 101 ASP Slide 4 .

Harvard Architecture Von Neumann Architecture q Von Neumann Architecture: − Fetches instructions and data from a single memory space Limits operating bandwidth 8-bit Bus CPU Harvard Architecture Program & Data M ory em − q Harvard Architecture: − Uses two separate memory spaces for program instructions and data Improved operating bandwidth Allows for different bus widths Slide 5 Program Mem ory 14 -bit Bus CPU 8-bit Bus Data Mem ory − − © 2006 Microchip Technology Incorporated. 101 ASP . All Rights Reserved.

w 54 return © 2006 Microchip Technology Incorporated.Instruction Pipelining q Instruction fetch is overlaped with execution of previously fetched instruction Instruction Cycles T2 T3 T4 Example Program 1 MAIN movlw 0x05 2 movwf REG1 3 call SUB1 4 addwf REG2 T0 T1 T5 T6 T7 Fetch Execute Fetch Execute Time to execute normal instruction Time to execute call instruction includes pipeline flush Fetch Execute Fetch Flush Fetch 51 SUB1 movf PORTB. 101 ASP Fetch Execute Fetch Execute Fetch Flush Slide 6 . All Rights Reserved.w 52 return 53 SUB2 movf PORTC.

101 ASP Slide 7 .w 52 return 53 SUB2 movf PORTC.w 54 return © 2006 Microchip Technology Incorporated. All Rights Reserved.Pre-Fetched Instruction Instruction Pipelining Executing Instruction movlw 0x05 Instruction Cycles Example Program 1 MAIN movlw 0x05 2 movwf REG1 3 call SUB1 4 addwf REG2 T0 Fetch 51 SUB1 movf PORTB.

w 52 return 53 SUB2 movf PORTC.Pre-Fetched Instruction Instruction Pipelining Executing Instruction movwf REG1 movlw 0x05 Instruction Cycles Example Program 1 MAIN movlw 0x05 2 movwf REG1 3 call SUB1 4 addwf REG2 T0 T1 Fetch Execute Fetch 51 SUB1 movf PORTB. All Rights Reserved. 101 ASP Slide 8 .w 54 return © 2006 Microchip Technology Incorporated.

w 54 return © 2006 Microchip Technology Incorporated.Pre-Fetched Instruction Instruction Pipelining Executing Instruction call SUB1 movwf REG1 Instruction Cycles Example Program 1 MAIN movlw 0x05 2 movwf REG1 3 call SUB1 4 addwf REG2 T0 T1 T2 Time to execute normal instruction Fetch Execute Fetch Execute Fetch 51 SUB1 movf PORTB. All Rights Reserved.w 52 return 53 SUB2 movf PORTC. 101 ASP Slide 9 .

All Rights Reserved.Pre-Fetched Instruction Instruction Pipelining Executing Instruction addwf REG2 call SUB1 Instruction Cycles Example Program 1 MAIN movlw 0x05 2 movwf REG1 3 call SUB1 4 addwf REG2 T0 T1 T2 T3 Fetch Execute Fetch Execute Fetch Execute Fetch 51 SUB1 movf PORTB.w 54 return © 2006 Microchip Technology Incorporated.w 52 return 53 SUB2 movf PORTC. 101 ASP Slide 10 .

Pre-Fetched Instruction Instruction Pipelining Executing Instruction movf PORTB.w 52 return 53 SUB2 movf PORTC. 101 ASP Fetch Slide 11 . All Rights Reserved.w 54 return © 2006 Microchip Technology Incorporated.w call SUB1 Instruction Cycles Example Program 1 MAIN movlw 0x05 2 movwf REG1 3 call SUB1 4 addwf REG2 T0 T1 T2 T3 T4 Fetch Execute Fetch Execute Fetch Execute Fetch Flush Time to execute call instruction includes pipeline flush 51 SUB1 movf PORTB.

101 ASP Fetch Execute Fetch Slide 12 .w 54 return © 2006 Microchip Technology Incorporated. All Rights Reserved.Pre-Fetched Instruction Instruction Pipelining Executing Instruction return movf PORTB.w 52 return 53 SUB2 movf PORTC.w Instruction Cycles Example Program 1 MAIN movlw 0x05 2 movwf REG1 3 call SUB1 4 addwf REG2 T0 T1 T2 T3 T4 T5 Fetch Execute Fetch Execute Fetch Execute Fetch Flush 51 SUB1 movf PORTB.

Pre-Fetched Instruction Instruction Pipelining Executing Instruction movf PORTC.w return Instruction Cycles Example Program 1 MAIN movlw 0x05 2 movwf REG1 3 call SUB1 4 addwf REG2 T0 T1 T2 T3 T4 T5 T6 Fetch Execute Fetch Execute Fetch Execute Fetch Flush 51 SUB1 movf PORTB.w 52 return 53 SUB2 movf PORTC. 101 ASP Fetch Execute Fetch Execute Fetch Slide 13 .w 54 return © 2006 Microchip Technology Incorporated. All Rights Reserved.

Pre-Fetched Instruction Instruction Pipelining Executing Instruction addwf REG2 return Instruction Cycles Example Program 1 MAIN movlw 0x05 2 movwf REG1 3 call SUB1 4 addwf REG2 T0 T1 T2 T3 T4 T5 T6 T7 Fetch Execute Fetch Execute Fetch Execute Fetch Flush Fetch 51 SUB1 movf PORTB. 101 ASP Fetch Execute Fetch Execute Fetch Flush Slide 14 .w 52 return 53 SUB2 movf PORTC.w 54 return © 2006 Microchip Technology Incorporated. All Rights Reserved.

All Rights Reserved. Slide 15 .Long Word Instruction 8-bit Program Memory 8-bit Instruction on typical 8-bit MCU Example: Freescale ‘Load Accumulator A’: • 2 Program Memory Locations • 2 Instruction Cycles to Execute ldaa #k 1 0 0 0 0 1 1 0 k k k k k k k k q q Limits Bandwidth Increases Memory Size Requirements 14-bit Program Memory 14-bit Instruction on PIC16 8-bit MCU Example: ‘Move Literal to Working Register’ • 1 Program Memory Location • 1 Instruction Cycle to Execute movlw k 1 1 0 0 0 0 k k k k k k k k q q Separate busses allow different widths 2k x 14 is roughly equivalent to 4k x 8 101 ASP © 2006 Microchip Technology Incorporated.

so any location in data memory may be operated on directly All peripherals are mapped into data memory as a series of registers Orthogonal Instruction Set: ALL instructions can operate on ANY data memory location The Long Word Instruction format allows a directly addressable register file d q w f q W 10h q Decoded Instruction from Program Memory: Opcode d Address Address of Second Source Operand Arithmetic/Logic Function to be Performed Result Destination © 2006 Microchip Technology Incorporated. 101 ASP Slide 16 .Register File Concept Data Memory (Register File) w f 07h 08h 09h q ALU Data Bus 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh Register File Concept: All of data memory is part of the register file. All Rights Reserved.

Instruction Set Overview Byte Oriented Operations 13 8 7 6 0 Opcode Opcode f d f f f f f f f f f f f f f File Register Address Destination (W or F) ADDWF 0x25. W File Register Address © 2006 Microchip Technology Incorporated. 101 ASP Destination Slide 17 . All Rights Reserved.

All Rights Reserved. 3 Bit Position Slide 18 101 ASP File Register Address . 0x25.Instruction Set Overview Bit Oriented Operations 13 10 9 7 6 0 Opcode b b b f Bit Position (0-7) f f f f f f File Register Address BSF © 2006 Microchip Technology Incorporated.

101 ASP Slide 19 .Instruction Set Overview Literal and Control Operations 13 10 8 7 0 Opcode Opcode k k k k k k k k Opcode k k k k k k k k k k k Literal Value MOVLW 0x55 Literal Value © 2006 Microchip Technology Incorporated. All Rights Reserved.

d f. All Rights Reserved.b f. Skip if Clear Bit Test f.d f.d f.d f.b k k k k k k k k k Bit Clear f Bit Set f Bit Test f.d f.d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f.b f.d f f. Skip if 0 Increment f Increment f.d f.d f.b f.PIC16 Instruction Set Byte Oriented Operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f.d f f.d f. .d f. Skip if Set Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W Slide 20 Literal and Control Operations © 2006 Microchip Technology Incorporated. Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw 101 ASP Bit Oriented Operations bcf bsf btfsc btfss f.d f.d f.

Execute Reset Literal Data from Instruction Word Address w d ALU f FF FF FF 18 FF FF FF FF FF FF 101 ASP w f FF W Register © 2006 Microchip Technology Incorporated. þÿ Data Bus Register File .PIC16 Visual Interpreter þÿADDLW Hex Dec Bin þÿ0x0A . All Rights Reserved. 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh STATUS 2 1 0 1 0 0 Z DC C Slide 21 .

Data Memory Organization PIC16F876/877 Register File Map 368 Bytes of General Purpose RAM Plus Special Function Registers 000h SFR 080h SFR 100h 10Fh 110h SFR 180h 18Fh 190h SFR 01Fh 020h 09Fh 0A0h 128 Bytes GPR 96 Bytes GPR 80 Bytes GPR 96 Bytes GPR 96 Bytes 0EFh 07Fh 0FFh 16Fh 1EFh Accesses 70h – 7Fh Bank 1 17Fh Accesses 70h – 7Fh Bank 2 1FFh Accesses 70h – 7Fh Bank 3 Slide 22 Bank 0 © 2006 Microchip Technology Incorporated. 101 ASP . All Rights Reserved.

Data Memory Organization Bank 0 000 001 002 003 004 005 006 007 008 009 00A 00B 00C 00D INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD PORTE PCLATH INTCON PIR1 PIR2 080 081 082 083 084 085 086 087 088 089 08A 08B 08C 08D Bank 1 INDF OPTION_REG PCL STATUS FSR TRISA TRISB TRISC TRISD TRISE PCLATH INTCON PIE1 PIE2 100 101 102 103 104 105 106 107 108 109 10A 10B 10C 10D PCLATH INTCON EEDATA EEADR PORTB Bank 2 INDF TMR0 PCL STATUS FSR 180 181 182 183 184 185 186 187 188 189 18A 18B 18C 18D PCLATH INTCON EECON1 EECON2 TRISB Bank 3 INDF OPTION_REG PCL STATUS FSR Device Specific Registers © 2006 Microchip Technology Incorporated. 101 ASP Slide 23 . All Rights Reserved.

01 = Bank 1. 11 = Bank 3 TO: Time-out bit 0 = A WDT time-out occurred PD: Power-down bit 0 = SLEEP instruction executed Z: Zero bit 1 = Result of arithmetic operation is zero DC: Digit cary / borrow bit 1 = Carry out of 4th low order bit occurred / No borrow occurred C: Carry / borrow bit 1 = Carry out of MSb occurred / No borrow occurred © 2006 Microchip Technology Incorporated. 1 1 = Bank 2. All Rights Reserved. 10 = Bank 2. 101 ASP Slide 24 . 3 RP1:RP0: Register Bank Select Bits (used for direct addressing) 00 = Bank 0.STATUS Register IRP bit 7 RP1 RP0 TO PD Z DC C bit 0 IRP: Register Bank Select (used for Indirect addressing) 0 = Bank 0.

All Rights Reserved. <d> <constant> − Immediate (Literal) movlw q Program Memory Access: − Absolute − Relative goto <program_address> addwf PCL.f © 2006 Microchip Technology Incorporated. <d> INDF. 101 ASP Slide 25 .PIC16 Addressing Modes q Data Memory Access: − Directaddwf − Indirect addwf <data_address>.

Register Direct Addressing 2-bits from STATUS Register 7-bits Encoded in Instruction 9-bit Effective Address (Use this when coding) 0 0 RP1 RP0 0 0 0 0 0 0 0 ‘f’ Operand 0x183 Bank 3 FF FF FF 1C FF FF FF FF FF FF FF FF Register File Address Bus Bank 0 00h 01h 02h 03h 04h 05h 7Ah 7Bh 7Ch 7Dh 7Eh 7Fh FF FF FF Bank 1 Bank 2 FF FF FF 18 FF FF Address FF FF FF FF FF FF 101 ASP FF FF FF FF FF FF © 2006 Microchip Technology Incorporated. Slide 26 . All Rights Reserved.

RP0 b’11110000’ TRISB STATUS. All Rights Reserved.RP0 PORTB FF FF FF FF FF FF 38 38 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF Bin Dec FF FF FF 38 38 FF FF FF FF FF FF FF FF Hex © 2006 Microchip Technology Incorporated.Register Direct Addressing Example: Initialize bits 0-3 of PORTB as outputs W Register: Address INDF: 00h TMR0: 01h PCL : 02h STATUS: 03h FSR: 04h PORTA: 05h PORTB: 06h PORTC: 07h 20h 21h 22h 23h Register File Bank 0 Bank 1 Address 80h : INDF: 81h OPTION 82h : PCL : 83h STATUS 84h : FSR : 85h TRISA 86h : TRISB 87h : TRISC A0h A1h A2h A3h F0 9-Bit Effective Address: 0 1 0 RP1 RP0 0 0 0 0 0 0 0 0 0 0 0 0 7-bits from Instruction bsf movlw movwf bcf clrf STATUS. 101 ASP Slide 27 .

1-bit from STATUS Register Register Indirect Addressing 8-bits from FSR Register FSR 9-bit Effective Address (Use this when coding) 0 IRP 0 0 0 0 0 0 0 0 Bank 0. .3 FF FF FF 1C FF FF FF FF FF FF FF FF Slide 28 FF FF FF FF FF FF FF Register File Address Bus © 2006 Microchip Technology Incorporated.1 000h 001h 002h 003h 004h 005h 0FAh 0FBh 0FCh 0FDh 0FEh 0FFh 100h 101h 102h 103h 104h 105h 1FAh 1FBh 1FCh 1FDh 1FEh 1FFh 101 ASP 0x1FC Bank 2. All Rights Reserved.

All Rights Reserved.Register Indirect Addressing Example: Clear all RAM locations from 20h to 7Fh W Register: Register File Address 20 9-Bit Effective Address: 0 IRP 0 0 0 0 0 0 0 0 FSR 00 FF FF 18 80 00 00 00 00 00 00 00 FF 00h : INDF 01h : TMR0 02h : PCL 03h : STATUS 04h : FSR 20h 21h 22h 23h 7Dh 7Eh 7Fh 80h bcf STATUS. 101 ASP Slide 29 .f btfss FSR.7 goto LOOP <next instruction> © 2006 Microchip Technology Incorporated.IRP movlw 0x20 movwf FSR LOOP clrf INDF incf FSR.

Program Memory Organization q Program memory is divided into four 2k×14 pages Required to maintain single word/single cycle execution Paging is only a concern when using the call or goto instructions. 0000h 0004h 14-bits Reset Vector Interrupt Vector 2k Page 0 PCH = 00h 0800h q Page 1 PCH = 08h 1000h 2k q Page 2 PCH = 10h 1800h 2k Page 3 PCH = 18h 1FFFh 101 ASP 2k Slide 30 . All Rights Reserved. or when directly modifying the program counter © 2006 Microchip Technology Incorporated.

RETFIE Any instruction that uses the PCL register as an operand © 2006 Microchip Technology Incorporated. RETURN.Program Counter PCH 12 11 10 9 8 7 6 5 PCL 4 3 2 1 0 Program Counter q q q q q q 0 0 0 0 0 0 0 0 0 0 0 0 0 13-bit PC can access up to 213 = 8192 words Contains address of NEXT instruction (pipelining) Lower byte accessible in data memory as PCL Upper byte indirectly accessible via PCLATH Runs freely across page boundaries Events that modify PC out of sequence: − − − Interrupts Instructions: CALL. RETLW. 101 ASP Slide 31 . All Rights Reserved. GOTO.

PC Absolute Addressing CALL and GOTO Instructions: 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Opcode 0 0 0 0 0 0 0 0 0 0 0 q PC Absolute Addressing (Program Memory) − − Jump to another program memory location out of PC sequence Call a subroutine 11-bits of the required 13 address bits are encoded in the instruction 2 additional bits will come from the PCLATH register Address to jump to is calculated by the program Computed address is written directly into the Program Counter q Used by the CALL and GOTO instructions − − q Used when performing Computed Goto operation − − © 2006 Microchip Technology Incorporated. All Rights Reserved. 101 ASP Slide 32 .

PC Absolute Addressing 14-Bit CALL or GOTO Instruction in Program Memory 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Opcode PCLATH Register in Data Memory 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 - - - 0 0 0 0 0 2-Bits From PCLATH 12 11 10 9 8 7 6 5 11-Bits From Instruction 4 3 2 1 0 0 0 0 PCH PCH 0 0 0 0 0 0 0 0 0 0 PCL PCL 13-Bit Program Counter © 2006 Microchip Technology Incorporated. All Rights Reserved. 101 ASP Slide 33 .

PC Absolute Addressing Example: Jumping to code located in a different program memory page. All Rights Reserved.PCH:PCL FF - 0 0 0 0 0 0 0 0 0 0 0 0 0 MySubroutine org 0x0020 movlw HIGH MySubroutine movwf PCLATH call MySubroutine … org 0x1250 <do something useful> … return 101 ASP © 2006 Microchip Technology Incorporated. Slide 34 . PCLATH Register 7 6 5 4 3 2 1 0 CALL Instruction in Program Memory 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - 0 0 0 0 0 Opcode 0 0 0 0 0 0 0 0 0 0 0 W Register Program Counter .

2 PORTB.3 MySub2 13-bit x 8-Level Return Address Stack 13-bit Program Counter 0020 0 1 2 3 4 5 6 7 MySub1 MySub2 MySub3 MySub4 © 2006 Microchip Technology Incorporated. 101 ASP Slide 35 .0 MySub2 PORTB.7 PORTB.CALL / RETURN Stack 0020 0021 0022 0023 0024 … 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 100A movlw movwf call call bsf … bsf call return bsf call return bsf return bsf call return HIGH MySub1 PCLATH MySub1 MySub4 PORTB.1 MySub3 PORTB. All Rights Reserved.

PC Relative Addressing W Register To write to PC:  Write high byte to PCLATH  Write low byte to PCL (PCH will be loaded with value from PCLATH) PCLATH FF 8-bit Data Bus FF PCH PCL FF FF movlw movwf movlw movwf HIGH 0x1250 PCLATH LOW 0x1250 PCL © 2006 Microchip Technology Incorporated. 101 ASP Slide 36 . All Rights Reserved.

PIC® MCU 101 ASP Slide 37 .7 = F8 retlw b’10000000’ .6 = 82 retlw b’11111000’ .4 = 99 retlw b’10010010’ .5 retrieve the bit pattern to call SevenSegDecode movwf PORTB display a digit on a 7segment LED … ORG 0x1800 .5 = 92 retlw b’10000010’ .f retlw b’11000000’ .9 = 90 © 2006 Microchip Technology Incorporated.Page 3 SevenSegDecode: addwf PCL.Page 0 movlw HIGH SevenSegDecode Example: Use a lookup table movwf PCLATH with relative addressing to movlw .0 = C0 retlw b’11111001’ .2 = A4 retlw b’10110000’ . All Rights Reserved.8 = 80 retlw b’10010000’ .1 = F9 retlw b’10100100’ .PC Relative Addressing: Lookup Table ORG 0x0020 .3 = B0 retlw b’10011001’ .

Special Features Overview © 2005 Microchip Technology Incorporated. Slide 38 . All Rights Reserved.

Configuration Word
CP bit 1 DEBUG WRT1 WRT0 CPD LVP BOREN PWRTEN WDTEN FOSC1 FOSC0 bit 0

q

Located in program memory space, outside the reach of the program counter Used to setup device options:
− − − − − − − Code Protection Oscillator Mode Watchdog Timer Power Up Timer Brown Out Reset Low Voltage Programming Flash Program Memory Write

q

q

Only readable at program time on most PIC16 devices
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© 2006 Microchip Technology Incorporated. All Rights Reserved.

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PIC16 Oscillator Options
XT HS LP RC INTRC
q

Standard frequency crystal oscillator Standard frequency High frequency crystal oscillator High frequency crystal oscillator Low frequency crystal oscillator Low frequency crystal oscillator External RC oscillator External RC oscillator Internal RC oscillator Internal RC oscillator

100kHz - 4MHz 4MHz - 20MHz 5kHz - 200kHz DC - 4MHz 4 or 8 MHz ± 2% or MHz ±

Selectable clock options provide greater flexibility for the designer:
− − − − LP Oscillator designed to draw least amount of current RC or INTRC provide ultra low cost oscillator solution XT optimized for most commonly used oscillator frequencies HS optimized to drive high frequency crystals or resonators

q

Speed ranges are guidelines only
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© 2006 Microchip Technology Incorporated. All Rights Reserved.

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POR, OST, PWRT
q

POR: Power On Reset
− With MCLR tied to VDD , a reset pulse is generated when VDD rise is detected Device is held in reset for 72ms (nominal) to allow VDD to rise to an acceptable level (after POR only) Holds device in reset for 1024 cycles to allow crystal or resonator to stabilize in frequency and amplitude; not active in RC modes; used only after POR or Wake Up from SLEEP

VDD MCLR TPWRT PWRT TOST OST

q

PWRT: Power Up Timer

q

OST: Oscillator Start-up Timer

Reset

Execut

© 2006 Microchip Technology Incorporated. All Rights Reserved.

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0µ A typical) Events that wake processor from sleep MCLR WDT INT TMR1 ADC CMP CCP PORTB SSP PSP Master Clear Pin Asserted (pulled low) Watchdog Timer Timeout INT Pin Interrupt Timer 1 Interrupt (or also TMR3 on PIC18) A/D Conversion Complete Interrupt Comparator Output Change Interrupt Input Capture Event PORTB Interrupt on Change 2 Synchronous Serial Port (I2C Mode) Start / Stop Bit Detect Interrupt Parallel Slave Port Read or Write 101 ASP © 2006 Microchip Technology Incorporated. Slide 42 .2.1 . All Rights Reserved.Sleep Mode q The processor can be put into a power-down mode by executing the SLEEP instruction − − − − System oscillator is stopped Processor status is maintained (static design) Watchdog timer continues to run.mostly due to leakage (0. if enabled Minimal supply current is drawn .

All Rights Reserved. 101 ASP 8:1 Mux WDT Timeou Slide 43 .0s typical Operates in SLEEP.Watchdog Timer q q q q q q q Helps recover from software malfunction Uses its own free-running on-chip RC oscillator WDT is cleared by CLRWDT instruction Enabled WDT cannot be disabled by software WDT overflow resets the chip Programmable timeout period: 18ms to 3. on time out. wakes up CPU WDT Ripple Counter Postscaler WDTEN Configuration Bit © 2006 Microchip Technology Incorporated.

All Rights Reserved. the device is held in reset Prevents erratic or unexpected operation Eliminates need for external BOR circuitry q q © 2006 Microchip Technology Incorporated.BOR –Brown Out Reset q When voltage drops below a particular threshold. 101 ASP Slide 44 .

use an external supervisor (MCP1xx. All Rights Reserved. or TC12xx) 101 ASP © 2006 Microchip Technology Incorporated.5V q q For other thresholds.5V – Minimum VDD for OTP PICmicro® MCUs − 2. MCP8xx/TCM8xx.7V − 4.PBOR – Programmable Brown Out Reset q Configuration Option (set at program time) − Cannot be enabled / disabled in software Four selectable BVDD trip points: − 2.2V − 4. Slide 45 .

All Rights Reserved.(P)BOR – Brown Out Reset q Holds PICmicro® MCU in reset until ~72ms after VDD rises back above threshold VDD 72ms Internal Reset BVDD VDD BVDD 72ms Internal Reset <72ms VDD 72ms Internal Reset © 2006 Microchip Technology Incorporated. 101 ASP BVDD Slide 46 .

8V up to 4. 101 ASP Slide 47 . All Rights Reserved.5V in 0.PLVD – Programmable Low Voltage Detect q Early warning before brown out 16 selectable trip points: − 1.1 to 0.2V steps − External analog input VDD LVDIN LVDCON q 16-bit Multiplexer VREF LVDIN q Internal VREF © 2006 Microchip Technology Incorporated.

In-Circuit Serial Programming™ q q Only two pins required for programming Convenient for In-System Programming of − − Calibration Data Serialization Data Pin Pin VPP P P VDD D D VSS S S RB6 RB7 Function Function Programming Voltage = 13V Supply Voltage Ground Clock Input Data I/O & Command Input q Supported by MPLAB® PM3 & ICD2 Application PCB VDD VDD MCLR/VPP PIC16Fxxx ICSP™ Connector ICSP Connector VDD VSS RB6 RB7 To application circuit Isolation circuits © 2006 Microchip Technology Incorporated. All Rights Reserved. 101 ASP Slide 48 .

I/O Ports VDD q q q High Drive Capability Can directly drive LEDs Direct. single cycle bit manipulation Data Bus W rite PORTx D Q Q RESET D W rite TRISx Q VSS Q q Each pin has individual direction control under software All pins have ESD protection diodes Pin RA4 is usually open drain Read PORTx q q q q All I/O pins default to inputs (high impedance) on startup All pins multiplexed with analog functions default to analog inputs on startup © 2006 Microchip Technology Incorporated. 101 ASP Slide 49 . All Rights Reserved.

I/O Pin Conceptual Diagram Bit 1 of TRISB Register movwf PORTB Write Operation PORTB Bit 1 Latch 1 = RB1 is input 0 = RB1 is output Bit 1 of Data Bus RB1 Read Operation movf PORTB. 101 ASP . All Rights Reserved.w Slide 50 © 2006 Microchip Technology Incorporated.

I/O Ports I/O Pin Direction Control TRISB PORTB 1 1 0 1 1 0 0 0 In In Out In In Out Out Out q q Bit n in TRISx controls the data direction of Bit n in PORTx 1 = Input. 0 = Output 101 ASP © 2006 Microchip Technology Incorporated. All Rights Reserved. Slide 51 .

Hands-on Exercises © 2005 Microchip Technology Incorporated. All Rights Reserved. Slide 52 .

101 ASP Slide 53 .MPLAB® ICD2 © 2006 Microchip Technology Incorporated. All Rights Reserved.

All Rights Reserved.PICDEM™ 2 Plus Board © 2006 Microchip Technology Incorporated. 101 ASP Slide 54 .

MPASM™ Assembler Template MPASM Program Template 1 2 3 4 5 6 RESET _V 7 8 9 INT _V 10 11 START 12 13 LIST p=16f877 a #include <p16f877 a.Explicitly declare processor .Put next line of code at address . these are just examples 101 ASP © 2006 Microchip Technology Incorporated.Interrupt Vector } .Tell MPASM that this is the end org 0x0000 goto START org 0x0004 retfie {Begin your code here END q q If not using interrupts. All Rights Reserved.Include register label definitions . lines 8 and 9 could be omitted The labels in the left column may be anything you want.Your code goes here . Slide 55 .Put next line of code at address .inc > .Reset Vector .

101 ASP Slide 56 . All Rights Reserved.25 Hexadecimal h’2A’ or 0x2A © 2006 Microchip Technology Incorporated.Specifying the Radix q q By default. r=dec q Good programming practice suggests that a number’s radix be specified explicitly: Radix MPASM Syntax Binary b’10101010’ Decimal d’25’ or . MPASM™ assembler expects numbers in hexadecimal Default can be changed through IDE or by adding r=hex or r=dec as a parameter to the LIST directive: LIST p=16f877a.

Lab 1: The Task q Turn on LED connected to bit 0 of PORTB (RB0) RB 0 37 470 Ω R21 D2 J6 © 2006 Microchip Technology Incorporated. All Rights Reserved. PIC16F877A 101 ASP Slide 57 .

Lab 1: Program Structure START Ce rP R B l a OT O t uL t hs up t ac e Mk 4 l w i so ae o b f t P R Bo t us O T up t Tr o L D n un n E o R ( OT . All Rights Reserved. 101 ASP Slide 58 . ) B0 P R B 0 S ic t B n w ho a k t 1 1 Instruction L a n me i t W o d u b r no 4 Instructions Mv v l et o e au o TI B RS S ic t B n w ho a k t 0 1 Instruction 1 Instruction: goto $ (Go to self) L o Hr F r v r o p ee oe e © 2006 Microchip Technology Incorporated.

Turn on LED on RB 0 . All Rights Reserved.Move value to TRISB .Reset Vector .Switch to bank 1 .Clear PORTB output latches .inc > 0x0000 START } } } } } } .Loop here forever #include org goto {1st In tru tio s c n nd {2 In tru tio s c n rd {3 In tru tio s c n th {4 In tru tio s c n th {5 In tru tio s c n th {6 In tru tio s c n goto END $ 4 bits © 2006 Microchip Technology Incorporated.Lab 1: Template Lab 1: “Hello .Load value to make lower .Switch to bank 0 . 101 ASP Slide 59 . world !” for Microcontrollers 1 2 3 4 5 6 RESET _V 7 8 START 9 10 11 12 13 14 15 16 17 LIST p=16 f877 a <p16f877 a.

Turn on LED on RB 0 . world !” for Microcontrollers 1 2 3 4 5 6 RESET _V 7 8 START 9 10 11 12 13 14 15 16 17 LIST p=16 f877 a <p16f877 a.RP 0 PORTB .Clear PORTB output latches . 101 ASP Slide 60 .inc > 0x0000 START PORTB STATUS . All Rights Reserved.Move value to TRISB .0 $ #include org goto clrf bsf movlw movwf bcf bsf goto END .Lab 1: Solution Lab 1: “Hello .Reset Vector .Switch to bank 1 .RP 0 b’11110000 ' TRISB STATUS .Switch to bank 0 .Loop here forever 4 bits © 2006 Microchip Technology Incorporated.Load value to make lower .

Lab 1: Results q You have learned: − How to program a device and run the code using the MPLAB® ICD2 − How to configure an I/O port − How to manipulate I/O pins − How to code an infinite loop (the equivalent of while(1) in C) © 2006 Microchip Technology Incorporated. 101 ASP Slide 61 . All Rights Reserved.

Lab 2: The Task q Make the LED connected to bit 0 of PORTB (RB0) blink 37 470 Ω R21 RB 0 D2 J6 © 2006 Microchip Technology Incorporated. PIC16F877A 101 ASP Slide 62 . All Rights Reserved.

Slide 63 . one instruction executes in 1µ s A 16-bit software counter is sufficient to implement the delay 101 ASP © 2006 Microchip Technology Incorporated.Lab 2: The Task q q q A delay is required to make the blinking slow enough for the human eye At 4MHz. All Rights Reserved.

MyReg1 = 0x21 MyReg2 . All Rights Reserved. Slide 64 .MyReg2 = 0x23 ENDC 101 ASP © 2006 Microchip Technology Incorporated.MyReg0 = 0x20 .MyReg2 = 0x23 q Constant Block Method: CBLOCK 0x20 MyReg0 .Naming Registers/Constants q Equate Method: MyReg0 equ 0x20 MyReg1 equ 0x21 MyReg2 equ 0x23 .MyReg0 = 0x20 MyReg1: 2 .MyReg1 = 0x21 .

All Rights Reserved.Lab 2: Program Structure START Taken from Lab 1 1 Instruction 1 Instruction Subroutine Call 1 Instruction 1 Instruction Subroutine Call Stp OT eu P R B Tr o L D n un n E o R B0 Delay T r ofL D n un f E o R B0 Delay © 2006 Microchip Technology Incorporated. 101 ASP Slide 65 .

Lab 2: Program Structure Delay Delay Subroutine 1 Instruction START CO UNTERL -- Hint: Use decfsz 1 Instruction CO UNTERL = 0? No Yes 1 Instruction CO UNTERH -- No 1 Instruction CO UNTERH = 0? Yes 1 Instruction RETURN © 2006 Microchip Technology Incorporated. All Rights Reserved. 101 ASP Slide 66 .

101 ASP Slide 67 .Switch to bank 0 4 bits . All Rights Reserved.CONTINUED ON NEXT SLIDE © 2006 Microchip Technology Incorporated.Switch to bank 1 .Move value to TRISB .RP 0 .inc > #include cblock 0x020 COUNTERL COUNTERH endc org goto clrf bsf movlw movwf bcf 0x0000 START PORTB STATUS .Load value to make lower .Reset Vector .Lab 2: Template – Part 1 Lab 2: Blinking LED 1 2 3 4 5 6 7 8 9 10 11 RESET _V 12 13 START 14 15 16 17 LIST p=16 f877 a <p16f877 a.RP 0 b’11110000 ' TRISB STATUS .Clear PORTB output latches .

All Rights Reserved. decrement COUNTERL a .Turn off LED on RB 0 .Repeat main loop .Turn on LED on RB 0 .Decrement COUNTERH .Return to main routine © 2006 Microchip Technology Incorporated.If not zero .Continued . 101 ASP Slide 68 .Call delay routine . keep decrementing CO .Decrement COUNTERL .Call delay routine .If not zero .Lab 2: Template – Part 2 Lab 2: Blinking LED 18 LOOP 19 20 21 22 23 24 DELAY 25 26 27 28 29 30 {1 In tru tio s c n } nd {2 In tru tio s c n } rd {3 In tru tion } s c th {4 In tru tio s c n } th {5 In tru tio s c n } {6th In tru tio s c n } th {7 In tru tio s c n } th {8 In tru tio s c n } th {9 In tru tio s c n } th {1 0 In tru tion } s c END s t .

Move value to TRISB .RP 0 b’11110000 ' TRISB STATUS . All Rights Reserved.CONTINUED ON NEXT SLIDE © 2006 Microchip Technology Incorporated.Switch to bank 0 4 bits .inc > #include cblock 0x020 COUNTERL COUNTERH endc org goto clrf bsf movlw movwf bcf 0x0000 START PORTB STATUS .Switch to bank 1 . 101 ASP Slide 69 .Load value to make lower .Reset Vector .RP 0 .Lab 2: Solution – Part 1 Lab 2: Blinking LED 1 2 3 4 5 6 7 8 9 10 11 RESET _V 12 13 START 14 15 16 17 LIST p=16 f877 a <p16f877 a.Clear PORTB output latches .

Continued .Turn on LED on RB 0 .If not zero . All Rights Reserved. keep decrementing CO .Decrement COUNTERL . decrement COUNTERL a © 2006 Microchip Technology Incorporated.Lab 2: Solution – Part 2 Lab 2: Blinking LED 18 LOOP 19 20 21 22 23 24 DELAY 25 26 27 28 29 30 bsf call bcf call goto decfsz goto decfsz goto return END PORTB .0 DELAY PORTB .Turn off LED on RB 0 .If not zero .Repeat main loop .Decrement COUNTERH .Call delay routine .0 DELAY LOOP COUNTERL DELAY COUNTERH DELAY .Call delay routine . 101 ASP Slide 70 .

Lab 2: Results q You have learned: − − − − − How to define register labels How to implement a loop How to implement software delays How to use a “skip” instruction How to call a subroutine © 2006 Microchip Technology Incorporated. 101 ASP Slide 71 . All Rights Reserved.

When it reaches one side. All Rights Reserved. 101 ASP Slide 72 . RB3 RB2 RB1 RB0 © 2006 Microchip Technology Incorporated. send it back to the start.Lab 3: The Task q Using one of the rotate instructions. “move” the illuminated LED across the lower 4 bits of PORTB.

All Rights Reserved.Lab 3: Program Structure START Same setup code from Lab 1 Stp OT eu P R B Rember: The rotate instructions operate on 9-bits. with the Carry bit in the STATUS register as the 9th bit 1 Instruction 1 Instruction Set Carry Bit Rotate Left PORTB Yes 1 Instruction 1 Instruction RB3 = 0? No Set Carry Bit 1 Instruction Call same subroutine from Lab 2 Delay © 2006 Microchip Technology Incorporated. 101 ASP Slide 73 .

Switch to bank 0 4 bits .RP 0 .Lab 3: Template – Part 1 Lab 3: Rotating LED 1 2 3 4 5 6 7 8 9 10 11 RESET _V 12 13 START 14 15 16 17 LIST p=16 f877 a <p16f877 a.Clear PORTB output latches . 101 ASP Slide 74 .inc > #include cblock 0x020 COUNTERL COUNTERH endc org goto clrf bsf movlw movwf bcf 0x0000 START PORTB STATUS .Move value to TRISB .Reset Vector .CONTINUED ON NEXT SLIDE © 2006 Microchip Technology Incorporated.Switch to bank 1 .Load value to make lower . All Rights Reserved.RP 0 b’11110000 ' TRISB STATUS .

Decrement COUNTERH .Rotate PORTB to left .Repeat main loop . All Rights Reserved.If not zero .Set carry bit for initial rotate .If yes . set the Carry bit .Call delay routine .Lab 3: Template – Part 2 Lab 3: Rotating LED 18 19 LOOP 20 21 22 23 24 25 DELAY 26 27 28 29 30 31 {1st In tru tio s c n } nd {2 In tru tio s c n } rd {3 In tru tion } s c th {4 In tru tio s c n } th {5 In tru tio s c n } th {6 In tru tio s c n } decfsz goto decfsz goto return END COUNTERL DELAY COUNTERH DELAY .Is the LED on RB 3 (PORTB . 101 ASP Slide 75 . keep decrementing CO .Continued .If not zero .Decrement COUNTERL .Return to main subroutine © 2006 Microchip Technology Incorporated. decrement COUNTERL a .3) on? .

Reset Vector .Load value to make lower .Lab 3: Solution – Part 1 Lab 3: Rotating LED 1 2 3 4 5 6 7 8 9 10 11 RESET _V 12 13 START 14 15 16 17 LIST p=16 f877 a <p16f877 a. All Rights Reserved.Move value to TRISB . 101 ASP Slide 76 .CONTINUED ON NEXT SLIDE © 2006 Microchip Technology Incorporated.Switch to bank 0 4 bits .RP 0 .Clear PORTB output latches .inc > #include cblock 0x020 COUNTERL COUNTERH endc org goto clrf bsf movlw movwf bcf 0x0000 START PORTB STATUS .Switch to bank 1 .RP 0 b’11110000 ' TRISB STATUS .

Repeat main loop . decrement COUNTERL a . 101 ASP Slide 77 .Rotate PORTB to left .Decrement COUNTERH .Lab 3: Solution – Part 2 Lab 3: Rotating LED 18 19 LOOP 20 21 22 23 24 25 DELAY 26 27 28 29 30 31 bsf rlf call btfsc bsf goto decfsz goto decfsz goto return END STATUS . All Rights Reserved.Continued .If yes . keep decrementing CO .Call delay routine .Decrement COUNTERL .Is the LED on RB 3 (PORTB .Return to main subroutine © 2006 Microchip Technology Incorporated.If not zero .Set carry bit for initial rotate .f DELAY PORTB .C LOOP COUNTERL DELAY COUNTERH DELAY . set the Carry bit .3 STATUS .3) on? .If not zero .C PORTB .

101 ASP Slide 78 .Lab 3: Results q You have learned: − How to use the rotate instructions − How to use the bit test & skip instructions © 2006 Microchip Technology Incorporated. All Rights Reserved.

but this time make the direction of rotation change when the LED is rotated to either end Rotate Left RB 3 RB 2 RB 1 RB 0 Rotate Right © 2006 Microchip Technology Incorporated. 101 ASP Slide 79 .Lab 4: The Task q Same as Lab 3. All Rights Reserved.

Lab 4: Program Structure START Same setup code from Lab 1 Stp OT eu P R B bsf STATUS. All Rights Reserved.C 1 Instruction 1 Instruction Subroutine Call 2 Instructions 1 Instruction 1 Instruction Subroutine Call 2 Instructions No No Set Carry Bit Rotate Left PORTB Delay RB3 = 1? Yes Rotate Right PORTB Delay RB0 = 1? Yes Slide 80 © 2006 Microchip Technology Incorporated. 101 ASP .

if no .Is the LED on RB 3 (PORTB . keep decrementing COUNTE .Decrement COUNTERH .0) on ? . rotate left {1st In tru tio s c n } nd {2 In tru tio s c n } rd {3 In tru tion } s c th {4 In tru tio s c n } {5 {6th {7th {8th {9th th In tru tio s c n } In tru tio s c n } In tru tion } s c In tru tio s c n } In tru tio s c n } COUNTERL DELAY COUNTERH DELAY decfsz goto decfsz goto return END .if no .If not zero .Is the LED on RB 0 (PORTB . 101 ASP Slide 81 .3) on ? . decrement COUNTERL again .if yes .Rotate PORTB to left .Return to main subroutine © 2006 Microchip Technology Incorporated. rotate right again .Rotate PORTB to right . rotate left again .If not zero .Lab 4: Template q Setup is identical to Lab 3 up to the LOOP Lab 3: Rotating LED 18 19 20 LEFT 21 22 23 24 25 RIGHT 26 27 28 29 30 31 DELAY 32 33 34 35 36 37 bsf STATUS .C . All Rights Reserved.Decrement COUNTERL .Call delay routine .Set carry bit for initial rotate .Call delay routine .Continued .

3 LEFT PORTB .Decrement COUNTERH . All Rights Reserved. rotate right again .if yes . Slide 82 .0 RIGHT LEFT COUNTERL DELAY COUNTERH DELAY .if no .if no .Is the LED on RB 0 (PORTB .Continued STATUS .If not zero .Set carry bit for initial rotate . rotate left . decrement COUNTERL a .f DELAY PORTB .Call delay routine .C PORTB .Rotate PORTB to right . rotate left again .If not zero .f DELAY PORTB .Return to main subroutine © 2006 Microchip Technology Incorporated.0) on? .Decrement COUNTERL .3) on? .Is the LED on RB 3 (PORTB .Rotate PORTB to left .Lab 4: Solution Lab 3: Rotating LED 18 19 20 LEFT 21 22 23 24 25 RIGHT 26 27 28 29 30 31 DELAY 32 33 34 35 36 37 bsf rlf call btfss goto rrf call btfss goto goto decfsz goto decfsz goto return END 101 ASP .Call delay routine . keep decrementing CO .

101 ASP Slide 83 . All Rights Reserved.Lab 4: Results q You have learned: − How to make decisions in software and take different courses of action © 2006 Microchip Technology Incorporated.

101 ASP Slide 84 . All Rights Reserved.Lab 5: The Task q Use a lookup table to obtain the bit pattern to be displayed on PORTB © 2006 Microchip Technology Incorporated.

Lab 5: Program Structure START Move W Reg to PO 1 Instruction RTB Lab 1 Setup Code 1 Instruction 2 Instructions 1 Instruction 1 Instruction Stp OT eu P R B Clear INDEX Delay 1 Instruction Subroutine Call Setup PCLATH INDEX 1 Instruction ++ No Move INDEX to W Register INDEX = 7? 3 Instructions Yes Call TABLE Clear INDEX 1 Instruction © 2006 Microchip Technology Incorporated. 101 ASP Slide 85 . All Rights Reserved.

Switch to bank 1 .Load W with high byte of TABLE addres .Lab 5: Template – Part 1 Lab 5: Lookup Table 1 2 3 4 5 6 7 8 9 10 11 RESET _V 12 13 START 14 15 16 17 18 19 20 LIST p=16f877 a #include <p16f877 a.RP0 s t {1 In tru tion } s c nd {2 In tru tion } s c rd {3 In tru tio s c n } .Move value to TRISB . All Rights Reserved.RP0 movlw b’11110000 ' movwf TRISB bcf STATUS .inc > cblock 0x020 COUNTERL COUNTERH endc org goto 0x0000 START .Move W to PCLATH .Load value to make lower 4 bits o .Switch to bank 0 .Clear PORTB output latches .Reset Vector clrf PORTB bsf STATUS . 101 ASP Slide 86 .CONTINUED ON NEXT SLIDE © 2006 Microchip Technology Incorporated.Clear index into table .

If not zero . 101 ASP Slide 87 .CONTINUED {4 In tru tion } s c th {5 In tru tion } s c th {6 In tru tion } s c th {7 In tru tion } s c th {8 In tru tion } s c th {9 In tru tion } s c th {1 0 In tru tion } s c th {1 1 In tru tion } s c th {1 2 In tru tion } s c th {1 3 In tru tion } s c decfsz goto decfsz goto return COUNTERL DELAY COUNTERH DELAY th .Move W to PORTB .Load W with 0x07 .Return to main subroutine ON NEXT SLIDE © 2006 Microchip Technology Incorporated. clear INDEX .Move INDEX to W .Increment INDEX .Repeat loop .Decrement COUNTERL .Subtract W from INDEX . keep decrementing COUN .Is Z bit in STATUS set .Decrement COUNTERH .Lab 5: Template – Part 2 Lab 3: Lookup Table 22 LOOP 23 24 25 26 27 28 29 30 31 32 33 DELAY 34 35 36 37 38 .Continued . decrement COUNTERL aga .if yes . result in ? .Call delay . All Rights Reserved.Call TABLE .If not zero .

Table entry © 2006 Microchip Technology Incorporated.Continued program counter 0 1 2 3 4 5 6 .Table entry .f b’00000001 b’00000011 b’00000111 b’00001111 b’00001110 b’00001100 b’00001000 ' ' ' ' ' ' ' .Table entry .Table entry . 101 ASP Slide 88 .Lab 5: Template – Part 3 Lab 3: Lookup Table 39 TABLE 40 41 42 43 44 45 56 58 59 addwf retlw retlw retlw retlw retlw retlw retlw END PCL .Table entry .Add offset to . All Rights Reserved.Table entry .Table entry .

inc > cblock 0x020 COUNTERL COUNTERH endc org goto clrf bsf movlw movwf bcf clrf movlw movwf 0x0000 START PORTB STATUS .Move value to TRISB .Clear PORTB output latches .Switch to bank 0 .Clear index into table .Load W with high byte of TABLE addres .RP 0 b’11110000 ' TRISB STATUS .Load value to make lower 4 bits o . All Rights Reserved.CONTINUED ON NEXT SLIDE © 2006 Microchip Technology Incorporated.Lab 5: Solution – Part 1 Lab 5: Lookup Table 1 2 3 4 5 6 7 8 9 10 11 RESET _V 12 13 START 14 15 16 17 18 19 20 LIST p=16 f877 a #include <p16f877 a.Reset Vector . 101 ASP Slide 89 .RP 0 INDEX HIGH TABLE PCLATH .Move W to PCLATH .Switch to bank 1 .

Call TABLE PORTB .Continued INDEX .Lab 5: Solution – Part 2 Lab 3: Lookup Table 22 LOOP 23 24 25 26 27 28 29 30 31 32 33 DELAY 34 35 36 37 38 . clear INDEX LOOP .Subtract W from INDEX STATUS . 101 ASP Slide 90 .if yes .Repeat loop COUNTERL DELAY COUNTERH DELAY .If not zero . decrement COUNTERL aga . result in ? .Return to main subroutine ON NEXT SLIDE © 2006 Microchip Technology Incorporated.Call delay INDEX .Is Z bit in STATUS set INDEX .Move INDEX to W TABLE .Decrement COUNTERL .CONTINUED movf call movwf call incf movlw subwf btfsc clrf goto decfsz goto decfsz goto return .w .Z .Decrement COUNTERH .If not zero .w . keep decrementing COUN . All Rights Reserved.Move W to PORTB DELAY .f .Increment INDEX 0x07 .Load W with 0x07 INDEX .

101 ASP Slide 91 .Table entry .Table entry © 2006 Microchip Technology Incorporated.Lab 5: Solution – Part 3 Lab 3: Lookup Table 39 TABLE 40 41 42 43 44 45 56 58 59 addwf retlw retlw retlw retlw retlw retlw retlw END PCL .Table entry .Table entry .Continued program counter 0 1 2 3 4 5 6 . All Rights Reserved.Table entry .Table entry .Add offset to .Table entry .f b’00000001 b’00000011 b’00000111 b’00001111 b’00001110 b’00001100 b’00001000 ' ' ' ' ' ' ' .

101 ASP Slide 92 . All Rights Reserved.Lab 5: Results q You have learned: − How to implement a lookup table − How to retrieve data from a lookup table − How to call a subroutine on another page − How to perform a computed goto © 2006 Microchip Technology Incorporated.

All Rights Reserved. 101 ASP Slide 93 .Summary q q q q PIC16 Architecture PIC16 Instruction Set PIC16 Memory Organization Simple Programming Techniques © 2006 Microchip Technology Incorporated.

References
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PICmicro® MCU Mid-Range Family Reference Manual (DS33023A) Microchip Technology Programming and Customizing PICmicro Microcontrollers by Myke Predko Design with PIC® Microcontrollers by John B. Peatman
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References
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123 PIC® Microcontroller Experiments for the Evil Genius by Myke Predko

© 2006 Microchip Technology Incorporated. All Rights Reserved.

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Thank You

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All Rights Reserved. SEEVAL. In-Circuit Serial Programming.S. FlexROM. dsPIC. and other countries.S. MPSIM. Mindi. 101 ASP Slide 97 . MPASM. the Microchip logo.A. ECONOMONITOR. PICtail. rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U. FilterLab. Migratable Memory. PICSTART. FanSense. SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U. dsPICDEM. MPLIB. Smart Serial.net. ICSP. PowerInfo. rfLAB. MXDEV. REAL ICE. Accuron. MPLAB. Total Endurance.A. PICkit. Select Mode.Trademarks The Microchip name and logo. Application Maestro. ECAN. Analog-for-the-Digital Age. All other trademarks mentioned herein are property of their respective companies. UNI/O. PowerTool.A. rfPICDEM. PICmicro. MXLAB. © 2006 Microchip Technology Incorporated. KeeLoq. MPLINK.net.A. PICDEM. MiWi. microID. PICDEM. Linear Active Thermistor. ICEPIC. WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U. and other countries. PRO MATE.S. SmartTel. SQTP is a service mark of Microchip Technology Incorporated in the U. AmpLab. PIC. dsPICDEM. fuzzyLAB. PowerCal. PowerSmart. PICLAB. dsPICworks.S. PowerMate.

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