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VHDL History

‡ 1960's - 1980's
± over 200 languages, either proprietary or academic

‡ 1983 VHSIC Program initiates definition of VHDL ‡ 1987 VHDL Standard (IEEE 1076) approved ‡ 1990 Verilog dominates the commercial marketplace
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VHDL History
‡ 1992 IEEE 1164 (abstract data types for different signal characteristics, i.e. 3, 4, 9valued logic standard) ‡ 1993 VHDL re-balloted
± minor changes make it more user-friendly.

‡ 1994 Widespread acceptance of VHDL.

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Modeling Interfaces
‡ Entity declaration
± describes the input/output ports of a module
entity name port names port mode (direction)

entity reg4 is port ( d0, d1, d2, d3, en, clk : in bit; q0, q1, q2, q3 : out bit ); end entity reg4;
reserved words port type

punctuation

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q2. q1. d2. d1. en. clk : in bit.VHDL-87 ‡ Omit entity at end of entity declaration entity reg4 is port ( d0. May 17. Hyderabad 4 . q0. end reg4. q3 : out bit ). d3. 2006 Xilinx.

2006 5 . each containing sequential statements. including signal assignment statements and wait statements Xilinx.Modeling Behaviour ‡ Architecture body ± describes an implementation of an entity ± may be several per entity ‡ Behavioral architecture ± describes the algorithm performed by the module ± contains ‡ ‡ ‡ ‡ process statements. Hyderabad May 17.

wait on d0. Hyderabad 6 . q3 <= stored_d3 after 5 ns. stored_d3 : bit. en.Behavior Example architecture behav of reg4 is begin storage : process is variable stored_d0. q2 <= stored_d2 after 5 ns. clk. end process storage. d1. stored_d3 := d3. stored_d2 := d2. q0 <= stored_d0 after 5 ns. d3. 2006 Xilinx. d2. end if. stored_d1. begin if en = '1' and clk = '1' then stored_d0 := d0. q1 <= stored_d1 after 5 ns. stored_d1 := d1. stored_d2. May 17. end architecture behav.

VHDL-87
‡ Omit architecture at end of architecture body ‡ Omit is in process statement header
architecture behav of reg4 is begin storage : process ... begin ... end process storage; end behav;

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Modeling Structure
‡ Structural architecture
± implements the module as a composition of subsystems ± contains
‡ signal declarations, for internal interconnections
± the entity ports are also treated as signals

‡ component instances
± instances of previously declared entity/architecture pairs

‡ port maps in component instances
± connect signals to component ports

‡ wait statements
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Structure Example
d0 bit0 d_latch d q clk bit1 d_latch d q clk bit2 d_latch d q clk bit3 d_latch d q gate and2 a y b clk int_clk q0

d1

q1

d2

q2

d3

q3

en clk

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clk : in bit. architecture basic of and2 is begin and2_behavior : process is begin y <= a and b after 2 ns. May 17. y : out bit ). end if. end process latch_behavior. end architecture basic. architecture basic of d_latch is begin latch_behavior : process is begin if clk = µ1¶ then q <= d after 2 ns. wait on clk. end entity d_latch. end architecture basic. 2006 Xilinx. wait on a. q : out bit ). end process and2_behavior. end entity and2. entity and2 is port ( a. b. d. b : in bit.Structure Example ‡ First declare D-latch and and-gate entities and architectures entity d_latch is port ( d. Hyderabad 10 .

int_clk. q0 ).d_latch(basic) port map ( d2. q2 ). q1 ).d_latch(basic) port map ( d0. gate : entity work. q3 ). bit3 : entity work. int_clk.d_latch(basic) port map ( d1.and2(basic) port map ( en. int_clk. clk.d_latch(basic) port map ( d3. bit2 : entity work. int_clk.Structure Example ‡ Now use them to implement a register architecture struct of reg4 is signal int_clk : bit. bit1 : entity work. May 17. int_clk ). Hyderabad 11 . end architecture struct. begin bit0 : entity work. 2006 Xilinx.

2006 Xilinx.VHDL-87 ‡ Can¶t directly instantiate entity/architecture pair ‡ Instead ± include component declarations in structural architecture body ‡ templates for entity declarations ± instantiate components ± write a configuration declaration ‡ binds entity/architecture pair to each instantiated component May 17. Hyderabad 12 .

Structure Example in VHDL-87
‡ First declare D-latch and and-gate entities and architectures
entity d_latch is port ( d, clk : in bit; q : out bit ); end d_latch; architecture basic of d_latch is begin latch_behavior : process begin if clk = µ1¶ then q <= d after 2 ns; end if; wait on clk, d; end process latch_behavior; end basic;
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entity and2 is port ( a, b : in bit; y : out bit ); end and2; architecture basic of and2 is begin and2_behavior : process begin y <= a and b after 2 ns; wait on a, b; end process and2_behavior; end basic;

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Structure Example in VHDL-87
‡ Declare corresponding components in register architecture body
architecture struct of reg4 is component d_latch port ( d, clk : in bit; q : out bit ); end component; component and2 port ( a, b : in bit; y : out bit ); end component; signal int_clk : bit; ...

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Structure Example in VHDL-87
‡ Now use them to implement the register
... begin bit0 : d_latch port map ( d0, int_clk, q0 ); bit1 : d_latch port map ( d1, int_clk, q1 ); bit2 : d_latch port map ( d2, int_clk, q2 ); bit3 : d_latch port map ( d3, int_clk, q3 ); gate : and2 port map ( en, clk, int_clk ); end struct;
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and2(basic) end for. 2006 Xilinx. end basic_level.Structure Example in VHDL-87 ‡ Configure the register model configuration basic_level of reg4 is for struct for all : d_latch use entity work.d_latch(basic). Hyderabad 16 . May 17. end for. end for. for all : and2 use entity work.

Mixed Behaviour and Structure ‡ An architecture can contain both behavioral and structural parts ± process statements and component instances ‡ collectively called concurrent statements ± processes can read and assign to signals ‡ Example: register-transfer-level model ± data path described structurally ± control section described behaviorally May 17. 2006 Xilinx. Hyderabad 17 .

2006 Xilinx. Hyderabad 18 .Mixed Example multiplier multiplicand shift_reg control_ section shift_ adder reg product May 17.

Mixed Example
entity multiplier is port ( clk, reset : in bit; multiplicand, multiplier : in integer; product : out integer ); end entity multiplier; architecture mixed of mulitplier is signal partial_product, full_product : integer; signal arith_control, result_en, mult_bit, mult_load : bit; begin arith_unit : entity work.shift_adder(behavior) port map ( addend => multiplicand, augend => full_product, sum => partial_product, add_control => arith_control ); result : entity work.reg(behavior) port map ( d => partial_product, q => full_product, en => result_en, reset => reset ); ...
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Mixed Example
« multiplier_sr : entity work.shift_reg(behavior) port map ( d => multiplier, q => mult_bit, load => mult_load, clk => clk ); product <= full_product; control_section : process is -- variable declarations for control_section -- « begin -- sequential statements to assign values to control signals -- « wait on clk, reset; end process control_section; end architecture mixed;

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Test Benches
‡ Testing a design by simulation ‡ Use a test bench model
± an architecture body that includes an instance of the design under test ± applies sequences of test values to inputs ± monitors values on output signals
‡ either using simulator ‡ or with a process that verifies correct operation

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d2. stimulus : process is begin d0 <= ¶1¶. end process stimulus. q2. q0. Hyderabad 22 . clk <= ¶1¶. q3 ).reg4(behav) port map ( d0. q1. d1. en. d3. « wait. wait for 20 ns. wait for 20 ns. en <= ¶0¶. 2006 Xilinx. Test Bench Example architecture test_reg4 of test_bench is signal d0. d3. d0 <= ¶0¶. q0. d2 <= ¶1¶. d3 <= ¶1¶. wait for 20 ns. en <= ¶1¶. wait for 20 ns. wait for 20 ns. d2 <= ¶0¶. q2. wait for 20 ns.entity test_bench is end entity test_bench. d1 <= ¶1¶. end architecture test_reg4. q1. d1. en. q3 : bit. clk. May 17. en <= ¶0¶. d3 <= ¶0¶. begin dut : entity work. d1 <= ¶0¶. clk. d2. clk <= ¶0¶.

Regression Testing ‡ Test that a refinement of a design is correct ± that lower-level structural model does the same as a behavioral model ‡ Test bench includes two instances of design under test ± behavioral and lower-level structural ± stimulates both with same inputs ± compares outputs for equality ‡ Need to take account of timing differences May 17. 2006 Xilinx. Hyderabad 23 .

d2. q0b. q2a. q2b. dut_b : entity work. wait for 20 ns. en <= ¶0¶. d3. q3a. begin dut_a : entity work. d1. en. d3. en. en <= ¶1¶. wait for 20 ns. clk <= ¶1¶.Regression Test Example architecture regression of test_bench is signal d0. q1b. d2. stimulus : process is begin d0 <= ¶1¶. clk : bit. d1. d1 <= ¶1¶. d1. q0b. d2 <= ¶1¶. d2. wait for 20 ns. « wait. q1a. q2a. q2b. q3b : bit.reg4(behav) port map ( d0. q3a ). 2006 Xilinx. d3 <= ¶1¶. clk.reg4(struct) port map ( d0. en. end process stimulus. Hyderabad 24 . wait for 20 ns. signal q0a. May 17. clk <= ¶0¶. . clk. q0a.. d3. q1a. q3b ). q1b..

assert q0a = q0b and q1a = q1b and q2a = q2b and q3a = q3b report ´implementations have different outputs´ severity error. d3. 2006 Xilinx. d1.Regression Test Example « verify : process is begin wait for 10 ns. wait on d0. d2. clk. end architecture regression. Hyderabad 25 . end process verify. en. May 17.

Design Processing ‡ ‡ ‡ ‡ Analysis Elaboration Simulation Synthesis May 17. 2006 Xilinx. Hyderabad 26 .

2006 ± in an implementation dependent internal form Xilinx.Analysis ‡ Check for syntax and semantic errors ± syntax: grammar of the language ± semantics: the meaning of the model ‡ Analyze each design unit separately ± entity declaration ± architecture body ±« ± best if each design unit is in a separate file ‡ Analyzed design units are placed in a library May 17. Hyderabad 27 .

Elaboration ‡ ³Flattening´ the design hierarchy ± create ports ± create signals and processes within architecture body ± for each component instance. Hyderabad 28 . copy instantiated entity and architecture body ± repeat recursively ‡ bottom out at purely behavioral architecture bodies ‡ Final result of elaboration ± flat collection of signal nets and processes May 17. 2006 Xilinx.

2006 Xilinx.Elaboration Example re d0 (str ct) bit0 d latc d clk bit1 d latc d clk bit2 d latc d clk bit d latc d ate and2 a y b clk int clk 0 d1 1 d2 2 d en clk May 17. Hyderabad 29 .

Elaboration Example reg4(struct) d0 bit0 d_latch(basic) d q clk bit1 d_latch(basic) d q clk bit2 d_latch(basic) d q clk bit3 d_latch(basic) d q gate and2(basic) a y b clk int_clk q0 d1 q1 d2 q2 d3 q3 en clk process with variables and statements May 17. 2006 Xilinx. Hyderabad 30 .

VHDL Design Example ‡ Problem: Design a single bit half adder with carry and enable ‡ Specifications ± ± ± ± Inputs and outputs are each one bit When enable is high. Hyderabad 31 . carry gets any carry of x plus y Outputs are zero when enable input is low x carry y Half Adder result enable May 17. result gets x plus y When enable is high. 2006 Xilinx.

result: OUT BIT). END half_adder. Xx Yy enable en May 17. enable: IN BIT. 2006 Xilinx. Hyderabad Half Adder carry result 32 . the entity declaration describes the interface of the component ± input and output ports are declared ENTITY half_adder IS PORT( x. carry.VHDL Design Example Entity Declaration ‡ As a first step. y.

VHDL Design Example Behavioral Specification ‡ A high level description can be used to describe the function of the adder ARCHITECTURE half_adder_a OF half_adder IS BEGIN PROCESS (x. carry <= x AND y. result <= µ0¶. END IF. enable) BEGIN IF enable = µ1¶ THEN result <= x XOR y. y. END half_adder_a. END PROCESS. ELSE carry <= µ0¶.  The May 17. 2006 model can then be simulated to verify correct functionality of the component Xilinx. Hyderabad 33 .

result <= enable AND (x XOR y). END half_adder_b. the model can be simulated at this level to confirm the logic equations Xilinx. Hyderabad 34 May 17.  Again.VHDL Design Example Data Flow Specification ‡ A second method is to use logic equations to develop a data flow description ARCHITECTURE half_adder_b OF half_adder IS BEGIN carry <= enable AND (x AND y). 2006 .

Hyderabad 35 .VHDL Design Example Structural Specification ‡ As a third method. 2006 gates can be pulled from a library of parts Xilinx. a structural description can be created from predescribed components x y enable carry result  These May 17.

out0 : OUT BIT). COMPONENT and3 PORT (in0.description is continued on next slide May 17.and3_Nty(and3_a). COMPONENT xor2 PORT (in0. out0 : OUT BIT).VHDL Design Example Structural Specification (Cont. END COMPONENT. FOR ALL : xor2 USE ENTITY gate_lib.and2_Nty(and2_a). FOR ALL : and3 USE ENTITY gate_lib. FOR ALL : and2 USE ENTITY gate_lib. in1. Hyderabad 36 . in2 : IN BIT. 2006 Xilinx.xor2_Nty(xor2_a). in1 : IN BIT. -. out0 : OUT BIT). END COMPONENT.) ARCHITECTURE half_adder_c OF half_adder IS COMPONENT and2 PORT (in0. in1 : IN BIT. END COMPONENT.

enable. y.Note that other signals are already declared in entity BEGIN A0 : and2 PORT MAP (enable. 2006 Xilinx. -. y. May 17.VHDL Design Example Structural Specification (cont. result).continuing half_adder_c description SIGNAL xor_res : BIT. A1 : and3 PORT MAP (x. X0 : xor2 PORT MAP (x. xor_res). carry). xor_res. Hyderabad 37 . END half_adder_c.internal signal -.) -.

optional and can be repeated ‡ | ---. ± constant number_of_byte : integer := 4.is defined to be ± variable_assignment <= target. } : subtype_indication [ := expression ] . ‡ [ clause ] ---. . . Hyderabad 38 . .Language Syntax ‡ BNF format for syntax rule ‡ ³<=³ ---. 2006 Xilinx.optional ‡ _ clause a ---.alternatives ± mode <= in | out | inout ± constant_declaration <= constant identifier { . May 17.

end if .Example ‡ if_statement <= ‡ maximum: if a > b then [ if_label : ] if a > c then if boolean_expression then result := a . { sequential_statement } ] else end if [ if_label ] . 2006 Xilinx. { sequential_statement } elsif b > c then [ else result := b. May 17. then end if. Hyderabad 39 . result := c. { sequential_statement } else { elsif boolean_expression result := c.

and files ‡ Types ± ± scalar type: individual values that are ordered ‡ discrete.Primitive Objects in VHDL ‡ Object -. variables. and physical ± composite type: array and record ± file type ± access type ‡ VHDL is a strongly typed language May 17. floating-point. signals. 2006 Xilinx. Hyderabad 40 .a named item that has a value of a specified type ‡ 4 classes of objects: ± constants.

Primitive Objects in VHDL ‡ time Variable -. May 17. ± Examples signal preset. Holds values that change over. signal CS1: bit. ± Example: variable i_slice: integer range 0 to Reg_size-1. A value for a signal is computed and added to a waveform for future application.analogous to wire or device output. Hyderabad 41 . 2006 Xilinx. ± used to establish connectivity and pass values between concurrently active design elements. Holds values which may change over time. clear: bit. ± assignment (:=) ± immediately overwrites the existing value ‡ Signal -.often no direct correspondence in hardware.

µ7¶). true). µ2¶. Hyderabad 42 .'1'). µ4¶. outcomes of logical expression evaluation.to count in discrete steps ± type integer is range -(231-1) to 231-1 (at least) ‡ Bit -.Primitive Data Types ‡ Integer -. ‡ Enumeration types -.values are in a list of identifiers | character_literal ± type octal_digital is (µ0¶. 2006 Xilinx.to represent the most commonly occurring model of discrete digital circuit value ± type bit is ('0'. µ6¶. May 17. µ5¶. ‡ Boolean -.to represent decisions. especially used in procedural control flow ± type boolean is (false. µ3¶. µ1¶.

to create models which work with textual data and communication / control symbols to provide textual information to designer-users through design tool windows to the model ± type character is the set of ASCII symbols ‡ Reals to represent analog. 2006 Xilinx.0E+38 and with 6 decimal digits of precision) ‡ The predefined package standard (stored in the library std ) ‡ Type declaration ± type byte_integer is integer range -128 to 127. continuously variable.0E+38 to 1. measurable values in design space. May 17.Primitive Data Types ‡ Character -. Hyderabad 43 . (at least ±1.

type bit is ('0'. «. eot.). etx. « hr = 60 min. 2006 Xilinx. error.. type character is ( nul.STANDARD. 'B'. «. warning.VHD -. '@'. 'C'. Hyderabad 44 . May 17.true). 'D'.0E308. type severity_level is (note..0E308 to 1. package standard is type boolean is (false.This is Package STANDARD as defined in the VHDL 1992 Language Reference Manual. type time is range -2147483647 to 2147483647 units fs. type integer is range -2147483647 to 2147483647. end units. soh. ps = 1000 fs. failure). type real is range -1. '1'). stx. 'A'.

May 17. impure function now return delay_length. end standard.VHD (cont¶d) subtype delay_length is time range 0 fs to time'high. write_mode. append_mode). subtype natural is integer range 0 to integer'high.STANDARD. type file_open_status is ( open_ok. name_error. type file_open_kind is ( read_mode. type string is array (positive range <>) of character. status_error. Hyderabad 45 . 2006 Xilinx. attribute foreign : string. subtype positive is integer range 1 to integer'high. type bit_vector is array (natural range <>) of bit. mode_error).

+-file2006 46 .VHD (cont¶d) types-+-scalar----+-discrete-------+-integer-------+-integer | | | +-natural | | | +-positive | | | | | +-enumeration---+-boolean | | +-bit | | +-character | | +-file_open_kind | | +-file_open_status | | +-severity_level | | | +-floating point-+-----------------real | | | +-physical-------+-----------------delay_length | +-----------------time | +-composite-+-array----------+-constrained| | | | | +-unconstrained-+-bit_vector | | +-string | | | +-record| +-access| Xilinx.STANDARD. Hyderabad May 17.

May 17.Generics ‡ Pass information from its environment into the design unit which is not time-varying ‡ Very useful for creating and using generalized designs. Hyderabad 47 . 2006 Xilinx.

all. Hyderabad 48 .std_logic_1164. USE IEEE.all. a: IN std_logic_vector(n-1 downto 0). 2006 Xilinx.Generics: Example a n LIBRARY IEEE.std_logic_arith. S: IN std_logic ). PORT (Y: OUT std_logic_vector(n-1 downto 0). b: IN std_logic_vector(n-1 downto 0). b 0 Y n 1 n ENTITY Generic_Mux IS S GENERIC (n: INTEGER). END ENTITY. USE IEEE. May 17.

Hyderabad 49 .Entities and Architectures ‡ Entities Entity Architecture A ± are Design Bodies ± provide the Interface description Architecture B Architecture C ‡ Architectures Architecture D ± are concurrent ± may be behavioral ± may be structural May 17. 2006 Xilinx.

wires etc. Hyderabad Dout 50 sel . procedures.Entities and Architecture ‡ Entity ± External view: Pin-out description. Interface description. I-O port definition etc ‡ Architecture ± Internal view ‡ Structural description: Gates. 2006 Din ARCHITECTURE Xilinx. RTL 4 description ENTITY mux 2 May 17. ‡ Behavioral description: functions.

May 17. 2006 Xilinx. ‡ Are signal objects ± connected together by signals ± used to pass values between concurrently active units. Hyderabad 51 .Ports ‡ Pass information through the interface which is time-varying.

but not read.Interface Modes ‡ Represent direction of value flow ‡ In entities. ± INOUT within the design unit (both entity and body) the value may be both read and written. Hyderabad 52 . components. and blocks the modes may be: ± IN value ± OUT value within the design unit (both entity and body) the may be read. but not written. May 17. 2006 Xilinx. within the design unit (both entity and body) the may be written.

local declarations. 2006 Xilinx.concurrent statements end identifier . May 17. Hyderabad 53 .Format of an Architecture architecture identifier of entity_identifier is -. typically signals begin -.

s2 <= b nand s0. 2006 z <= s1 nand s2. 54 .Xilinx. s2: bit. s1 <= a nand s0. May 17. s1.b:in bit. end. z : out bit ).Simple Example entity XOR port (a. architecture nand_gates of XOR is signal s0. Hyderabad end nand_gates. begin s0 <= a nand b.

2006 Xilinx.Hierarchical Design Strategies ‡ Bottom Up Strategy ± create low level and auxiliary models first. they can be used as components in the next higher level architectural body. Hyderabad 55 . ‡ Top Down Strategy ± create highest level entity and architecture first. entity and architecture ± once low level entities are present. creating only the interface definitions (entity declarations) for lower level architectures May 17.

‡ The packages can be shared among models. . ‡ Its implementation is provided in the µpackage body¶. ‡ 17.Packages ‡ An important way of organizing the data. 2006 Several predefined packages exist. ‡ The external view of a package is specified in µpackage declaration¶. such as 56 Xilinx. ‡ A collection of related declaration grouped to serve a common purpose. Hyderabad May IEEE standard packages.

contains declarations of objects defined in the package ± Package body -. subtypes ‡ Constants Xilinx.Packages ‡ Packages consist of two parts ± Package declaration -. Hyderabad May 17.contains necessary definitions for certain objects in package declaration ‡ e.g. 2006 ‡ Subprograms 57 . subprogram descriptions ‡ Examples of VHDL packages : ± Basic declarations Signal declarations items included in  Attribute declarations  Component declarations  ‡ Types.

subsequent package Hyderabad 2006 ± for type and subtype definitions. temp_carry : OUT BIT). CONSTANT My_ID : INTEGER. b. body May 17. ‡ Note some items only require declaration while others need further detail provided in Xilinx.14. OFF ). en : IN BIT. SIGNAL temp_result. CONSTANT PI : REAL := 3. END my_stuff. PROCEDURE add_bits3(SIGNAL a.Packages Declaration ‡ An example of a package declaration : PACKAGE my_stuff IS TYPE binary IS ( ON. declaration is 58 .

PROCEDURE add_bits3(SIGNAL a. END my_stuff. May 17. b.Packages Package Body ‡ The package body includes the necessary functional descriptions needed for objects declared in the package declaration ± e. temp_carry <= a AND b AND en.g. 2006 Xilinx.this function can return a carry temp_result <= (a XOR b) AND en. en : IN BIT. assignments to PACKAGE BODY my_stuff IS constants CONSTANT My_ID : INTEGER := 2. SIGNAL temp_result. END add_bits3. temp_carry : OUT BIT) IS BEGIN -. subprogram descriptions. Hyderabad 59 .

. ENTITY declaration. May 17.use all of the declarations in package my_stuff USE my_stuff.. -....add_bits3. ENTITY declaration. and other packages -..use only the binary and add_bits3 declarations USE my_stuff.. 2006 Xilinx.. ARCHITECTURE declaration ..Packages Use Clause ‡ Packages must be made visible before their contents can be used ± The USE clause makes packages visible to entities.binary. . architectures.. Hyderabad 60 ...ALL. . .. ARCHITECTURE declaration .. . my_stuff...

Hyderabad May 17. 2006 ± Many other libraries usually supplied by VHDL . architectures.g. libraries of previous designs ‡ Libraries accessed via an assigned logical name ± Current design unit is compiled into the Work library ± Both Work and STD libraries are always available 61 Xilinx.e. compiled) VHDL entities. and packages ‡ Facilitate administration of configuration and revision control ± E.Libraries ‡ Analogous to directories of files ± VHDL libraries contain analyzed (i.

Hyderabad 62 .Packages: Example May 17. 2006 Xilinx.

‡ Hence. 2006 Xilinx. Hyderabad 63 . ‡ However.Special Library: Work ‡ The identifier ³work´ is a special library that maps on to the present directory. May 17. an explicit declaration of ³work´ library is not required. ‡ All the design units in the present directory are visible to all models. one needs to specify the ³work´ when accessing declarations and design units in other files.

Work Library: Example May 17. 2006 Xilinx. Hyderabad 64 .

2006 Xilinx.Processes May 17. Hyderabad 65 .

highway_light : out color ). May 17. max_hwyred : time ). 2006 architecture specification of Xilinx. port ( farmroad_trip : in boolean. end traffic_light_controller.Procedural Modeling USE: High level abstraction of behavior entity traffic_light_controller generic ( yellow_time : time. Hyderabad 66 . farmroad_light : out color. min_hwygreen : time.

Hyderabad May 17. farmroad_light <= red. farmroad_light <= yellow. highway_light <= yellow. Xilinx.Procedural Modeling USE: High level abstraction of behavior architecture specification of traffic_light_controller is begin cycle: process is begin highway_light <= green. highway_light <= red. wait for min_green. wait until not farmroad_trip for max_hwyred. wait for yellow_time. wait for yellow_time. 2006 end process. 67 . farmroad_light <= green. wait until farmroad_trip.

Xilinx. begin Zvar := µ1¶. Hyderabad May 17.Procedural Modeling Use: Detailed Modeling of Behavior Example: Timed Behavior of Primitive Elements AND_n: process (x) is -. 68 . 2006 exit .for every i in the range of x if x(i) = '0' then Zvar := '0' .x is an array of bit variable Zvar : bit. for i in x'range loop -.

May 17.Process Statement Is the ³wrapper´ around a sequential routine to compute the behavior desired for the design at a specific moment in time.(typically ended by a wait statement) end process [ label ]. label: process [ (signal list) ] is { declarations } begin { sequential statements } -. Hyderabad 69 . 2006 Xilinx.

± interrupted only by WAIT statements. Hyderabad May process. ‡ Time advances until the wait condition is satisfied.´ ‡ 17. then execution resumes. it advances during a WAIT 70 . ± bottom of the process contains an implicit "go to the top. 2006 DOES NOT ADVANCE within a TIME Xilinx. ‡ Executes in an endless loop.initialization. running till it hits a WAIT statement.Process Execution Model ‡ Executes once (at TIME = 0) -.

Process Statement . Hyderabad 71 May 17.A Concurrent Statement ‡ A process is a kind of concurrent statement. 2006 ± For example: the AND_n process example is the model of . ± includes declarations. and all ‡ Evaluation of a process is triggered when one of a list of signals in the wait statement changes value ‡ Note: Just because a process is sequential does NOT mean it is modeling the sequential behavior of a design. sequential body. ± a description of functional behavior Xilinx.

in3 : in std_ulogic.all. 2006 72 . entity andcircuit is port( in1. end andcircuit. May 17.std_logic_1164.library IEEE. out1 : out std_ulogic ). use IEEE. Hyderabad Xilinx. in2.

variable Fval : std_logic := '0'. where Tprop. constants can all be set to default values: signal enable : bit := 0. . . Hyderabad:= '0'. ‡ Ports can be initialized by entity xyz port ( aXilinx. load are generics or constants. constant Tplh : Time := Tprop + K * load . K. 2006 73 . variables. ) : in bit May 17. .Initialization of Objects ‡ Signals.

Hyderabad 74 .Signal assignment ‡ Signals ± Used to communicate between concurrently executing processes. May 17. 2006 Xilinx. ± Within a process they continue to have the form sig <= waveform . ± Means that for the signal a sequence of value updating events is to be scheduled for the future.

functions. Not visible to others. X <= Y. 2006 Xilinx. X := Y. like processes.Variable assignment ‡ Variables: ± Exist within procedural bodies. May 17. ± Variable assignment statements appear as follows: var := expression. Y <= X. Hyderabad 75 . Y := X. ± Used within the sequential body just as in other procedural languages. and procedures.

simulation time does not advance. Hyderabad May 17. the signal will never be updated before the WAIT ± and may not be updated even after the WAIT is complete if the WAIT completed faster than the signal update has delay associated with it.Misuse of Sequential Signal Assignments ‡ Note a signal does not take on its new value until time advances. ‡ Therefore. Xilinx. ‡ Until the process hits a WAIT (hold. 2006 76 . or suspend) statement.

y) VARIABLE x : BIT := '1'. y <= in_sig XOR x. 2006 a 1 to 0 transition on in_sig. ARCHITECTURE test2 OF mux IS SIGNAL y : BIT := '0'. END test2.Signals and Variables ‡ This example highlights the difference between signals and variables ARCHITECTURE test1 OF mux IS SIGNAL x : BIT := '1'. END test1. Hyderabad 77 . y <= in_sig XOR x. BEGIN x := in_sig XOR y. y) BEGIN x <= in_sig XOR y. BEGIN PROCESS (in_sig. x. END PROCESS. BEGIN PROCESS (in_sig.  Assuming May 17. what are the resulting values for y in the both cases? Xilinx. END PROCESS. SIGNAL y : BIT := '0'.

END sig_ex. 2006 Xilinx. Time 0 1 1+d 1+2d a 0 1 1 1 b 1 1 1 1 c 1 1 1 1 out_1 1 1 0 0 out_2 0 0 0 1 May 17. b. out_2 <= out_1 XOR c. Hyderabad 78 . out_1) BEGIN out_1 <= a NAND b.VHDL Objects Signals vs Variables ‡ A key difference between variables and signals is the assignment delay ARCHITECTURE sig_ex OF test IS PROCESS (a. END PROCESS. c.

c) VARIABLE out_3 : BIT. 2006 a 0 1 1 b 1 1 1 c 1 1 1 out_3 1 0 0 out_4 0 0 1 79 Xilinx.) ARCHITECTURE var_ex OF test IS BEGIN PROCESS (a. BEGIN out_3 := a NAND b.VHDL Objects Signals vs Variables (Cont. Time 0 1 1+d May 17. b. END var_ex. out_4 <= out_3 XOR c. Hyderabad . END PROCESS.

‡ wait until x = 1. ‡ wait on a. Hyderabad 80 . May 17. c. 2006 for 100 ns. « } ] [ until boolean_expr ] [ for time_expr ] . ‡ wait Xilinx. b. ‡ wait.Wait Statements wait_stmt <= [ label : ] wait [ on signal_name{ .

2006 after 10 ns. Hyderabad 10 ns. b) is begin begin s <= a xor b after 10 ns. half_adder: process is half_adder: process (a. ‡ The list of signals is also called a sensitivity list. s <= a xor b after 10 ns. c <= a and b afterXilinx. c <= a and b 81 May 17. .Wait on ‡ process being suspended until an event takes place on any one of the signals.

s2. s3 until condition. ‡ The process is resumed when the condition evaluates to TRUE. 2006 ‡ Hence the process is resumed when . ‡ The condition is evaluated only when an event occurs on a signal in the sensitivity list. Hyderabad 82 May 17.Wait until wait on s1. Xilinx.

. May 17. wait until . 2006 Mem_Req <= '1' after Hyderabad wait until DAV = '1'. . Data <= ROM_DATA(Address) after 50 ns.. 83 . end process. address value .. CPU_Read: process is begin Mem_Req <= '0'. . 10 ns. wait until Mem_Req = '0'. Address <= . the need for memory read . Xilinx. . DAV <= '1' after 60 ns.Example Use of Multiple Wait Statements: CPU and Memory Handshaking Memory: process is begin DAV <= '0'. wait until Mem_Req = '1'.

84 May 17.. d are the sensitivity list ‡ is equivalent to a single WAIT with a sensitivity list at the bottom of the process: process begin . the process will be executed. d ) is where signals a. c... ‡ Whenever any of the signals in the sensitivity list change value.. b. c. c. 2006 . wait on a. b. statements. b.. ‡ Note: Processes with a sensitivity list may not contain any wait statements.label: process ( a. nor may they call procedures with wait Hyderabad Xilinx. d.. end process.

Hyderabad . 2006 Xilinx.Configuration & Component Instantiation A B HALF_ADDER HA1 C1 C2 S1 Cin HALF_ADDER HA2 OR O1 COUT SUM D0 D1 XOR X1 AND A1 S C 85 May 17.

end FULL_ADDER. HS. architecture FA_WITH_HA of FULL_ADDER is component HALF_ADDER port (HA.Configuration & Component Instantiation entity FULL_ADDER is «.HB: in BIT. May 17. Hyderabad 86 . end component.HC: out BIT). 2006 Xilinx.

C2. COUT).. C2). S1. HA2: HALF_ADDER port map (S1. end FA_WITH_HA.HA_STR has components XOR2 and AND2 87 . C1). May 17. SUM. O1: OR2 port map (C1. . Cin..Configuration & Component Instantiation begin HA1: HALF_ADDER port map (A. 2006 .similar declaration for entity HA and architecture HA_STR Hyderabad Xilinx. B.

Top-level configuration for HA1.HA2: HALF_ADDER use entity WORK. Hyderabad 88 May 17. D1. for HA_STR . configuration FA_HA_CON of FULL_ADDER is for FA_WITH_HA .Nested configuration for all: XOR2 use entity WORK.. 2006 end for.HA(HA_STR) port map (D0=> HA. S. for A1: AND2 .Configuration & Component Instantiation library ECL. Xilinx.XOR(XOR2). C)..

Sequential VHDL Statements May 17. Hyderabad 89 . 2006 Xilinx.

Sequential Statements These statements can appear inside a process description ‡ variable assignments ‡ if-then-else ‡ case ‡ loop ‡ infinite loop ‡ while loop Xilinx. Hyderabad 90 May 17. 2006 for loop ‡ .

Hyderabad 91 . 2006 Xilinx.If statement: Examples May 17.

Hyderabad 92 . 2006 Xilinx.Case statement: Example May 17.

Null statement: Example ‡ To take care of conditions when no action is needed May 17. 2006 Xilinx. Hyderabad 93 .

‡ avoid this situation in any high level programming language. May 17.Loop statements: Infinite Loop ‡ Repeats a sequence of statements indefinitely. ‡ Typical structure: Loop statement in process body with a wait statement. Hyderabad 94 . ‡ In digital systems this is useful as hardware devices repeatedly perform the same operation as long as power supply is on. 2006 Xilinx.

2006 Xilinx. Hyderabad 95 .Infinite Loop: Example May 17.

Hyderabad 96 .While Loop: Example May 17. 2006 Xilinx.

For loop May 17. Hyderabad 97 . 2006 Xilinx.

Hyderabad 98 May 17. ‡ It can be used in an expression but not written to. Xilinx. ‡ Loop parameter is a constant inside the loop body.For Loop: Rules ‡ Loop parameter¶s type is the base type of the discrete range. ‡ Loop parameter is not required to be explicitly declaration. 2006 ‡ Loop parameter¶s scope is defined by the .

2006 Xilinx. Hyderabad 99 .For Loop: Example May 17.

end case.A Typical use of CASE: FSM A part of a process used to model the next state computation for a finite state machine. case machine_state is when sv0 => machine_state <= sv1 when sv1 => machine_state <= sv2. Hyderabad 100 . 2006 Xilinx. May 17. when sv2 => machine_state <= sv3. when sv3 => machine_state <= sv0.

2006 Xilinx. Hyderabad 101 .Typical use of CASE: Multiplexer Model the output value generation for a finite state machine. May 17. case Current_state is when sv0 | sv1 | sv2 => Z_out <= '0'. end case. when sv3 => Z_out <= '1'.

wait until ssyn = '1'. 2006 end loop. Hyderabad May 17. 102 . bus_data <= data_src. msyn <= '1' after 50 ns. ‡ Example: while bus_req = '1' loop wait until ad_valid_a = '1'. Xilinx. msyn <= '0'.While Loops ‡ Form: while condition loop sequential statements end loop.

2006 Xilinx.Next ‡ branches back to the beginning of the loop (like a Fortran CONTINUE statement). Hyderabad 103 . May 17. loop sequential statements next when condition sequential statements end loop.

Exit ‡ branches completely out of the loop to the first statement following the end loop. ‡ Example: where x_in is an array of inputs May 17. Xilinx. loop sequential statements exit when condition sequential statements end loop. Hyderabad exit when new_val = '0'. 104 . 2006 for i := 2 to x_in'length loop new_val := new_val and x_in(i) .

Concurrent VHDL May 17. Hyderabad 105 . 2006 Xilinx.

Hyderabad 106 . 2006 Xilinx.Need for Concurrent VHDL ‡ Intuitively closer to actual hardware than procedural descriptions ‡ More compact representation than procedural descriptions ‡ Provides natural way to represent the natural concurrency arising in hardware May 17.

Concurrent statements ‡ Signal assignment statements ± (unconditional) ± Conditional (when-else) ± Selected (with-select) ‡ Process (interface to procedural descriptions) ‡ Component instantiation (interface to structural descriptions) May 17. Hyderabad 107 . 2006 ‡ Block statement Xilinx.

Concurrent VHDL Statements ‡ Execution whenever an input (RHS) changes value. 2006 Xilinx. Y <= X. Example: Exchange of signal values X <= Y. May 17. Hyderabad 108 . ‡ Execution order totally independent of order of appearance in source code.

Hyderabad 109 ± Supports modeling of concurrent and sequential . 2006 Xilinx.Simulation Cycle Revisited Sequential vs Concurrent Statements ‡ VHDL is inherently a concurrent language ± All VHDL processes execute concurrently ± Concurrent signal assignment statements are actually one-line processes ‡ VHDL statements execute sequentially within a process ‡ Concurrent processes with sequential execution within a process offers maximum flexibility ± Supports various levels of abstraction May 17.

s2 <= b nand s0. s1. z : out bit ). s1 <= a nand s0.Xilinx. 2006 z <= s1 nand s2. architecture nand_gates of XOR is signal s0. begin s0 <= a nand b. 110 .b:in bit. s2: bit.Simple Example entity XOR port (a. May 17. end. Hyderabad end nand_gates.

s2 <= b nand s0. The s1 <= « and s2 <= « statements would have used the Xilinx. 2006 111 . s1 <= a nand s0. end placing the first statement (s0 <= «) after the last statement has absolutely no effect on execution or the result. old s0 value May 17. Hyderabad anyhow. nand_gates. z <= s1 nand s2.more In the example begin s0 <= a nand b.Concurrent statements .

Conditional signal assignment (When-else statements)
‡ When-else statements imply priority encoding.
S <= W0 after W1 after W2 after W3 after delay0 delay1 delay2 delay3 when when when when c0 c1 c2 c3 else else else else

Wx after delayx ;
Note: Priority encoding is implied since more than one condition might be true at the same time. The condition Xilinx, Hyderabad May 17, 2006 appearing first in the statement has the priority.

112

Circuit implementation

May 17, 2006

Xilinx, Hyderabad

113

Equivalent process
PROCESS (W0, W1, . . ., WX, C0, C1, . . . ); BEGIN
IF c0 THEN S <= W0 after delay0 ELSIF c1 THEN S <= W1 after delay1 ELSIF c2 THEN S <= W2 after delay2 ELSE S <= Wx after delayx ; END PROCESS; Xilinx, Hyderabad May 17, 2006

114

‡ UNAFFECTED has the same Xilinx. ‡ No ELSE implies Memory S <= X after t WHEN C.else S <= Wa after Ta when c0 else Wb after Tb. Hyderabad May 17. 2006 effect as a null clause 115 .Simple when .

no event is implied when the condition is false. B <= A when phase_a = '1' . I. May 17.. so the signal retains its old value. Hyderabad 116 . it has memory. 2006 Xilinx.e. ‡ Examples: Q <= D when rising_edge (clock).No ELSE implies Memory ‡ Memory is implied where no else clause is provided. ‡ In the simulation model.

B <= A when en else (others => 'Z'). Hyderabad 117 . May 17. -.for tri-state driver output B <= A when en else 'Z'. 2006 Xilinx. B <= A when en else (others =>'0').for simple AND enabling B <= A when en else '0¶.Simple enabling -.

May 17. Wx after delayx when OTHERS. 2006 Xilinx. W2 after delay2 when c2. W1 after delay1 when c1.Selected Signal Assignment ‡ Form WITH selector SELECT signame <= W0 after delay0 when c0. Hyderabad 118 .

when lteq.cond select branch <= '1' uncond. 2006 nzero . when less. May 17. when 119 . when when zero.Example: Branch Condition Selector ‡ Typically the cond field of the instruction specifies which of several logical expressions of status flipflops is to be used. when never . Z S xor V (S xor V) and Z '0' not Z Hyderabad Xilinx. With IR.

2006 Xilinx. Hyderabad 120 .Circuit example May 17.

‡ Since no more than one value can be selected at a time. 2006 involved. 121 .Selected Signal Assignment ‡ All values must be included ± the range of values for the selector should be restricted with some care. a declaration like ³signal csel : integer.Xilinx. the address partitioned to correspond to the decoding method being used. Hyderabad no priority encoding is May 17. ‡ Otherwise.´ calls for a 2**32-1 input multiplexer which we would not want to build! Even where address decoding is required the range should be 0 to 255 or so.

synthesis standard ‡ unused inputs ‡ optimization possibilities ‡ Forces explicit consideration of what is to be done if unexpected input values occur. 2006 Xilinx. Hyderabad 122 .OTHERS Clause ‡ handle 'X' -. May 17.

1 bit cout: out std_logic. USE work. -. .unlatched func_sel: in std_logic_vector (0 to Xilinx. ENTITY ALU is -.add_w_carry. 1 bit.Example: An ALU LIBRARY ieee.std_logic_1164. 2006 1). -.Data Out(latched) a.A and B leg inputs cin: in std_logic. USE ieee.all. b: in std_logic_vector.Carry Out.IO ports port (dout: out std_logic_vector.Carry in.ALU_funcs. Hyderabad 123 May 17. -. -.

constant OPOR: std_logic_vector := "01". May 17. 2006 Xilinx. -. Hyderabad 124 BEGIN .Opcode interpretation constant OPADD: std_logic_vector := "00".Example continued ARCHITECTURE concurrent of ALU is constant XOUT: std_logic_vector(a¶range) := (others=>'X') --ALU output: carry concatentated to left end makes an extra bit signal ALUout: std_logic_vector(xt_reg¶range). constant OPAND: std_logic_vector := "10". constant OPXOR: std_logic_vector := "11".

'0' & (a AND b) when OPAND. cin) when OPADD. '0' & (a XOR b) when OPXOR. b. Hyderabad 125 May 17. 2006 OTHERS. XOUT when Xilinx. add_w_carry(a. ALUout) <= '0' & (a OR b) when OPOR. .Example continued BEGIN with func_sel select (cout.

1X. Other legal values that must be accounted for include: 0X. May 17. since STD_LOGIC is a 9-valued system. X0. ³01´. there are 81-4 ³other´ selector values that must be handled.Note use of OTHERS clause ‡ Only intended values are ³00´. X1. ³11´. Hyderabad 126 . -‡ In fact. XX. ‡ However!!!! The inputs are type STD_LOGIC_VECTOR (0 to 1). ³10´. 2006 Xilinx.

Procedures ‡ Procedure: Declared and then called ‡ Example: procedure average_samples is variable total: real := 0. Hyderabad ‡ This can be called inside a process as: 127 . --------------end procedure average_samples. May 17. 2006 Xilinx.0.

‡ Unlike procedure. ‡ Parameters of the function must be of µin¶ mode and may not be of class variable. 2006 end function bv_add. bv2 : in bit_vector) return bit_vector is begin --------------Xilinx. ‡ Example: function bv_add (bv1. Hyderabad 128 May 17. function calculates and returns a result that can be used in an expression.Functions ‡ Syntax is very similar to that of the procedures. .

Hyderabad 129 May 17. 2006 particularly useful for de-bugging. ‡ Some of these can specified by ³assert´ statements. ‡ Report Statement are useful for providing extra information from specific assertion statements (as there can be several assertion statements). ‡ Assert and report statements are Xilinx.Assertion & Report statements ‡ A functionally correct model may need to satisfy certain conditions. .

Hyderabad 130 .Assertion & Report: Example May 17. 2006 Xilinx.

Hyderabad May 17.Block Statement ‡ Three major purposes: ± Disable signal drivers by using guards ± Limit scope of declarations (including signals) ± Represent a portion of design B1: block (STROBE=µ1¶) begin Z <= guarded (not A). end block B1. Xilinx. 2006 131 .

Hyderabad 132 . 2006 Xilinx.Signal Assignment. Delay and Attributes May 17.

133 .Event-driven Simulation ‡ Event: occurrence of an signal change (transaction) ‡ When an event occurs. need to handle it (execution) ± to execute any concurrent statements that are sensitive to the change ± to activate a waiting process if the condition becomes true ‡ The execution triggered by an event may generate future eventsHyderabad Xilinx. 2006 ± sig_a <= a_in after 5 ns. May 17.

2006 Xilinx. Hyderabad 134 .Event-driven Simulation Initialization No future event find the next event(s) exit execute statements activated by the event(s) generate future events May 17.

2006 ‡ it will be changed to ³1´ at current_time+5ns 135 . need a data structure to indicate that ‡ the current state (value) of ³sig_a´ is ³0´ and Xilinx. Hyderabad May 17.Event-driven Simulation ‡ Events must be handled in sequence ± current_time advances when the execution all current events is done and the next event is triggered ± event queue ± an internal data structure to manage the event sequence ‡ System state ± represented by the states of all objects ± thus.

‡ Delay values must appear in ascending order ‡ List of updating events (I. Hyderabad 136 .e.Waveforms in Signal Assignment ‡ Form Sig_identifier <= val_expr1 after delay1 { . May 17. 2006 Xilinx.. val_expr_ after delay_ } . value / time) is called a Driver of the signal.

2006 Xilinx.Simulation of VHDL ‡ All components work concurrently ‡ If an event triggers 2 statements and the result of the 1st one is also the input of the 2nd one ‡ Sequential statements allow immediate updates ± for functional behavior ± no notion of time ‡ Concurrent statement ± execute and update stages May 17. Hyderabad 137 ± for circuit operation .

the new values will be written to the objects sig_a and add_a. 2006 seems there is a delay between execution and 138 update (delta delay) . -. -statement (2) If a_input changes at current_time ± execution stage -. and new events can be generated due to the changes ± no change in current_time Xilinx.sig_a and add_a will be computed in the statements (1) and (2) ± update stage -.Simulation of signal assignment statements sig_a <= a_input. Hyderabad ± It May 17.statement (1) add_a <= sig_a xor c_in xor a_input.

Examples of a waveform ‡ OS_Out <= OS_in. 2006 time 0 20ns 40ns 60ns 80ns S 1 0 0 0 1 C 0 0 1 0 1 µ1¶ after 40 ns. Xilinx. µ1¶ after 80 ns. May 17. Clear_pattern <= µ0¶. µ0¶ after Tperiod. Hyderabad 139 . µ0¶ after 20 ns. ‡ Test sequence for an RS latch: Set_pattern <= µ1¶.

Hyderabad 140 ‡ Order of listing these .Concurrent VHDL Assignments NQ <= NZ after tprop. Z <= NZ nor CLEAR after tprop. 2006 Xilinx. May 17. NZ <= Z nor SET after tprop. Q <= Z after tprop.

µ0¶ after 5 ns. y <= a xor b after 4 ns. 2006 » 1st event is 141 removed when 2nd is created and . b <= µ1¶. Hyderabad May 17. b Y 4 5 8 9 ‡ Output Y is initially µ1¶ and will be scheduled: µ0¶ after 8 ns µ1¶ after 9 ns Xilinx.Inertial Delay ‡ Inputs: a a <= µ0¶. µ1¶ after 4 ns.

Hyderabad 142 removed when 2nd is May 17. µ0¶ after 5 ns. b Y 4 5 8 9 ‡ Output Y is initially µ1¶ and will be scheduled: µ0¶ after 8 ns µ1¶ after 9ns ± 1st event is NOT Xilinx. µ1¶ after 4 ns. y <= a xor b after 4 ns.again a a <= µ0¶. b <= µ1¶. 2006 .Transport Delay ‡ Inputs: -.

Signal Attributes ‡ S¶delayed(t) ± a waveform all of its own. delayed by t ‡ S¶stable(t) ± a waveform all of its own. Hyderabad ‡ S¶last_event 143 ± time since last value . type boolean ‡ S¶event ± a function true only when S changes value May 17. 2006 Xilinx.

e. types. procedures. subtypes. Hyderabad 144 May 17. variables ± General form of attribute use :read as "tick" name'attribute_identifier -- ‡ VHDL has several predefined. 2006 signal X .Attributes ‡ Attributes provide information about certain items in VHDL ± E.g. signals. functions.returns the previous value of Xilinx.g : ± X'EVENT -.TRUE when there is an event on signal X ± X'LAST_VALUE -.

abs. <. /. ror ± Relational operators -. OR. >= ± Logical operators -.AND. sla. /=. XOR.+. rem ± Sign operator -. ± Addition operators -.Operators ‡ chained to form complex expressions res <= a AND NOT(B) OR NOT(a) AND b.+. ‡ Defined precedence levels in decreasing order : ± Miscellaneous operators -. srl.**. & ± Shift operators -. <=. NOR. 2006 XNOR . rol. >. mod. Xilinx.*. sra.=. NAND. Hyderabad 145 May 17. not ± Multiplication operators -.sll. -.

Array. Records. Hyderabad 146 . 2006 Xilinx. and Aggregated Constants May 17.

May 17.Composite structures ‡ Arrays ± group elements of same types ‡ Records ± group elements of different types ‡ Access ± like pointers in ³C´. Hyderabad 147 . may be useful in file I/O and creation of test environments. 2006 Xilinx.

May 17. 2006 148 . TYPE regs IS ARRAY ( 0 to 31) of byte. (where we previously defined type byte by type byte is 0 to 255.) Hyderabad Xilinx.«}) OF element_subtype_indication.Declaring Arrays ‡ FORM TYPE array_name IS ARRAY (discrete_range {. ‡ Examples TYPE carrier IS ARRAY (15 downto 0) of bit.

USE of Discrete Range ‡ Discrete range is ± index_value TO index_value ± index_value DOWNTO index_value ± using a previously defined type ‡ type_name RANGE left_value TO right_value OR ‡ type_name RANGE right_value DOWNTO left_value May 17. Hyderabad 149 . 2006 Xilinx.

Hyderabad May 17. 2006 150 SIGNAL AX. CX. ‡ HOWEVER! Almost always MULTIPLE arrays of the same dimensions and with the same element types are needed. so usually ± declare array type ± declare objects TYPE word IS ARRAY ( 31 DOWNTO 0 ) of BIT. Xilinx. BX.Objects or Types ‡ Can declare objects to be arrays directly SIGNAL AX : ARRAY ( 31 DOWNTO 0 ) of BIT. DX : word. .

number of elements in array May 17.left index.right index.smallest index value defined in range high -.right index defined in range low -. opposite direction. right index reverserange -. left index ‡ length -. direction.Array Attributes ‡ ‡ ‡ ‡ ‡ ‡ left -. Hyderabad 151 .left index defined in range right -. 2006 Xilinx.largest index value defined in range range -.

Reference to Elements of an Array ‡ Use parenthesis. END LOOP. Hyderabad 152 . 2006 Xilinx. ELSE AX(j) <= new_right_bit. not brackets for index ‡ Example: Put a new example here ‡ Example FOR j in AX¶range LOOP IF j <> AX¶right THEN AX ( j) <= AX(j-1). May 17.

the actual size of the array objects is unknown ‡ Necessary because OPERATIONs on the array need to be written generally ± operate the objects regardless of the size they may have. ± declare element types ± declare array types ‡ At the time the array type is declared. May 17. Hyderabad 153 .Unconstrained Arrays ‡ In a package. 2006 Xilinx.

TYPE std_logic_vector IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC. May 17. Hyderabad 154 . 2006 Xilinx.How to Declare an Unconstrained Array FORM TYPE arrayname IS ARRAY ( indextype RANGE <> ) OF element_type. Examples: TYPE bit_vector IS ARRAY ( NATURAL RANGE <>) OF BIT.

-string is -an array of characters constant zeroes : bit_vector := B´0000_0000´. May 17.Bit_Vectors and Strings ‡ Predefined for use in STD. constant restart: bit_vector := X´0FC´. constant empty: bit_vector := O´052´.STANDARD ‡ Both are unconstrained array declarations Examples of use: constant Error_Msg : string := ³System is Unstable´. Hyderabad 155 . 2006 Xilinx.

all. cy_in : in std_logic.Std_Logic_Vectors ‡ Unconstrained array defined for us in Library IEEE. Hyderabad May 17. Xilinx. right : in std_logic_vector. 2006 control : in std_logic_vector (0 to 3) ). Example of use: entity alu ( left. USE Package IEEE. 156 .STD_LOGIC_1164. result : out std_logic_vector. cy_out : out std_logic.

May 17. END RECORD ‡ Should be used to group elements of different types which logically belong together. 2006 Xilinx. field2 : type. Hyderabad 157 .Records ‡ Declaration TYPE record_type IS RECORD field1 : type.

END RECORD. 158 . 2006 Xilinx. ‡ VARIABLE current_time : time_stamp. hour : integer range 0 to 23. May 17. minute : integer range 0 to 59. Hyderabad current_time.second := 0.Records ‡ Definition -TYPE time_stamp IS RECORD second : integer range 0 to 59.

direct. indexed). src_mode: Address_mode.Example of Record ‡ Type declarations TYPE Operations is (move. ‡ A type describing the structure of instructions: TYPE Instruction is RECORD opcode : Operations. rot flag). sp. src_reg. dec. bra. bx. sbb. dst_mode: Address_mode. pop. call. inc. bp. TYPE Xreg is (ax. dst_reg: Xreg. TYPE Address_mode is (reg. Xilinx. Hyderabad May 17. sub. si. shf. 159 . displ. add. push. di). adc. 2006 END RECORD. indirect. cx. dx.

. Hyderabad 160 .fieldname ‡ Example SIGNAL IR : Instruction. . . . name the object followed by period and the field FORM: objectname. 2006 Xilinx.. . May 17.opcode IS -.. case IR.References to records ‡ Just as in other languages.references opcode field where mov => . where add => .

2006 . . repeated as many times as needed. . Hyderabad 161 separated by |.Aggregated constants ‡ The way to define constant values for composite data objects like arrays and records. ‡ FORM ( index_or_field_name(s) => value. index_or_field_name(s) can be a range of values for array indexing. several enumerated values Xilinx. ). May 17. or the field names for records.

constant conversion_table : ctable := (³0110´). Hyderabad May 17. .¶1¶. high.high=>¶1¶.¶1¶.falling=>¶0¶).rising=>¶1¶. constant conversion_table : ctable := (µ0¶. Xilinx.¶0¶). constant conversion_table : ctable := (low=>¶0¶. high|rising => µ1¶). 2006 constant conversion_table : ctable := (low|falling 162 => µ0¶. type ctable is array (clock_level) of bit. rising.Examples of Aggregated Constants Assume type clock_level is (low. falling).

Then we can write the following statement: bit_action <= ctable ( clk_tran ).Referencing into tables Suppose we declare Variable clk_tran : clock_level. May 17. Signal bit_action : bit. 2006 Note that the index Xilinx. Hyderabad NOT integers. 163 values are .

May 17. . Constant Y : std_logic_vector := ³001X´.Aggregated Constants ‡ Strings and derived types on character can be placed in ³ .´ ‡ Examples Constant X : bit_vector := ³0010´. Hyderabad 164 . 2006 Xilinx. . Constant Z : string := ³ABCD´.

‡ Array example Constant ZZs : cpureg := (cpureg¶range => µZ¶).More examples of aggregated constants ‡ Record example Constant CLEARAX : Instruction := (opcode => xor. Hyderabad 165 . src_mode=> reg. src_reg => ax. May 17. 2006 Xilinx. dst_mode => reg). dst_reg => ax.

Multidimensional Arrays TYPE array_name IS ARRAY(index_type1. . Hyderabad 166 .) OF element_type. . . ‡ Most useful in creating lookup tables for functions May 17. index_type2. 2006 Xilinx.

'0'.| 0 | ( 'U'. '0'. .example TYPE stdlogic_table IS ARRAY(std_ulogic. -. '0'. 'X'.std_ulogic) OF std_ulogic. '0'. 'X'. '0'. 'U'. 2006 ). '1'. '1'.| U | ( 'U'. '0'. 'U' ). Hyderabad 167 May 17. 'X'. '0'. -. 'U'.| X | ( '0'. 'U'. '0'. '0'. '0' Xilinx. '0'. '0'. 'X' ). 'X'.truth table for "and" function CONSTANT and_table : stdlogic_table := ( ----------------------------------------------------| U X 0 1 Z W L H | | ---------------------------------------------------( 'U'. -. 'X'. 'X'. 'U'. 'X'.Creating tables for lookup functions . '0'. '0'. -. 'U'. 'X'.

handled by the AND operation in the Package STD_LOGIC_1164 Body. then the quickest way to get the new value for AND is a table lookup.Another table lookup example ‡ Suppose inputs P and Q are std_ulogic. Result := and_table (P. 2006 Xilinx. ‡ Note: the values of P and Q are enumerated. not indexed.Q). Hyderabad 168 . May 17.

Use of OTHERS keyword ‡ Filling in all the default values in Arrays ‡ Extremely useful where unconstrained arrays need to be initialized. Hyderabad 169 May 17. Xilinx. 2006 . OTHERS => µ0¶). ‡ FORM: use keyword OTHERS as the index_name ± Constant S_ONE : std_logic_vector := (S_ONE¶right => µ1¶. ± Constant S_ZZZ : std_logic_vector := (OTHERS => µZ¶).

2006 Xilinx. Hyderabad 170 .Design Processing ‡ ‡ ‡ ‡ Analysis Elaboration Simulation Synthesis May 17.

2006an implementation dependent internal 171 form .Design Processing: Analysis ‡ Check for syntax and semantic errors ‡ Analyze each design unit separately ± entity declaration ± architecture body ±« ± best if each design unit is in a separate file ‡ Analyzed design units are placed in a library Xilinx. Hyderabad ± in May 17.

copy instantiated entity and architecture body -. Hyderabad 172 May 17.Design Processing: Elaboration ‡ ³Flattening´ the design hierarchy ± create ports ± create signals and processes within architecture body ± for each component instance. 2006 ± flat collection of signal nets and processes .repeat recursively ‡ Final result of elaboration Xilinx.

Hyderabad 173 . 2006 Xilinx.Design Processing: Elaboration Example May 17.

Hyderabad 174 . 2006 Xilinx.Design Processing: Elaboration Example May 17.

Hyderabad 175 May 17. 2006 signals .Design Processing: Simulation ‡ Execution of the processes in the elaborated model ‡ Discrete event simulation ± time advances in discrete steps ± when signal values change²events ‡ A processes is sensitive to events on input signals ± specified in wait statements ± resumes and schedules new values on output Xilinx.

Design Processing: Simulation Algorithm ‡ Initialization phase ± each signal is given its initial value ± simulation time set to 0 ± for each process ‡ activate ‡ execute until a wait statement. 2006 176 . Hyderabad May 17. then suspend ± execution usually involves scheduling transactions on signals for later times Xilinx.

2006 ‡ resume . or whose ³wait for «´ time-out has expired Xilinx. Hyderabad 177 May 17.Design Processing: Simulation Algorithm ‡ Simulation cycle ± advance simulation time to time of next transaction ± for each transaction at this time ‡ update signal value ± event if new value is different from old value ± for each process sensitive to any of these events.

Hyderabad 178 .Design Processing: Synthesis ‡ Translates register-transfer-level (RTL) design into gate-level netlist ‡ Restrictions on coding style for RTL model ‡ Tool dependent: A subset of RTL is synthesizable depending on the tool May 17. 2006 Xilinx.