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CONSTRUCTION OF LOGIC GATES

DIODE
y A diode is an electrical device allowing current to move

through it in one direction y When placed in a simple battery-lamp circuit, the diode will either allow or prevent current through the lamp, depending on the polarity of the applied voltage.

DIODE

DIODE
y Diodes can be used as
y y y y y y

voltage regulators tuning devices in rf tuned circuits frequency multiplying devices in rf circuits mixing devices in rf circuits switching applications or can be used to make logic decisions in digital circuits. emit "light , known as light-emitting-diodes or LED's

the diode is ON .DIODE AS A SWITCH y The Ideal Diode Considered as a Switch y reverse bias causes zero current (negative x-axis) and is therefore open circuit i..e.e.. .7V for silicon or 0. the diode is OFF . y A "practical" diode model improves over this ideal model by taking account of the small switch-on voltage source of 0. y Forward biasing causes a large current at zero voltage (positive y-axis) and therefore corresponds to a closed circuit i.3V for germanium.

either P-N-P or N-P-N. y Difference between a PNP transistor and an NPN transistor is the proper biasing (polarity) of the junctions when operating.TRANSISTOR y A bipolar transistor y consists of a three-layer "sandwich" of doped (extrinsic) semiconductor materials. .

respectively). or from emitter to collector. or from emitter to base. y The main current that is controlled goes from collector to emitter. once again depending on the type of transistor it is (PNP or NPN. respectively). .TRANSISTOR y Bipolar transistors y work as current-controlled current regulators. y they restrict the amount of current that can go through them according to a smaller. depending on the type of transistor it is (PNP or NPN. y The small current that controls the main current goes from base to emitter. controlling current.

y Example of a simple switch circuit (before using transistor) . it can be used as a sort of current-controlled switch.TRANSISTOR AS SWITCH y Because a transistor's collector current is proportionally limited by its base current.

.TRANSISTOR AS A SWITCH y controlled current through a transistor must go between collector and emitter y position the collector and emitter of our transistor where the two contacts of the switch are now y make sure that the lamp's current will move against the direction of the emitter arrow symbol to ensure that the transistor's junction bias will be correct.

TRANSISTOR AS A SWITCH y If the switch is open. . the transistor is said to be cutoff. the base wire of the transistor will be left "floating" (not connected to anything) y there will be no current through it. y In this state.

back to the positive side of the battery. the transistor is said to be saturated. y through the switch and up to the left side of the lamp. electrons will be able to flow from the emitter through to the base of the transistor. y This base current will enable a much larger flow of electrons from the emitter through to the collector. thus lighting up the lamp.TRANSISTOR AS A SWITCH y If the switch is closed. . y In this state of maximum circuit current.

which in turn controls the lamp any sufficient source of DC current may be used to turn the transistor on using a relatively low-power signal to control a relatively large amount of power .TRANSISTOR AS A SWITCH y the switch contacts need only handle what little base current is necessary to y y y y y turn the transistor on. a small switch may be used to control a relatively high-current load. EXAMPLE : a solar cell is used to control the transistor. while the transistor itself handles the majority of the lamp's current.

Saturation Region . Cut-off Region .Both junctions are Reverse-biased. . Base current is high enough to give a Collector-Emitter voltage of 0v resulting in maximum Collector current flowing.TRANSISTOR SWITCHING CIRCUIT y 1. the device is switched fully "ON". Base current is zero or very small resulting in zero Collector current flowing. the device is switched fully "OFF".Both junctions are Forward-biased. y y 2.

.7 volts y By varying the Base-Emitter voltage Vbe. the Base input terminal must be made more positive than the Emitter by increasing it above the 0. the Base current is altered and which in turn controls the amount of Collector current flowing through the transistor y When maximum Collector current flows the transistor is said to be Saturated.TRANSISTOR SWITCHING CIRCUIT y To make the Base current flow. The value of the Base resistor determines how much input voltage is required and corresponding Base current to switch the transistor fully "ON".

TRANSISTOR SWITCHING CIRCUIT Vcc Vcc OUTPUT = 5V INPUT = 0V INPUT = 5V CUT-OFF OUTPUT = 0V SATURATION .

while a Schottky diode voltage drop is between approximately 0. Schottky y is a semiconductor diode with a low forward voltage drop and a very fast switching action. y .SCHOTTKY DIODE (increase switching speed) y A normal silicon diode has a voltage drop between 0.45 volts.7 volts. y This lower voltage drop can provide higher switching speed and better system efficiency. y The Schottky diode named after German physicist Walter H.6 1.15 0.

html y Delay time (td) is the time required for the BJT to come out of cutoff.com/chet_paynter_introduct_6/ 0.prenhall.SWITCHING TIME (BJT) y http://wps. y rise time is measured from the 90% to the 10% points on the .426359-. y this is the time required for to drop to 90% of its high-state value.5779. y Rise time (tr) is the time required for the BJT to make the transition from cutoff to saturation.00.

5779. y fall time is measured from the 10% to the 90% points on the waveform.prenhall.html y Storage time (tS) is the time required for the BJT to come out of saturation. y this is the time required for the to reach 10% of its high-state value.SWITCHING TIME y http://wps.426359-.com/chet_paynter_introduct_6/ 0. y Fall time () is the time required for the BJT to make the transition from saturation to cutoff.00. .

SIMPLE BASIC DIGITAL LOGIC GATES y http://www.ws/logic/logic_1. y The simple 2-input Diode-Resistor AND gate can be converted into a NAND gate by the addition of a single transistor inverting (NOT) stage.html y Simple digital logic gates can be made by combining transistors. diodes and resistors.electronics-tutorials. .

. y so the following TTL and CMOS circuit designs are used instead. resistors and transistors) to make digital logic gate circuits are not used in practical commercially y these circuits suffer from propagation delay or gate delay.) y Also this type of design does not turn fully "OFF" as a Logic "0" produces an output voltage of 0. power loss due to the pull-up resistor y also there is no "Fan-out" facility (the ability of a single output to drive many inputs of the next stages.SIMPLE BASIC DIGITAL LOGIC GATES y Using discrete components (diodes.6v (diode voltage drop).

y called transistor transistor logic because both the logic gating function (e.TRANSISTOR-TRANSISTOR LOGIC (TTL) y http://en. .g.org/wiki/Transistor%E2%80%93transistor_logic y Transistor transistor logic (TTL) y a class of digital circuits built from bipolar junction transistors (BJT) and resistors. AND) and the amplifying function are performed by transistors (contrast this with RTL and DTL).wikipedia..

TRANSISTOR-TRANSISTOR LOGIC (TTL) y TTL NAND GATE .

causing current to flow out of that emitter. y T2 will be in CUT OFF situation .TRANSISTOR-TRANSISTOR LOGIC (TTL) y TTL NAND GATE OPERATION (1 OF THE INPUT =0) y will forward-bias Input = 0 CUT OFF Forward Bias the base-emitter junction.

y Now that T2 is in Input = 0 . causing T4 to go into cut-off. CUT OFF y the output Vo is pulled up to logic '1'.TRANSISTOR-TRANSISTOR LOGIC (TTL) y TTL NAND GATE OPERATION(1 OF THE INPUT=0) cut-off. causing T3 to saturate. or closer to Vcc. current from Vcc will be diverted to the base SATURATION of T3 through R3. CUT OFF y The base of T4 will Input = 0 be deprived of current.

LOW-POWER SCHOTTKY TTL .

ADVANCED SCHOTTKY TTL .

y If the IC is sourcing current it is flowing out of the output. . The terms refer to the direction of the current at the IC's output. y If the IC is sinking current it is flowing into the output. y a device connected between the IC output and the negative supply (0V) will be switched ON when the output is high (+Vs).SOURCING & SINKING CURRENT y IC outputs are often said to 'sink' or 'source' current. y a device connected between the positive supply (+Vs) and the IC output will be switched ON when the output is low (0V).

com/digital%20elec tronics/TTL%20Logic%20Family.awardspace. .pptx y What is totem pole? y addition of an active pull up circuit in the output of a gate is called totem pole. Using Q3 and Q4 to achieve this purpose y Why totem pole? y To increase the switching speed of the gate which is limited due to the parasitic capacitance at the output.TOTEM POLE IN TTL y http://uojcourses.

BASIC CMOS DIGITAL LOGIC GATE y Main disadvantages of the TTL logic series y they consume large amounts of power from a fixed +5 volt power supply. y limited operating speed when switching from an "OFF" state to an "ON" state and vice-versa called the "gate" or "propagation delay". y To overcome these limitations complementary MOS called "CMOS" logic gates using "Field Effect Transistors" or FET's were developed .

CMOS y is a technology for constructing integrated circuits. static RAM. and other digital logic circuits y Two important characteristics y high noise immunity y low static power consumption. y CMOS circuits y use a combination of p-type and n-type metal oxide semiconductor field-effect transistors (MOSFETs) to implement logic gates and other digital circuits . y used in microprocessors. microcontrollers.

.CMOS INVERTER (INPUT=0) y When the voltage of input A is low. y NMOS The output therefore registers a high voltage. y This limits the current that can flow from Q to ground. the voltage drop between the supply voltage and Q due to a current drawn from Q is small. y Because the resistance between the supply voltage and Q is low. the NMOS transistor's channel is in a high resistance state. PMOS y The PMOS transistor's channel is in a low resistance state and much more current can flow from the supply to the output.

CMOS INVERTER (INPUT=1) y when the voltage of input A is high. y NMOS This low drop results in the output registering a low voltage. . y Because the resistance between Q and ground is low. allowing the output to drain to ground. the voltage drop due to a current drawn into Q placing Q above ground is small. the PMOS transistor is in an off (high resistance) y limit the current flowing from the positive supply to the output PMOS y the NMOS transistor is in an on (low resistance) state.

y If either of the A or B inputs is low. y both the NMOS transistors will conduct y neither of the PMOS transistors will conduct y a conductive path will be established between the output and Vss (ground). y a conductive path will be established between the output and Vdd (voltage source). PMOS NMOS . y one of the PMOS transistors will. bringing the output low. bringing the output high.CMOS NAND GATE y A and B inputs are high. y one of the NMOS transistors will not conduct.

.and the complementary '1' is gate input to the pMOS. both are turned off. y However when gate input to the nMOS is '1' and its complementary '0' is the gate input to the pMOS. y The use of transmission gates eliminates the undesirable threshold voltage effects which give rise to loss of logic levels in pass transistor logic. y See the truth table at the right.CMOS TRANSMISSION GATE y when the gate input to the nMOS transistor is '0'. both are turned on and passes any signal '1' or '0' equally well without degradation.

Q4 is also at cut-off. . y Since Q2 is not conducting. and the diode connecting Q1 emitter and Q2 collector. Q1 Conducts.TRI-STATE TTL GATE y when Enable En is HIGH. conducts driving Q3 into cut-off. output Z is in high-impedance state. When both pull-up and pull-down transistors are not conducting. it works like any other NAND gate. y But when Enable En is driven LOW.

BASIC CONCEPT y Propagation Delay y Power Dissipation y Noise immunity y Fan-in y Fan-out .

y Low to high transition delay is called turn-on delay and High to low transition delay is called turn-off delay. before it reaches the gate output. . y The figure shows a NOT gate with a delay of "Delta".com/digital/logic1.asic-world.PROPAGATION DELAY y http://www.html y Gate delay / Propagation Delay y is the delay offered by a gate for the signal appearing at its input. where output X' changes only after a delay of "Delta".

y ICCT: Current drawn during HIGH to LOW. . It draws a certain amount of current during its operation. y ICCL: Current drawn during LOW state. Transition or Low state. y ICCH: Current drawn during HIGH state. there are three different currents drawn from power supply.POWER DISSIPATION y Each gate is connected to a power supply VCC (VDD in the case of CMOS). Since each gate can be in a High. LOW to HIGH transition.

ICCH and ICCL current is negligible. If we assume that ICCH and ICCL are equal then. y So for TTL like logics family. . So the Average power dissipation is calculated as below. power dissipation does not depend on frequency of operation.POWER DISSIPATION y For TTL. Average Power Dissipation = Vcc * (ICCH + ICCL)/2 y For CMOS. ICCT the transition current is negligible. in comparison to ICCH and ICCL. and for CMOS the power dissipation depends on the operation frequency. in comparison to ICCT. Average Power Dissipation = Vcc * ICCT.

y y Pd (Dynamic Power Dissipation): y y Power consumed during output and input transitions. y Normally static power dissipation is caused by leakage current. So we can say Pd is the actual power consumed i. y Thus Total power dissipation = static power dissipation + dynamic power dissipation.POWER DISSIPATION y Ps (Static Power Dissipation): Power consumed when the output or input are not changing or rather when clock is turned off. .e. the power consumed by transistors + leakage current.

NOISE IMMUNITY y NOISE IMMUNITY y The maximum noise level that can be added to logic levels while still maintaining error-free operation. whereas the speedy ECL family has less . y CMOS has greater voltage noise immunity than TTL.

FAN-IN y http://en. An AND gate with three inputs has a fanin of 3. . because the complexity of the input circuitry increases the input capacitance of the device.org/wiki/Fan-in y Fan-in is the number of inputs of an electronic logic gate. y For instance the fan-in for the AND gate shown below is 3.wikipedia. y Physical logic gates with a large fan-in tend to be slower than those with a small fan-in.

org/wiki/Fan-out y FAN-OUT y measure of the ability of a logic gate output. implemented electronically. y fanout is simply the number of inputs that can be connected to an output before the currents required by the inputs exceeds the current that can be delivered by the output while still maintaining correct logic levels. y to drive a number of inputs of other logic gates of the same type.wikipedia. .FAN-OUT y http://en.

htm Interfacing any TTL gate to any CMOS gate using the same power supply (5V) Interfacing an OpenCollector TTL gate to any CMOS gate using different power supplies .com/interfacing- ttl-cmos.INTERFACING TTL TO CMOS y http://ecelab.

INTERFACING TTL TO CMOS y it would be good to use an NPN transistor to translate the TTL output voltage level to a correct CMOS input voltage level as shown so as not to overstress the TTL gate. Interfacing any TTL gate to any CMOS gate using different power supplies .

INTERFACING CMOS TO TTL Interfacing any CMOS gate to any TTL gate using the same power supply (5V) Interfacing an OpenCollector TTL gate to any CMOS gate using different power supplies .

y The example in Figure 3 is an inverting buffer. Figure 3: Interfacing any TTL gate to any CMOS gate using different power supplies . so the input to the TTL gate is an inverted logic of the CMOS output.INTERFACING CMOS TO TTL y Instead of a transistor. a CMOS buffer (inverting or non-inverting) may be used as long as it is supplied from the 5-V TTL supply.