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Chapter #9: Finite State Machine Optimization

No. 9-1

Chapter Outline Procedures for optimizing implementation of an FSM State Reduction State Assignment Computer Tools for State Assignment: Nova, Mustang, Jedi Choice of Flipflops FSM Partitioning

No. 9-2

Motivation Basic FSM Design Procedure: (1) Understand the problem (2) Obtain a formal description (3) Minimize number of states (4) Encode the states (5) Choose FFs to implement state register (6) Implement the FSM Next Chapter This Chapter!

No. 9-3

9-4 . Reduce later No. but require different implementations Design state diagram without concern for # of states.Motivation State Reduction 0 0 S0 [0] S0 [0] 0 S [ ] S [ ] S [0] 0 0 Odd Parity Checker: two alternative state diagrams Identical output behavior on all input strings FSMs are equivalent.

Motivation State Reduction (continued) Implement FSM with fewest possible states Least number of flipflops Boundaries are power of two number of states Fewest states usually leads to more opportunities for don't cares Reduce the number of gates needed for implementation No. 9-5 .

9-6 .State Reduction Goal Identify and combine states that have equivalent behavior Equivalent States: for all input combinations. states transition to the same or equivalent states Odd Parity Checker: S . S2 are equivalent states Both output a Both transition to S1 on a 1 and self-loop on a Algorithmic Approach Start with state transition table Identify states with same output behavior If such states transition to the same next state. they are equivalent Combine into a single new renamed state Repeat until no new states are combined No.

9-7 . .State Reduction Row Matching Method Example FSM Specification: Single input X. . output Z Taking inputs grouped four at a time. .. output 1 if last four inputs were the string 1 1 or 11 Example I/O Behavior: X= Z= 1 11 11 1 1 1 1 11 . Upper bound on FSM complexity: Fifteen states (1 + 2 + 4 + 8) Thirty transitions (2 + 4 + 8 + 16) sufficient to recognize any binary string of length four! No..

State Reduction Row Matching Method State Diagram for Example FSM: Re et No. 9-8 .

State Reduction Row Matching Method Initial State Transition Table: Input Sequence Reset 0 1 00 01 10 11 000 001 010 011 100 101 110 111 Next State Output Present State X =0 X =1 X =0 X =1 0 0 S2 S0 S1 0 0 S4 S1 S3 0 0 S6 S2 S5 0 0 S8 S3 S7 0 0 S4 S9 S10 0 0 S5 S11 S12 0 0 S6 S13 S14 0 0 S0 S7 S0 0 0 S0 S8 S0 0 0 S0 S9 S0 0 1 S0 S10 S0 0 0 S0 S11 S0 0 1 S0 S12 S0 0 0 S0 S13 S0 0 0 S0 S14 S0 No. 9-9 .

State Reduction Row Matching Method Initial State Transition Table: Input Sequence Reset 0 1 00 01 10 11 000 001 010 011 100 101 110 111 Next State Output Present State X =0 X =1 X =0 X =1 0 0 S2 S0 S1 0 0 S4 S1 S3 0 0 S6 S2 S5 0 0 S8 S3 S7 0 0 S4 S9 S10 0 0 S5 S11 S12 0 0 S6 S13 S14 0 0 S0 S7 S0 0 0 S0 S8 S0 0 0 S0 S9 S0 0 1 S0 S10 S0 0 0 S0 S11 S0 0 1 S0 S12 S0 0 0 S0 S13 S0 0 0 S0 S14 S0 No. 9-1 .

State Reduction Row Matching Method Input Sequence Reset 0 1 00 01 10 11 000 001 010 011 or 101 100 110 111 Output Next State Present State X =0 X =1 X =0 X=1 0 0 S0 S2 S1 0 0 S1 S4 S3 0 0 S2 S6 S5 0 0 S3 S8 S7 0 0 S4 S'10 S9 0 0 S5 S'10 S11 0 0 S6 S14 S13 0 0 S7 S0 S0 0 0 S8 S0 S0 0 0 S9 S0 S0 0 1 S'10 S0 S0 0 0 S11 S0 S0 0 0 S13 S0 S0 0 0 S14 S0 S0 No. 9-11 .

State Reduction Row Matching Method Input Sequence Reset 0 1 00 01 10 11 000 001 010 011 or 101 100 110 111 Output Next State Present State X =0 X =1 X =0 X=1 0 0 S0 S2 S1 0 0 S1 S4 S3 0 0 S2 S6 S5 0 0 S3 S8 S7 0 0 S4 S'10 S9 0 0 S5 S'10 S11 0 0 S6 S14 S13 0 0 S7 S0 S0 0 0 S8 S0 S0 0 0 S9 S0 S0 0 1 S'10 S0 S0 0 0 S11 S0 S0 0 0 S13 S0 S0 0 0 S14 S0 S0 No. 9-12 .

9-13 .State Reduction Row Matching Method Input Sequence Reset 0 1 00 01 10 11 not (011 or 101) 011 or 101 Next State Output Present State X =0 X =1 X =0 X=1 S0 S1 S2 0 0 S1 S3 S4 0 0 S2 S5 S6 0 0 S3 0 0 S'7 S7 ' S4 0 0 S'10 S7 ' S5 0 0 S'10 S7 ' S6 0 0 S'7 S7 ' S'7 S0 S0 0 0 S'10 S0 S0 1 0 No.

State Reduction Row Matching Method Input Sequence Reset 0 1 00 01 10 11 not (011 or 101) 011 or 101 Next State Output Present State X =0 X =1 X =0 X=1 S0 S1 S2 0 0 S1 S3 S4 0 0 S2 S5 S6 0 0 S3 0 0 S'7 S7 ' S4 0 0 S'10 S7 ' S5 0 0 S'10 S7 ' S6 0 0 S'7 S7 ' S'7 S0 S0 0 0 S'10 S0 S0 1 0 No. 9-14 .

9-15 .State Reduction Row Matching Method Input Se uence Reset 0 1 00 or 11 01 or 10 not (011 or 101) 011 or 101 resent State S0 S1 S S ' S ' S ' S10' Ne t State 0 1 S1 S S ' S ' S ' S ' S ' S ' S ' S10' S0 S0 S0 S0 utput 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Final Reduced State Transition Table Reset S0 00 S1 00 10 10 10 S 00 S ' 00 S ' 010 01 10 S10' 10 Corresponding State Diagram 010 S ' No.

State Reduction Row Matching Method Straightforward to understand and easy to implement Problem: does not allows yield the most reduced state table! Example: 3 State Odd Parity Checker Next State X =0 X =1 S1 S0 S2 S1 S1 S2 Present State S0 S1 S2 Output 0 1 0 No way to combine states S and S2 based on Next State Criterion! No. 9-16 .

Single output Z Output a 1 whenever the serial sequence 1 or 11 has been observed at the inputs State transition table: Input Sequence Reset 0 1 00 01 10 11 Next State Present State X=0 X =1 S1 S2 S0 S3 S4 S1 S5 S6 S2 S0 S0 S3 S0 S0 S4 S0 S0 S5 S0 S0 S6 Output X =0 X=1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 No.State Reduction Implication Chart Method New example FSM: Single input X. 9-17 .

9-18 .State Reduction Implication Chart Method Enumerate all possible combinations of states taken two at a time S S1 Next States Under all Input Combinations S1 S S S S S S S1 S S S S S S S1 S S S S S S S S S Naive Data Structure: Xij will be the same as Xji Also. can eliminate the diagonal Implication Chart No.

9-19 .1> contains entries S1-S3 (transition on zero) S2-S4 (transition on one) S S1-S3 S2-S4 S1 No. Sj have different output behavior. then Xij is crossed out Example: S transitions to S1 on . S2 on 1. S4 on 1. So square X< . S1 transitions to S3 on . Column is Sj Si is equivalent to Sj if outputs are the same and next states are equivalent Xij contains the next states of Si. Sj which must be equivalent if Si and Sj are equivalent If Si.State Reduction Implication Chart Filling in the Implication Chart Entry Xij ?Row is Si.

State Reduction Implication Chart Method S2 and S4 have different I/O behavior This implies that S1 and S cannot be combined S1 S2 S S4 S S S1-S S2-S4 S1-S S -S S2-S S4-S S1-S S -S S -S S2-S S4-S S -S S1-S S -S S -S S -S S2-S S4-S S -S S -S S -S S -S S S1 S2 S S4 S Starting Implication Chart No. 9-2 .

9-21 .State Reduction Implication Chart Method S1 Results of First Marking Pass Second Pass Adds No New Information S3 and S5 are equivalent S4 and S6 are equivalent This implies that S1 and S2 are too! S2 S3 S4 S5 S6 S0 S3-S5 S4-S6 S0-S0 S0-S0 S0-S0 S0-S0 S1 S2 S3 S4 S5 Input Sequence Reset Reduced State 0 or 1 Transition Table 00 or 10 01 or 1 1 Next State Present State X =0 X =1 S0 S1 ' S'1 S1 ' S3 ' S'4 S3 ' S0 S0 S4 ' S0 S0 Output X =0 X =1 0 0 0 0 0 0 1 0 No.

State Reduction Multiple Input State Diagram Example
00 10 00 01 10 11 01

S0

S1 0]

11

Pre ent tate
0 1 2 3

00
0 0 1 1 0 1

ext tate 01 10 11
1 3 3 0 1 4 2 1 2 4 2 0 3 5 4 5 5 5

utput 1 0 1 0 1 0

00

S2
10 11

01

01

00

10

S3 0]
11 00

4 5

Symbolic State Diagram

10 00

01

10 11 01

S4

S5 0]

11

State Diagram

No. 9-22

State Reduction Multiple Input Example
S1

S2

S -S1 S1-S3 S2-S2 S3-S4 S -S1 S3-S S1-S4 S5-S5 S -S S1-S1 S2-S2 S3-S5 S -S1 S3-S4 S1-S S5-S5 S S1 S2 S1-S S3-S1 S2-S2 S4-S5 S1-S1 S -S4 S4-S S5-S5 S3 S4

S3

Present State S'0 S1 S2 S'3

Next State 00 01 10 S0' S1 S2 S0' S3' S1 S1 S3' S2 S1 S'0 S'0

Output 11 S3' S3' S0' S'3 1 0 1 0

Minimized State Table

S4

S5

Implication Chart

No. 9-23

State Reduction Implication Chart Method Does the method solve the problem with the odd parity checker?

S1
Implication Chart

S

S -S S1 -S1 S S1

S is equivalent to S2 since nothing contradicts this assertion!

No. 9-24

Construct implication chart. then Xi. Sn and that pair labels a square already labeled "X". Square labeled Xi. if outputs differ than square gets "X". No. Continue executing Step 3 until no new squares are marked with "X".j contains next state pair Sm. one square combination of states taken two at a time for each 2. 9-25 .j. If square Xi.j.State Reduction Implication Chart Method The detailed algorithm: 1. For each remaining unmarked square Xi. Advance through chart top-to-bottom and left-to-right. 4. 5. then Si and Sj are equivalent.j is labeled "X". Otherwise write down implied state pairs for all input combinations 3.

HY. 2 for third.State Assignment When FSM implemented with gate logic. Red=1 No. number of gates will depend on mapping between symbolic state names and binary encodings 4 states = 4 choices for first state. 3 for second. 9-26 ¡   ¡   ¡   t t t Q Q HG HG HG HY HY FG FG FG FY FY ¡   t t t T H t H t F F . FY Green= . Yellow= 1. 1 for last = 24 different encodings (4!) Example for State Assignment: Traffic Light Controller HG HY FG FY HG HY FG FY I C t TL T r HG HG HY HY FG FG FY FY FY HG 24 state assignments for the traffic light controller Symbolic State Names: HG. FG.

o 7 .State Assignment Some Sample Assignments for the Traffic Light Controller Espresso input format: .FG FY 11 -1.ilb c tl ts q1 q .ob p1 p st h1 h f1 f . HY = 1 .e Two assignments: HG = HG = . FG = 11.HG HG 1 11. FY = 11 No.FG FG 1 -. FG = 1.HG HG 1 .HG HY 1 1 -.. 9-27 .i 5 . HY = 1.HY HY 11 --1 HY FG 1 11 1 . FY = 1 .HY FY 1 1 --1 HY HG 11 1 .FG FY 11 -.p 1 -.

State Assignment Random Assignments Evaluated with Espresso ..1 --11 1 11 -1-11 1 11 .11 11 1 1 .i 5 .ob p1 p st h1 h f1 f .1 1 -.1 1 1 --11 11 1 --.ob p1 p st h1 h f1 f .e 26 literals 9 unique terms several 5 and 4 input gates 13 gates total 21 literals 8 unique terms no 5 input gates. 2 4 input gates 14 gates total No.1 1 1 1 --.1 1 1 -.p 8 11.ilb c tl ts q1 q .p 9 1111 1 -11 11 1 --1 1 1 1 -.i 5 .o 7 . 9-28 .ilb c tl ts q1 q .1 1 1 --11 11 1 --111 11 1 ---1 --.1 1 1 -.o 7 .e .

9-29 1 S1 S State Map .State Assignment Pencil & Paper Heuristic Methods State Maps: similar in concept to K-maps If state X transitions to state Y. then assign "close" assignments to X and Y S Assignment State Name S S1 S S3 S4 1 Assignment State Name S S1 S S3 S4 1 1 1 S1 S 1 1 1 1 1 1 1 1 1 1 1 1 1 1 S3 1 Assignment 1 Assignment S4 1 S 11 S4 10 S3 1 S 1 11 10 S1 S3 S S4 State Map No.

traffic light controller: HG = . FG = 11.g.State Assignment Paper and Pencil Methods Minimum Transition Distance Criterion First Assignment Second Assignment Bit Changes Bit Changes 1 2 3 1 3 1 1 2 1 1 2 2 13 7 Transition S to S1: S to S2: S1 to S3: S2 to S3: S3 to S4: S4 to S1: This heuristic is not likely to achieve the best assignment! E. FY = 1 yields minimum transition distance.. HY = 1. 9-3 . but turned out not best assignment as shown in 9-28! No.

9-31 .State Assignment Paper & Pencil Methods Alternative heuristics based on input and output behavior as well as transitions: E i/j F i/ Adjacent assignments to: states that share a common next state for a given input (group 1's in next state map) i hest Priorit E Medi E i/j F Priorit F i/j states that share a common ancestor state (group 1's in next state map) states that have common output behavior (group 1's in output map) o est Priorit No.

S3') 1/ : (S .1/ S1' 1/ / Highest Priority: (S3'.State Assignment Pencil and Paper Methods Example: 3-bit Sequence Detector eset S . S4') 1/ . 9-32 . S1'. S3'.1/ S3' S4' No. S1'. / : (S . S4') Medium Priority: (S3'. S4') Lowest Priority: /1.

State Assignment Paper and Pencil Methods Q Q1 S 1 S3' 1 S1' S4' Reset State = Q Q1 S 1 S1' Highest Priority Adjacency 1 S3' S4' Not much difference in these two assignments No. 9-33 .

S4'). S1 ') Lowest Priority: / : (S . S1.1/ /1 / 1/ 1/ 1/ S2 / S4' 1/ S1 ' 1/ Highest Priority: (S3'. S1 ') Medium Priority: (S1. S7') No. S4').State Assignment Paper & Pencil Methods Another Example: 4 bit String Recognizer Reset S / S1 / S3' . S4'. S7') 1/ : (S . (S7'. S2. 2x(S3'. 9-34 . S1. (S7'. S4'. S3'. S2). S2.1/ S7' . S3'.

(S7'. S2). S1 ') placed adjacently 1 11 1 S4' S1 ' S4' S1 ' S4' S1 ' S7' S2 No. (S3'.State Assignment Paper & Pencil Methods State ap 1 2 S 1 1 2 S 1 1 2 S 1 1 2 S 1 1 S1 S2 (a) 11 S3' 1 S7' 1 2 S 1 11 S3' 1 S7' 1 1 1 S1 11 S3' S4' S1 ' ( ) 1 2 S S7' 1 11 S3' S4' 1 1 1 11 S3' 1 1 2 S S7' S1 ' 1 2 S 1 1 1 11 1 1 11 1 = Reset = S (S1. S4'). 9-35 .

State Assignment Effect of Adjacencies on Next State Map (Q1.Q3 (a) in the previous slide Current State (S0 ) 000 (S1 ) 001 (S2 ) 101 ( S'3 ) 011 (S4 ) 111 ' ( S'7) 010 (S'10 ) 110 Next State X =0 X=1 001 101 011 111 111 011 010 010 010 110 000 000 000 000 P1. 9-36 .P3) Q2 Q1 00 Q0 X 00 0 01 11 10 1 1 0 01 0 0 0 0 P2 11 0 0 1 0 10 X X 0 1 Q2 Q 1 00 Q0 X 00 0 01 11 10 0 1 1 01 0 0 1 1 P1 11 0 0 1 1 10 X X 1 1 Q2 Q1 00 Q0 X 00 1 01 11 10 1 1 1 01 0 0 0 0 P0 11 0 0 0 0 10 X X 1 1 Current State ( S0) 000 ( S1) 001 ( S2) 010 ( S3 ) 011 ' ( S4 ) 100 ' ( S'7) 101 (S'10 ) 110 Next State X =0 X=1 010 001 011 100 011 100 101 101 110 101 000 000 000 000 Q2 Q1 00 Q0 X 00 0 01 11 10 0 1 0 01 1 0 1 1 P2 11 0 0 X X 10 1 1 0 0 Q2 Q1 00 Q0 X 00 0 01 11 10 1 0 1 01 0 1 0 0 P1 11 0 0 X X 10 0 1 0 0 Q2 Q1 00 Q0 X 00 1 01 11 10 0 0 1 01 0 1 1 1 P0 11 0 0 X X 10 1 0 0 0 First encoding exhibits a better clustering of 1's in the next state map No.P2.Q2.

0100 1000 11000 --0 0010 1000 01001 --1 0010 0001 11001 .p 10 0-.State Assignment One Hot Encodings to reduce next-state and output logic complexity n states encoded in n flipflops 1 HG = HY = 1 FG = 1 FY = 1 .0001 0001 00010 -0.o 9 .ob p3 p2 p1 p0 st h1 h0 f1 f0 .ob p3 p2 p1 p0 st h1 h0 f1 f0 .e Espresso Inputs Espresso Outputs No.e Complex logic for discrete gate implementation .p 8 10-0100 010001000 11-0001 001010010 -0-0001 000100010 0--0001 000100010 0--0100 100011000 -1-0100 100011000 --00010 101001111 --10010 010111111 .i 7 .o 9 .0100 0100 01000 0-.ilb c tl ts q3 q2 q1 q0 .i 7 . 9-37 .0001 0001 00010 11.ilb c tl ts q3 q2 q1 q0 .0001 0010 10010 --0 0010 0010 00110 --1 0010 0100 10110 10.0100 1000 11000 -1.

all the terms are too complicated with many literals  Could be OK if PLAbased design used No.State Assignment One Hot Encoding Results:  Yields eight product terms cf.9-28  But. 9-38 . P.

State Assignment Computer-Based Methods NOVA: State Assignment for 2-Level Circuit Networks Input Constraints: states with same i/o mapped to same next state Output Constraints: states which are successors of same predecessor NOVA Input File for the Traffic Light Controller inputs current_state next_state outputs 0--011--0 --1 100--1--0 --1 HG HG HG HY HY FG FG FG FY FY HG HG HY HY FG FG FY FY FY HG 00010 00010 10010 00110 10110 01000 11000 11000 01001 11001 nova -e <encoding strategy> -t <nova input file> No. 9-39 .

but uses an even improvement strategy 1-Hot: uses a 1-hot encoding Random: uses a randomly generated encoding No.State Assignment Computer-Based Methods Greedy: satisfy as many input constraints as possible Hybrid: satisfy input constraints. more sophisticated improvement strategy I/O Hybrid: satisfy both input and output constraints Exact: satisfy ALL input conditions Input Annealing: like hybrid. 9-4 .

State Assignment Computer-Based Methods HG HY 11 11 11 1 1 1 11 1 FG 1 1 1 11 11 1 1 1 1 FY 1 1 # of Product Terms 9 9 1 9 9 9 Greedy (-e ig): Hybrid (-e ih): Exact (-e ie): IO Hybrid (-e ioh): I Annealing (-e ia): Random (-e r): -z HG on the command line forces NOVA to assign to state HG No. 9-41 .

State Assignment Computer Based Methods More NOVA Examples: 3-bit Recognizer 0 1 0 1 S0 S1 S1 S3 S4 S4 S1 S3 S4 S0 S0 S0 0 0 0 0 1 0 Greedy: Hybrid: Exact: IO Hyb: I Ann: Random: S0 00 00 00 00 00 00 S1' 01 01 01 10 01 11 S3' 11 10 10 01 11 10 S4' 10 11 11 11 10 01 terms 4 4 4 4 4 4 No. 9-42 .

9-43 .State Assignment Computer Based Methods More NOVA Examples: 4-bit Recognizer 0 1 0 1 0 1 0 1 0 1 S0 S0 S1 S1 S2 S2 S3 S4 S4 S7 S10 S10 S1 S2 S3 S4 S4 S3 S7 S7 S7 S0 S0 S0 0 0 0 0 0 0 0 0 0 0 1 0 S0 100 101 101 110 100 011 S1 110 110 110 011 101 100 S2 010 111 111 001 001 101 Q1 Q0 Q2 0 1 00 S7 ' S0 01 S2 S1 S'3 11 10 S10 ' S'4 Same adjacencies as the heuristic method Greedy: Hybrid: Exact: IO Hyb: I Ann: Rand: S3' 011 001 001 100 111 110 S4' 111 011 011 101 110 111 S7' 000 000 000 000 000 000 S10' terms 001 7 010 7 010 7 010 7 010 6 001 7 No.

o 5 .i 3 .State Assignment Mustang Oriented towards multi-level logic implementation Goal is to reduce literal count.s 2 0--011--0 --1 100--1--0 --1 # inputs # outputs # of state bits HG HG HG HY HY FG FG FG FY FY HG HG HY HY FG FG FY FY FY HG 00010 00010 10010 00110 10110 01000 11000 11000 01001 11001 No. rather than product terms Input Format: . 9-44 .

State Assignment Mustang Goal: maximum common subexpressions in next state function Encoding Strategies: Random Sequential One-Hot Fan-in: states with common predecessors given adjacent assignment Fan-out: state with common next state and outputs given adjacent assignments No. 9-45 .

must run misII . 9-46 To obtain multilevel implementations.State Assignment Mustang Traffic Light: Random: Sequential: Fan-in: Fan-out: HG 01 01 00 10 HY 10 10 01 11 FG 11 11 10 00 FY 00 00 11 01 # product terms 9 9 8 8 3 Bit String Recognizer: S0 S1 Random: 01 10 Sequential: 01 10 Fan-in: 10 11 Fan-out: 10 11 S3' 11 11 00 00 S4' 00 00 01 01 # product terms 5 5 4 4 4 Bit String Recognizer: S0 S1 S2 Random: Sequential: Fan-in: Fan-out: 101 001 100 110 010 010 010 010 011 011 011 011 S3' 110 100 000 100 S4' 111 101 001 101 S7' 001 110 101 000 S10' # product terms 000 8 111 8 110 8 001 6 No.

9-47 .0 .1 # of states.enum .0 . encoding bit length States 4 2 HG HY FG FY Colors 3 2 GREEN RED YELLOW HG HG 0 GREEN RED HG HG 0 GREEN RED HG HY 1 GREEN RED HY HY 0 YELLOW RED HY FG 1 YELLOW RED FG FG 0 RED GREEN FG FY 1 RED GREEN FG FY 1 RED GREEN FY FY 0 RED YELLOW FY HG 1 RED YELLOW Kinds of states Kinds of outputs General encoding problems: best encodings for states and outputs Encoding Strategies: Random Straightforward One Hot Input Dominant Output Dominant Modified Output Dominate I/O Combination No..o 4 ...State Assignment JEDI Input Format: ...1 ..0 1 1 .i 4 .enum 0 .1 1 0 0 .

: 10 11 00 01 Output': 10 11 00 01 4 Bit String Recognizer: S0 S1 S2 S3' Input: 111 101 100 010 Output: 101 110 100 010 Comb. 9-48 .State Assignment JEDI Traffic Light: HG HY Input: 00 10 Output: 00 01 Comb: 00 10 Output': 01 00 FG 11 11 11 10 FY 01 10 01 11 Grn 11 10 10 10 Yel 01 11 00 00 Red 00 01 01 01 # product terms 9 9 9 10 3 Bit String Recognizer: S0 S1 S3' S4' Input: 01 10 11 00 Output: 01 10 11 00 Comb. must run misII No.: 100 011 111 110 Output': 001 100 101 010 # product terms 4 4 4 4 S4' 110 000 010 011 S7' 011 111 000 000 S10' # product terms 001 7 011 7 101 7 111 8 To obtain multilevel implementations.

9-49 .State Assignment Mustang vs. Jedi Traffic Light Controller Q1 = HL TS + FL  TS' + FL '  P1 Q = Q1  C'  P1 + C  TL  P ' + TS'  P ST = Q  P ' + Q '  P HL1 = FL + P1  P ' HL = P1'  P FL1 = P1' FL = HL '  P Q1 = HL1  C  TL + HL + FL1  C  TL' Q = HL  TS + FL1 + FL  TS' ST = Q1  HL1 + Q1'  FL + HL1'  FL1'  TS HL1 = P1' P ' HL = P1  P ' FL1 = HL '  P1 FL = HL1'  P1' Mustang Fewer wires Jedi Fewer literals No.

good for VLSI implementations Procedure: 1. derive the next state maps from the state transition table 2. Given state assignments. increase # of connections D FFs: simplify implementation process. decrease # of connections.Choice of Flipflops J-K FFs: reduce gate count. Minimize the remapped next state function No. Remap the next state maps given excitation tables for a given FF 3. 9-5 .

Choice of Flipflops Examples 4 bit Sequence Detector using NOVA derived state assignment Pre ent tate 000 0 011 1 010 101 '3 111 '4 100 ') ' 110 10 ) Next tate I =0 I =1 011 1 ) ) 010 101 3 ) ' 111 '4) 111 '4) 101 '3 ) 100 100 ' ) ') 110 100 ' 10 ) 000 ') Next tate I =0 I =1 011 010 111 101 000 100 000 100 101 111 000 100 000 110 No. 9-51 Encoded State Transition Table utput I =0 I =1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Encoded Next State Map Pre ent tate 000 001 010 011 100 101 110 111 .

Choice of Flipflops ¤ Q Q £ D = Q2Q1 + Q Q2+ D = Q1  Q  I + Q2  Q  I + Q2  Q1 Q I ¤ £ Q1+ Q Q £ D Q + = Q2  Q1 + Q2  I ¢ ¤ Q Q £ ¢ 6 product terms 15 literals Q I Q ¤ ¢ ¢ D FF Implementation Q I X X Q + X X Q + X X + No. 9-52 .

9-53 .Choice of Flipflops J-K Implementation Re apped Next State Next State Present State 000 001 010 011 100 101 110 111 I =0 I =1 011 010 XXX XXX 111 101 101 111 000 000 100 100 000 000 100 110 J I =0 011 XXX 1X1 1XX X00 X0X XX0 XXX K I =0 XXX XXX X0X X10 1XX 0X1 11X 011 J I=1 010 XXX 1X1 1XX X00 X0X XX0 XXX K I =1 XXX XXX X1X X00 1XX 0X1 11X 001 Remapped Next State Table No.

J Q2+ = Q1 Q + J Q1+ = Q2 K Q1+ = Q  I + Q  I + Q2  Q © Q + Q + K Q + = Q2 9 unique terms 14 literals  Q + § ¦  § Q Q ¦ Q Q ¥ J Q + = Q2  Q1 + Q2  I Q I ¥ § ¦ © § Q Q ¦ Q Q Q I ¥ Q I ¥ Q I Q + ¨ ¨ K Q2+ = Q § Q + ¦ § Q Q ¦ Q Q ¥ ¥ Choice of Flipflops J-K Implementation (continued) Q I Q I No. 9-54 .

9-55 .t te d O t t F cti s o t ts rti io eco d rti io t t e t t e Example of Input/Output Partitioning: 5 outputs depend on 15 inputs 5 outputs depend on different overlapping set of 15 inputs No.Finite State Machine Partitioning Why Partition? mapping FSMs onto programmable logic components: limited number of input/output pins limited number of product terms or other programmable resources First i s Next.

Finite State Machine Partitioning Introduction of Idle States in the hope of reducing # of terms In the next-state functions Before Partitioning C1 S1 C2 S6 C3 S2 S5 S3 C4 C5 S4 No. 9-56 .

9-57 .Finite State Machine Partitioning Introduction of Idle States After Partitioning C2S6 C1 S1 C2S6 C3+C5 SB C3S2 + C4S3 S5 S6 SA C1S1 C2 S2 C1S1 + C3S2 + C4S3 + C5S2 C4 S3 C5S2 S4 No.

Finite State Machine Partitioning Rules for Partitioning Rule #1: Source State Transformation. SA is the Idle State S1 C1 C1 S6 S1 SA Rule #2: Destination State Transformation S1 C2 S6 S1 C2S6 SA No. 9-58 .

9-59 .Finite State Machine Partitioning Rules for Partitioning Rule #3: Multiple Transitions with Same Source or Destination C3 S2 S5 S2 C3+C5 C3S2 + C4S3 SA S3 C4 C5 S4 S3 C4 SB S5 C5S2 S4 Rule #4: Hold Condition for Idle State C2S6 S1 C2S6 SA No.

9-6 .Finite State Machine Partitioning Another Example D S U D D U U S4 U D S2 D U S3 U D S5 S1 6 state up/down counter building block has 2 FFs + combinational logic No.

S2. leaves after S5 S5 goes to SB and holds. S4. SB Count sequence S . S1. S3. leaves after S2 Down sequence is similar No.Finite State Machine Partitioning 6 State Up/Down Counter S D U U  S5 S1 U D S2 U SA D  S3 D  S + U  S2 D SB D US5 + DS3 DS U S5 D U S4 U  S2 U D S3 Introduction of the two idle state SA. S5: S2 goes to SA and holds. 9-61 .

Chapter Summary Optimization of FSM State Reduction Methods: Row Matching. 9-62 . Implication Chart State Assignment Methods: Heuristics and Computer Tools Implementation Issues Choice of Flipflops Finite State Machine Partitioning No.