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130nm is the worst node across the industry for latchup. As a result we will be implementing DRC checks to increase our robustness against Latch-Up. LSI Proprietary 2 . Unfortunately.   According to Chester. COM2 has had many parts fail latch-up over the last couple years. In COM2 we had hoped that our epi on highly doped P+ substrate would protect us from latch up concerns.

(2 and 3) | |  ! !_  || . ‡ Beta can generally be reduced by increasing the width of the base regions._  ‡ Latch up is caused by an SCR (PNPN) structure with enough current gain (beta) to generate a self sustaining voltage drive.! ||    "  .

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ARIABLE NETS_P3 " CC" ARIABLE NETS_P2 " N12_ CC" " P33" " POS_33" ARIABLE NETS_P1PV " P2V ARIABLE NETS_P1 " N30_ CC" " P12" " POS_12 ARIABLE NETS_0 "GND?" " NEG ARIABLE NETS_N1 " P33_ EE" " N12" " NEG_12 ARIABLE NETS_N2 " P12_ EE" " N30" " NEG_30 ARIABLE NETS_N3 " EE" " SUB" LSI Confidential  .

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.$ 2 ‡ Additional rules control distance to tub contacts within adjacent NTUBs ‡ If an NWELL guard is placed between NTUBs rules become slightly less strict ± Don¶t rely on this.. . use smart placement of supply domains  . .

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 toward safe placement ± High Supply † Top of Cell #  # #  ± Mid supply devices/cascodes/etc in the middle #  ± Low Supply † Bottom of Cell #  ‡ Be careful when cells will be tiled  -  LSI Proprietary ý .

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1% ‡ Automated Checking via the DRC deck ± Tubs are identified as belonging to specific supply groups ± Minimum distance is a function of the assumed voltages of specific tubs ‡ Checks: ± Top Level: Supplies will be identified by chip pins and regulator pins ± Cell Level: Strict naming conventions should be adhered as much as possible. LSI Proprietary „ . ‡ Cells with multiple supply levels (> 3.3 ) ± Treat these cells as critical cells (like noise sensitive or high-speed) ± Good latchup prevention starts with designer device placement! ± If cell will be replicated. make certain arrays of cells won¶t generate an error ‡ Devices not connected to supplies but with strong drive are not checked and could also latch. Keep your eyes open. Failure to name pins correctly will result in checks missing errors.

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