GATE WAY TO SRAM

(STATIC RANDOM ACCESS MEMORY)

BY,
P. VAMSIKUMAR,
REGD NO:122120130
MTECH(VLSI)
 CONTENTS
Classification of Memory arrays
Ram
Introduction
Operation of SRAM CELL
Different states of SRAM
Advantages and disadvantages of SRAM
Applications
Top spice implementation and O/P waveforms
Conclusion
References
RAM
    Robert Dennard was the inventor of RAM:
Random Access Memory, the device was
patented in 1968 by Dennard.
which functions as the computer's primary
workspace. The "random" in RAM means that
the contents of each byte can be directly
accessed without regard to the bytes before or
after it.
This is also true of other Volatile RAM chips
require power to maintain their data, which is
why you must save your data onto disk before
you turn the computer off.
CLASSIFICATION OF
MEMORY ARRAYS
Memory is a collection of storage cells with associated input
and output circuitry
Possible to read and write cells

Random access memory (RAM) contains words of

information.

Data can be accessed using a sequence of signals.

Leads to timing waveforms.

Decoders are an important part of memories

Selects specific data in the RAM
 INTRODUCTION
Static random access memory
(SRAM)
 Operates like a collection of latches.
 Once value is written, it is guaranteed to
remain in the memory as long as power is
applied.
 Used inside the processors (like the
Pentium).
 The size of an SRAM with m address lines
and n data lines is 2m words, or 2m × n
bits.
A SIX TRANSISTOR
SRAM CELL
 OPERATION OF SRAM
CELL
Each bit in an SRAM is stored on four
transistors that form two cross-coupled
inverters.

This storage cell has two stable states which

are used to denote 0 and 1.

Two additional access transistors serve to

control the access to a storage cell during
read and write operations. It thus typically
takes six MOSFETs to store one memory bit.
 Contd…..
These bit lines are used to transfer data for
both read and write operations.

Access to the cell is enabled by the word line

(WL in figure) which controls the two access
transistors M5 and M6 which, in turn, control
whether the cell should be connected to the bit
lines: BL and BL’

It's not strictly necessary to have two bit lines,

both the signal and its inverse are typically
provided since it improves noise margins.
 DIFFERENT STATES
OF SRAM
An SRAM CELL has three different
states:
STANDBY where the circuit is idle.
READING when the data has been
requested
WRITING when updating the
contents.
 STANDBY
If the word line is not asserted, the access
transistors M5 and M6 disconnect the cell
from the bit lines. The two cross coupled
inverters formed by M1 – M4 will continue
to strengthen each other as long as they
are connected to the supply.
 SRAM-READ
OPERATION
Assume a 1 is stored at Q.
Pre charge both bit lines to high.
The read cycle is started by asserting the
word line.
During the read operation the values
stored in Q and Qbar are transferred to
the bit lines.
So BL remains at its pre-charged value
and BL-bar discharges through M1-M5.
 Kn,M5 ( ( VDD-▲V- VTn ) VDSATn-
( VDSATn²/2 )
=Kn,M1(( VDD-VTn )▲V-(▲V²/2) )
▲V=VDSATn+CR(VDD-VTn√ VDSATn²
√(1+CR)+CR² (VDD-VTn) ² )
Where CR Cell ratio ≥1.2
 SRAM-WRITE
OPERATION
The start of a write cycle begins by
applying the value to be written to the bit
lines. If we wish to write a 0, we would
apply a 0 to the bit lines, i.e. setting BL-
bar to 1 and BL to 0.
This is similar to applying a reset pulse to
a SR-latch, which causes the flip flop to
change state (A 1 is written by inverting
the values of the bit lines)
WL is then asserted and the value that is
to be stored is latched in.
 Kn,M6 ( ( VDD- VTn ) VQ -(VQ²/2 )
=Kp,M4( ( VDD-|VTp| )VDSATp-
( VDSATp²/2) )
Solving,we get
VQ=VDD-VTn-(√ (VDD-VTn) ² -
2(up/un)PR( ( VDD- |VTp| ) VDSATp-
(VDSATp ² / 2) ) )
where PR Pull up Ratio =(W4/L4)/(W6/L6)
& PR ≤ 1.8
 ADVANTAGES &
DISADVANTAGES OF
S-RAM
Advantages:
Simplicity: SRAM’s don't require external refresh
circuitry or other work in order for them to keep
their data intact.

Speed:. The primary advantage of an SRAM

over a DRAM is its speed.
Disadvantages:
Cost: SRAM is, byte for byte, several times more
expensive than DRAM.

Size: SRAM’s take up much more space than

DRAM’s ( Since 32 MB of SRAM would be prohibitively
large and costly, DRAM is used for system memory )
 APPLICATIONS
It is used in the circuitry where either speed or low power, or both are of
prime interest.

SRAM is used as main memory in personal computers &also used in

workstations, routers and peripheral equipment.

Used in moderately clocked microprocessors, and have a nearly

negligible power consumption( in the region of a few microwatts.)

LCD screens and printers also normally employ SRAM to hold the image
displayed (or to be printed).

Small SRAM buffers are also found in CDROM and CDRW drives usually
256 KB or more are used to buffer track data, which is transferred in
blocks instead of as single values.

The so called "CMOS RAM" on PC motherboards was originally a battery-

powered SRAM chip, but is today more often implemented using
EEPROM or Flash.
READ
SPICE NET LIST
O/P WAVEFORMS
READ OPERATION:
WRITE OPERATION:
 CONCLUSION
Amplification is achieved here only by a single
stage.

Static power in the amplifier can be reduced by

pulsing the SE control signal for short periods.

An SRAM chip is comprised of thousands or millions

of identical cells, it is much easier to make than a
CPU, which is a large die with a non-repetitive
structure. This is one reason why RAM chips cost
much less than processors do .
 REFERENCES
1. INTRODUCTION TO CMOS VLSI
DESIGN BY DAVID HARRIS.

2. VLSI CIRCUITS EE 4321 BY PROF.

AZEEZ BHAVNAGARWALA.

3. DIGITAL INTEGRATED CIRCUITS BY

JAN RABAEY.
THANK YOU