PERIPHERAL INTERFACING UNIT III Mr. S.

VINOD LECTURER EEE DEPARTMENT

‡ Study of Architecture and programming of ICs: 8255 PPI, 8259 PIC, 8251 USART, 8279 Key board display controller and 8253 Timer/ Counter Interfacing with 8085 - A/D and D/A converter interfacing.

Block Diagram of 8255

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‡ Control word and status information are also transferred through this unit. Data bus buffer 2. Data is transmitted or received by the buffer on execution of input or output instruction by the CPU. . Port A. Group A and Group B controls 4. B and C Data bus buffer: ‡This is a tri state bidirectional buffer used to interface the 8255 to system data bus. Read Write control logic 3.It has a 40 pins of 4 groups. 1.

WR ) and also inputs from address bus and issues commands to individual group of control blocks ( Group A. Group B). d) RESET: A high on this pin clears the control register and all ports are set to the input mode e) A0 and A1 ( Address pins ): These pins in conjunction with RD and WR pins control the selection of one of the 3 ports. a) CS Chipselect : A low on this PIN enables the communication between CPU and 8255. . b) RD (Read) A low on this pin enables the CPU to read the data in the ports or the status word through data bus buffer. the CPU can write data on to the ports or on to the control register through the data bus buffer.It has the following pins. c) WR ( Write ) : A low on this pin.Read/Write control logic This unit accepts control signals ( RD.

PA and PCU ( PC7 PC4) Group B . .Group A and Group B controls These block receive control from the CPU and issues commands to their respective ports. ‡ Group A .PCL ( PC3 PC0) Control word register can only be written into no read operation of the CW register is allowed.

It can be programmed in 3 modes mode 0. it can be programmed in mode 0. mode 2. b) Port B: This has an 8 bit latched / buffered O/P and 8 bit input latch. It can be programmed in mode 0. mode1. .PORTS a) Port A: This has an 8 bit latched/buffered O/P and 8 bit input latch. c) Port C : This has an 8 bit latched input buffer and 8 bit out put latched/buffer. This port can be divided into two 4 bit ports and can be used as control signals for port A and port B. mode 1.

the 8255 ports work as programmable I/O ports. further there are three modes of operation of 8255. I/O mode and Bit Set-Reset mode (BSR). Under the I/O mode of operation. . so as to support different types of applications. mode 0. mode 1 and mode 2.Modes of Operation of 8255 ‡ These are two basic modes of operation of 8255. In I/O mode. while in BSR mode only port C (PC0-PC7) can be used to set or reset its individual port bits.

The bit to be set or reset is selected by bit select flags D3. D2 and D1 of the CWR as given in table. .‡ BSR Mode: In this mode any of the 8-bits of port C can be set or reset depending on D0 of the control word.

. This mode provides simple input and output capabilities using each of the three ports. Data can be simply read from and written to the input and output ports respectively. after appropriate initialization.Mode 0 I/O Modes : a) Mode 0 ( Basic I/O mode ): This mode is also called as basic input/output mode.

5 . 7 PC7 PC6 PC3 8255 PC2 PC1 PC0 PC4.Programming 8255 Mode 1: ² Ports A and B are programmed as input or output ports ² Port C is used for handshaking PA[7:0] STBA IBFA INTRA PB[7:0] STBB IBFB INTRB PA[7:0] OBFA ACKA INTRA PB[7:0] OBFB ACKB INTRB PC4 PC5 PC3 8255 PC2 PC1 PC0 PC6.

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Programming 8255 Mode 2: ² Port A is programmed to be bi-directional ² Port C is for handshaking ² Port B can be either input or output in mode 0 or mode 1 PC7 PC6 PC4 8255 PC5 PC3 PC0 PC0 PC0 PA[7:0] OBFA ACKA STBA IBFA INTRA PB[7:0] 11-15 .

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CONROL WORD .

example 1 -Keyboard 11-18 .

Bouncing Problem 11-19 .

Bouncing 11-20 .

example 2 stepper motor ‡ Unipolar full step Stepper motor: ‡ INPUT SEQUENCE: X Y X Y 1100 0110 0011 1001 ‡ 8255 CONTROL WORD: 1 0 0 0 0 0 0 0 =80H ‡ control register 0F ‡ PORT ADDRESS port A .0D port C .0E .0C port B .

START: MVI A. 09 OUT 0C JMP START MVI C. 03 OUT 0C CALL DELAY MVI A. FFH DCR C JNZ LOOP RET . 06 OUT 0C CALL DELAY MVI A. 80 DELAY: OUT 0F LOOP: MVI A. 0C OUT 0C CALL DELAY MVI A.

TRAFFIC LIGHT CONTROLLER ‡ Common Cathode: ‡ ‡ ‡ ‡ ‡ ‡ ‡ ‡ ‡ ‡ ‡ ‡ ‡ ‡ 1 ON 0 OFF uses 8255 . To make all ports as O/P ports: Control word 80H 8255 port addresses: If 8255 Chip is loaded in PCB left port: Port A 0CH Port B 0DH Port C 0EH Control register Address 0FH If 8255 Chip is loaded in PCB right port: Port A 14H Port B 15H Port C 16H Control register Address 17H .

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M OUT 0C INX H MOV A.S: L: MVI A. 80 OUT 0F MVI C.FF MVI E. 80 DATA . 80 OUT 0F MVI 01 OUT 0C 01. 4200 MOV A. FF DCR E JNZ S3 DCR D JNZ S2 DCR B JNZ S1 RET TEST PROGRAM MVI A. 05 MVI D . 08. 40. 04. M OUT 0E INX H DCR C JNZ L JMP S DELAY: S1: S2: S3: MVI B. 10.M OUT 0D INX H MOV A. 20. 02. 03 LXI H.

LOOP UP TABLE: Address 4200 4201 4202 4203 4204 4205 4206 4207 4208 Data .

8279 Programmable Keyboard/Display Interface .

‡ Scans and encodes up to a 64-key keyboard. ‡ The display is controlled from an internal 16x8 RAM that stores the coded display information. ‡ 8279 has 8 control words to be considered before It is programmed .‡ A programmable keyboard and display interfacing chip. ‡ Keyboard section has a built-in FIFO 8 character buffer. And Controls up to a 16 digit numerical display.

Max is 3 MHz. ‡ Chip select that enables programming. ‡ DB7-DB0: Consists of bi-directional pins that connect to data bus from 8085. Output that blanks the displays. ‡ CN/ST: Control/strobe. connected to the control key on the keyboard. reading the keyboard. etc. .I/O Interface Basic Description of the 8279 ‡ A0: Selects data (0) or control/status (1) for reads and writes between 8085 and 8279. ‡ CLK: Used internally for timing.

I/O Interface ‡ IRQ: Interrupt request. . reads data/status registers. ‡ : Connects to 8085 WR or RD signal. ‡ RESET: Connects to system RESET. ‡ RL7-RL0: Return lines are inputs used to sense key depression in the keyboard matrix. data is available. becomes 1 when a key is pressed. ‡ SL3-SL0: Scan line outputs scan both the keyboard and displays. ‡ OUT A3-A0/B3-B0: Outputs that sends data to the most significant/least significant of display. ‡Shift: Shift connects to Shift key on keyboard.

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8279 INTERNAL ARCTHITECTURE .

The pins A0. RD and WR select the command. Scan counter divide down the operating frequency of 8279 to derive scan keyboard and scan display frequencies. ‡ The I/O section is enabled only if CS is low. The data buffers interface the external bus of the system with internal bus of 8279. status or data read/write operations carried out by the CPU with 8279.Architecture and Signal Descriptions of 8279 ‡ I/O Control and Data Buffers : The I/O control section ‡ controls the flow of data to/from the 8279. The registers are written with A0=1 and WR=0. ‡ Control and Timing Register and Timing Control : ‡ These registers store the keyboard and display modes and other operating conditions programmed by CPU. . The Timing and control unit controls the basic timings for the operation of the circuit.

Architecture and Signal Descriptions of 8279 Scan Counter : ‡ The scan counter has two modes to scan the key matrix and refresh the display. the counter provides binary count that is to be externally decoded to provide the scan lines for keyboard and display (Four externally decoded scan lines may drive upto 16 displays). The keyboard and display both are in the same mode at a time.e. Return Buffers and Keyboard Debounce and Control: ‡ This section for a key closure row wise. After the debounce period. In the decode scan mode. if the key continues to be detected. In the encoded mode. the keyboard debounce unit debounces the key entry (i. The code of key is directly transferred to the sensor RAM along with SHIFT and CONTROL key status. wait for 10 ms). . the counter internally decodes the least significant 2 bits and provides a decoded 1 out of 4 scan on SL0-SL3(Four internally decoded scan lines may drive up to 4 displays). If a key closer is detected.

The contents of the registers are automatically updated by 8279 to accept the next data entry by CPU. the IRQ line goes high to interrupt the CPU. In scanned sensor matrix mode. till the RAM become empty. this unit acts as sensor RAM. . Display Address Registers and Display RAM : The ‡ display address register holds the address of the word currently being written or read by the CPU to or from the display RAM. this block acts as 8-byte first-in-first out (FIFO) RAM. Each row of the sensor RAM is loaded with the status of the corresponding row of sensors in the matrix. If a sensor changes its state. ‡ The status logic generates an interrupt after each FIFO read operation till the FIFO is empty. Each key code of the pressed key is entered in the order of the entry and in the mean time read by the CPU.Architecture and Signal Descriptions of 8279 FIFO/Sensor RAM and Status Logic: In keyboard or ‡ strobed input mode.

Modes of Operation of 8279 The modes of operation of 8279 are as follows ‡ 1. . With encoded scan 8*8 sensor matrix or with decoded scan 4*8 sensor matrix can be interfaced. These modes are as follows: 1. the data on return lines. Output (Display) modes. In encoded scan. a sensor array can be interfaced with 8279 using either encoded or decoded scans. Scanned Keyboard Mode : This mode allows a key matrix to be interfaced using either encoded or decoded scans. 2. The code of key pressed with SHIFT and CONTROL status is stored into the FIFO RAM. Input (Keyboard) modes. is stored in the FIFO byte by byte. an 8*8 keyboard or in decoded scan. Strobed input: In this mode. ‡ 2. 3. Scanned Sensor Matrix : In this mode. a 4*8 keyboard can be interfaced. Input ( Keyboard ) Modes : 8279 provides three input modes. The sensor codes are stored in the CPU addressable sensor RAM. if the control lines goes low.

a debounce logic comes into operation. i. A key code is entered to FIFO only once for each valid depression. the first will be ignored. it has at least one byte free. or released before it. the keycode is entered in FIFO. During the next two scans.e. If another key is found closed during the first key. naturally the key data will not be entered and the error flag is set. the above code is entered into it and the 8279 generates an interrupt on IRQ line to the CPU to inform about the previous key closures. . provided the FIFO is not full. that remains depressed is considered as single valid key depression. If the FIFO does not have any free byte. The last key. ‡ If FIFO has at least one byte free. ‡ The key code of the identified key is entered into the FIFO with SHIFT and CNTL status.(i)Scanned Keyboard mode with 2 Key Lockout : ‡ In this mode of operation. ‡ If two keys are pressed within a debounce cycle (simultaneously ). other keys are checked for closure and if no other key is pressed the first pressed key is identified. independent of other keys pressed along with it. no key is recognized till one of them remains closed and the other is released. when a key is pressed. ‡ If the first pressed key is released before the others.

All the keys are sensed in the order of their depression. . rather in the order the keyboard scan senses them.(ii)Scanned Keyboard with N-Key Rollover ‡ In this mode. ‡ In this mode. the code is entered in FIFO RAM. If it is still depressed. All the codes of such keys are entered into FIFO. the first pressed key need not be released before the second is pressed. the keyboard scan recorded them. When a key is pressed. each key depression is treated independently. ‡ Any number of keys can be pressed simultaneously and recognized in the order. and independent of the order of their release. the debounce circuit waits for 2 keyboards scans and then checks whether the key is still depressed.

otherwise. The error flag can be read by reading the FIFO status word.(iii). if any change in sensor value is detected at the end of a sensor matrix scan or the sensor RAM has a previous entry to be read by the CPU. ‡ The IRQ line goes high. . by issuing the end interrupt command. ‡ This flag. The error Flag is set by sending normal clear command with CF = 1. if AI = 0. this is considered a simultaneous depression and an error flagis set. This mode is programmed using end interrupt / error mode set command. AI is a bit in read sensor RAM word. The status of the sensor switch matrix is fed directly to sensor RAM matrix. (iv)Sensor Matrix Mode : ‡ In the sensor matrix mode. the debounce logic is inhibited. Scanned Keyboard Special Error Mode : ‡ This mode is valid only under the N-Key rollover mode. If during a single debounce period ( two keyboard scans ) two keys are found pressed . The 8-byte FIFO RAM now acts as 8 * 8 bit memory matrix. prevents further writing in FIFO but allows the generation of further interrupts to the CPU for FIFO read. if set. The IRQ line is reset by the first data read operation. Thus the sensor RAM bits contains the row wise and column wise status of the sensors in the sensor matrix.

1. 2. . These are discussed briefly. Display Entry : ( right entry or left entry mode ) 8279 allows options for data entry on the displays. The display data is entered for display either from the right side or from the left side.bit or single 8-bit display units.Output (Display) Modes : 8279 provides two output modes for selecting the display options. Display Scan : In this mode 8279 provides 8 or 16character multiplexed displays those can be organized as dual 4.

Programmable clock 4. Read Display RAM 6.Keyboard Display Mode Set 3. Write Display RAM 7.Command Words of 8279 ‡ All the command words or status words are written or read with A0 = 1 and CS = 0 to or from 8279. 1. End Interrupt / Error mode . Display Write Inhibit/Blanking 8. Clear Display RAM 2. This section describes the various command available in 8279. Read FIFO / Sensor RAM 5.

1.Keyboard Display Mode Set .

2.decided by the bits of an internal prescaler. ppppp should be set to 10100 to divide the clock by 20 to yield the proper 100 KHz operating frequency. The input frequency isdivided by a decimal constant ranging from 2 to 31. Programmable clock ‡ ‡ The clock for operation of 8279 is obtained by dividing the external clock input signal by a programmable constant called prescaler. If pin 3 of the 8279 is being clocked by a 2 MHz signal. . PPPPP. PPPPP is a 5-bit binary constant.

Read FIFO / Sensor RAM .3.

4. Read Display RAM .

5.Write Display RAM .

6. blank (BL) bits are available for each set as shown in format. Display Write Inhibit/Blanking ‡ The IW ( inhibit write flag ) bits are used to mask the individual set as shown in the below command word. those can be masked by setting the corresponding IW bit to 1. D2 corresponds to OUTB0 ± OUTB3 while D1 and D3 corresponds to OUTA0-OUTA3 for blanking and masking. The blank display bit flags (BL) are used for blanking A and B nibbles. ‡ Once a set is masked by setting the corresponding IW bit to 1. The output lines are divided into two set ( OUTA0 ± OUTA3 ) and ( OUTB0 ± OUTB3 ). Both BL bits will have to be cleared for blanking both the set. . ‡ If the user wants to clear the display. the entry to display RAM does not affect the set even though it may change the unmasked set. ‡ Here D0.

7.Clear Display RAM .

End Interrupt / Error mode .8.

Rolling Message In Seven Segment Display FORMAT FOR SEVEN SEGMENTS: d c B a dp e g f command word 1.Keyboard Display Mode Set 2. Write Display RAM 10h 90h Common anode: 0 ± ON 1 ± OFF .

M OUT 00 CALL DELAY INX H DCR D JNZ LOP 1 JMP START MVI B. 90H OUT 01 MOV A. FF DCR C JNZ LOP2 DCR B JNZ LOP3 RET Address 412C 412D 412F 4130 4131 4132 4133 4134 4135 4136 4137 4138 4139 413A 413B 413C Opcode FF FF FF FF FF FF FF FF 98 68 7A C8 FF FF FF FF Comment Blank Blank Blank Blank Blank Blank Blank Blank H E L P Blank Blank Blank Blank . 0FH MVI A. 412CH MVI D. A0 MVI C.START : LOP1: DELAY: LOP3: LOP2: LXI H. 10H OUT 01 MVI A.

FF MVI C. M OUT 00 INX H DCR D JNZ LOOP CALL DELAY JMP START MVI B. M OUT 00 INX H DCR D JNZ LOP CALL DELAY MVI D. 90H OUT 01 LOP: MOV A.Flashing Message In Seven Segment Display START : LXI H. 4300H MOV A. 10H OUT 01 MVI A. 06H MVI A. 4200H MVI D. LXI H. FF DCR C JNZ LOP2 DCR B JNZ LOP3 RET DELAY: LOP3: LOP2: . 06H LOOP.

Address 4200 4201 4202 4203 4204 4205 4300 4301 4302 4303 4304 4305 Opcode 98 68 7A C8 FF FF FF FF FF FF FF FF Comment H E L P Blank Blank Blank Blank Blank Blank Blank Blank .

lop for the pressing of key ANI 07 JZ LOP MVI A.M OUT DAT JMP LOP . 0FF . set to read FIFO OUT CNT IN DAT ANI 0F . A : code from look up table MVI H. 42 MOV A.clear the display BACK: OUT DAT DCR B JNZ BACK LOP: IN CNT . 40 . set mode and display MVI A.set clear display OUT CNT MVI A.ACCEPT A KEY AND DISPLAY MVI B. 00 OUT CNT . write display OUT CNT MVI A. 0CC. get the corresponding MOV L. 08 MVI A. 90 .

Address 4200 4204 4208 420C Opcode OC 99 08 6C 9F 29 09 1A 4A 28 88 68 0B 8F 38 E8 ‡ CNT C2 ‡ DAT C0 01 00 .

8259 Programmable Interrupt Controller .

determine which of the incoming requests is of the highest importance ‡ Special features of 8259: ‡ ‡ ‡ ‡ Eight level priority controller Expandable to 64 levels Programmable interrupt modes Individual request mash capability . ‡ It accepts request from the peripheral equipment.8259 Programmable Interrupt Controller ‡ The 8259 programmable interrupt controller (PIC) adds eight vectored priority encoded interrupts to the microprocessor.

It has several modes. uses NMOS technology and requires a single a5V supply.It is packaged in a 28-pin DIP. The 8259A is designed to minimize the software and real time overhead in handling multi-level priority interrupts. requiring no clock input. Circuitry is static. permitting optimization for a variety of system requirements .

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The highest priority is selected and stroed into the corresponding bit of the ISR during INTA pulse. Masking of a higher priority input will not affect the interrupt request lines of lower quality. The IRR is used to store all the interrupt levels which are requesting service. PRIORITY RESOLVER This logic block determines the priorities of the bits set in the IRR. INTERRUPT MASK REGISTER (IMR The IMR stores the bits which mask the interrupt lines to be masked. The V level on this line is designed to be fully compatible with the 8080A. . the Interrupt Request Register (IRR) and the In-Service (ISR). The IMR operates on the IRR.INTERRUPT REQUEST REGISTER (IRR) AND IN-SERVICE REGISTER (ISR) The interrupts at the IR input lines are handled by two registers in cascade. and the ISR is used to store all the interrupt levels which are being serviced. INT (INTERRUPT) This output goes directly to the CPU interrupt input. 8085A and 8086 input levels.

the Interrupt Mask Register (IMR). READ/WRITE CONTROL LOGIC The function of this block is to accept Output commands from the CPU. In Service Register (ISR). . This line can be tied directly to one of the address lines . or the Interrupt level onto the Data Bus. bidirectional 8-bit buffer is used to interface the 8259A to the system Data Bus. RD (READ) A LOW on this input enables the 8259A to send the status of the Interrupt Request Register (IRR).INTA (INTERRUPT ACKNOWLEDGE) INTA pulses will cause the 8259A to release vectoring information onto the data bus. It contains the Initialization Command Word (ICW) registers and Operation Command Word (OCW) registers which store the various control formats for device operation. No reading or writing of the chip will occur unless the device is selected. as well as reading the various status registers of the chip. CS (CHIP SELECT) A LOW on this input enables the 8259A. The format of this data depends on the system mode (mPM) of the 8259A. This function block also allows the status of the 8259A to be transferred onto the Data Bus. Control words and status information are transferred through the Data Bus Buffer. A0 This input signal is used in conjunction with WR and RD signals to write commands into the various command registers. DATA BUS BUFFER This 3-state. WR (WRITE) A LOW on this input enables the CPU to write control words (ICWs and OCWs) to the 8259A.

the ISR bit remains set until an appropriate EOI command is issued at the end of the interrupt sequence. The 8259A will also release a CALL instruction code (11001101) onto the 8-bitData Bus through its D7±0 pins. This CALL instruction will initiate two more INTA pulses to be sent to the 8259A from the CPU group. the highest priority ISR bit is set. and sends an INT to the CPU. and the corresponding IRR bit is reset. setting the corresponding IRR bit(s). if appropriate. In the AEOI mode the ISR bit is reset at the end of the third INTA pulse. 2. This completes the 3-byte CALL instruction released by the 8259A.INTERRUPT SEQUENCE The events occur as follows in an MCS-80/85 system: 1. Upon receiving an INTA from the CPU group. One or more of the INTERRUPT REQUEST lines (IR7±0) are raised high. The CPU acknowledges the INT and responds with an INTA pulse. . The 8259A evaluates these requests. 5. Otherwise. These two INTA pulses allow the 8259A to release its preprogrammed subroutine address onto the Data Bus. 3. 7. 6. 4. The lower 8-bit address is released at the first INTA pulse and the higher 8-bitaddress is released at the second INTA pulse.

Special mask mode d. Rotating priority mode c. Initialization Command Words (ICWs): Before normal operation can begin. each 8259A in the system must be brought to a starting point -by WR pulses. These modes are: a.PROGRAMMING THE 8259A The 8259A accepts two types of command words generated by the CPU: 1. . Operation Command Words (OCWs): These are the command words which command the 8259A to operate in various interrupt modes. Polled mode The OCWs can be written into the 8259A anytime after initialization. 2. Fully nested mode b.

Initialization Sequence .

INITIALISATION COMMAND WORDS ICW1 .

respectively. When the routine interval is 4. When the routine interval is 8. ‡ SNGL: Single. The address format is 2 bytes long (A0±A15).‡ A5±A15: Page starting address of service routines . then the 8259A will operate in the level interrupt mode. . These can be programmed to be spaced at intervals of 4 or 8 memory locations. ADI = 1 then interval = 4. Edge detect logic on the interrupt inputs will be disabled. while A6±A15 are programmed externally. ‡ ADI: CALL address interval. A0±A5 are automatically inserted by the 8259A. IfICW4 is not needed. while A5±A15 are programmed externally. A0±A4 are automatically inserted by the 8259A. Means that this is the only 8259A in the system.In an MCS 80/85 system. the 8 request levels will generate CALLs to 8 locations equally spaced in memory. ‡ T: If LTIM e 1. set IC4 = 0. If SNGL = 1 no ICW3 will be issued. ADI e 0 then interval e 8. thus the 8 routines will occupy a page of 32 or 64 bytes. ‡ IC4: If this bit is setÐICW4 has to be read.

ICW 2 .

ICW 3
This word is read only when there is more than one 8259A in the system and cascading is used, in which case SNGL e 0. It will load the 8-bit slave register. The functions of this register are: ‡ a. In the master mode (either when SP = 1, or in buffered mode when M/S = 1 in ICW4) a ``1'' is set for each slave in the system. The master then will release byte 1 of the call sequence (for MCS- 80/85 system) and will enable the corresponding slave to release bytes 2 and 3 (for 8086 only byte 2) through the cascade lines. ‡ b. In the slave mode (either when SP e 0, or if BUF e 1 and M/S e 0 in ICW4) bits 2±0 identify the slave. The slave compares its cascade input with these bits and, if they are equal, bytes 2 and 3 of the call sequence (or just byte 2 for 8086) are released by it on the Data Bus. d only when there is more than one 8259A in the system and cascading is used, in which

If BUF=0,M/S is to be neglected.

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Programmable Interval Timer 8253 .

It uses N-MOS technology with a single +5V supply and is packaged in a 24-pin plastic DIP.6 megahertz. It is organized as 3 independent 16-bit counters. each with a counter rate up to 2 MHz .‡ ‡ ‡ ‡ ‡ The Intel 8253 is a programmable counter / timer chip designed for use as an Intel microcomputer peripheral. depending on the programmed mode of the counter. Actual operation of the out line depends on how the device has been programmed. or it can act as a start pulse. All modes of operation are software programmable. Clock This is the clock input for the counter. The maximum clock frequency is 1 / 380 nanoseconds or 2. The counter is 16 bits. . Gate This input can act as a gate for the clock input line. Out This single output line is the signal that is the final programmed output of the device. The minimum clock frequency is DC or static operation.

Block diagram of 8253 .

the RD. The control word register and counters are selected according to the signals on lines A0 and A1. In the peripheral I/O mode. 2. 1. The Data bus buffer has three basic functions. Loading the count registers. bi-directional. Reading the count values.Data Bus Buffer : ‡ This tri-state. WR. In memory-mapped I/O. CS and the ‡ address lines A0 and A1. and WR signals are connected to IOR and IOW. 8-bit buffer is used to interface the 8253/54 to the system data bus. Address lines A0 and A1 of the CPU are usually connected to lines A0 and A1 of the 8253/54. Programming the modes of 8253/54. and CS is tied to a decoded address. . 3. Read/Write Logic : The Read/Write logic has five signals : RD. respectively. these are connected to MEMR and MEMW.

. Counters : These three functional blocks are identical in operation.Control Word Register : This register is accessed when lines A0 and A1 are at logic 1. 16 bit. its mode. The programmer can read the contents of any of the three counters without disturbing the actual count in process. down counter. It is used to write a command word which specifies the counter to be used (binary or BCD). Each counter ‡ consists of a single. and either a read or write operation. pre-settable. The counter can operate in either binary or BCD and its input. The counters are fully independent. gate and output are configured by the selection of modes stored in the control word register.

.A1 = 11).Programming the 8253/54 : ‡ Each counter of the 8253/54 is individually programmed by writing a control word into the control word register (A0 .

Write a control word into control register. The first I/O operation reads the low-order byte. 2. and two I/O read operations are performed by the CPU. and the second I/O operation reads the high order byte. 2. . and two I/O read operations are performed by the CPU. Counter Latch Command : In the second method. 3. Load the low-order byte of a count in the counter register. The first I/O operation reads the low-order byte. Load the high-order byte of count in the counter register. and the second I/O operation reads the high order byte. Simple Read : It involves reading a count after inhibiting the counter by controlling the gate input or the clock input of the selected counter. it is necessary to read the value of the count in process. especially in event counters.WRITE Operation : 1. an appropriate control word is written into the control register to latch a count in the output latch. READ Operation : In some applications. This can be done by two possible methods: 1.

.MODES OF 8253 ‡ ‡ ‡ ‡ ‡ ‡ Mode 0 : Interrupt on terminal count MODE 1 : Hardware Retrigger able One-shot MODE 2 : Rate generator MODE 3 : Square Wave Rate Generator MODE 4 : Software Triggered Strobe. MODE 5 : Hardware triggered strobe (Retrigger able).

‡ 1)Gate = 1 enables counting. .Mode 0 : Interrupt on terminal count ‡ 1) The output will be initially low after the mode set operation. ‡ 3) When the terminal count is reached the output will go high and remain high until the selected count is reloaded. ‡ 2) Gate = 0 disables counting. ‡ 2) After the count is loaded into the selected count Register the output will remain low and the counter will count.

Let us set channel 0 in mode 0 START: MVI A. 00 OUT 0C8H HLT Observe. using an CRO that the output of channel 0 is initially low. 30 OUT 0CEH MVI A. 05 OUT 0C8H MVI A. After giving six clock pulse the output goes high .

3) The output will go high on the terminal count and remain high until the next rising edge at the gate input. If retriggered. the counter is loaded with the new count and the one-shot pulse continues until the new count expires. the current one shot is not affected unless the counter is retriggered.MODE 1 : Hardware Retrigger able One-shot a) Normal operation 1) The output will be initially high 2) The output will go low on the CLK pulse following the rising edge at the gate input. c) New count If the counter is loaded during one shot pulse. b) Retriggering The one shot is retrigger able. hence the output will remain low for the full count after any rising edge of the gate input. .

05 OUT 0C8H MVI A.triggers gate 0 .START: MVI A. 32 OUT 0CEH MVI A. 00 OUT 0C8H OUT 0D0H HLT .

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. the counter reloads the initial count and the process is repeated. 4) The period from one output pulse to the next equals the number of input counts in the count register. the new count will be loaded with the new count on the next CLK pulse and counting will continue from the new count. the new count will be loaded at the end of the current counting cycle. output is set immediately high.MODE 2 : Rate generator This mode functions like a divide by-N counter. 2) The output will go low for one clock pulse before the terminal count. Otherwise. 2) If Gate goes low during an low output pulse. If a trigger is received after writing a new count but before the end of the current period. 3) The output then goes high. A trigger reloads the count and the normal sequence is repeated. c) New count The current counting sequence does not affect when the new count is written. b) Gate Disable 1) If Gate = 1 it enables a counting otherwise it disables counting (Gate = 0 ). a) Normal Operation 1) The output will be initially high.

74 OUT 0CEH MVI A.channel 1 in mode 2 . 0AH OUT 0CAH MVI A.Using mode 2. 00H OUT 0CAH HLT .LSB of count .MSB of count . divide the clock preset at channel 1 by 10 START: MVI A.

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In this way. Subsequent clock pulses decrement the clock by 2. if the count is odd. the output goes low and the full count is reloaded. the counter is loaded with the initial count on the next clock pulse and the sequence is repeated.Mode 3 Square Wave Rate Generator a)Normal operation 1) Initially output is high. After timeout. otherwise. If Gate goes low while output is low. . 2) For even count. counter is decremented by 2 on the falling edge of each clock pulse. When Gate goes high. After this. the output will be high for (n+1)/2 counts and low for (n-1)/2 counts. b) Gate Disable If Gate is 1 counting is enabled otherwise it is disabled. 3) If the count is odd and the output is high the first clock pulse (after the count is loaded) decrements the count by 1. the counter will be loaded with the new count on the next CLK pulse and counting will continue from the new count. c) New Count The current counting sequence does not affect when the new count is written. the state of the output is changed and the counter is reloaded with the full count and the whole process is repeated. output is set high immediately. the new count will be loaded at end of the current half-cycle. When the counter reaches terminal count. If a trigger is received after writing a new count but before the end of the current half-cycle of the square wave. Then the whole process is repeated. The first clock pulse (following the reload) decrements the count by 3 and subsequent clock pulse decrement the count by two.

5 MHZ.6 micro sec . which corresponds to 0. Here the maximum count is FFFF. 36 OUT 0CEH MVI A. 00 OUT 0C8H HLT Vary the frequency by varying the count . 0A OUT 0C8H MVI A. Thus with the clock frequency of 1.To generate a square wave of frequency 150 KHz at channel START: MVI A.

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3) And become high again b) Gate Disable ‡ If Gate is one the counting is enabled otherwise it is disabled. 2) Writing the second byte allows the new count to be loaded on the next CLK pulse. If the count is two byte then 1) Writing the first byte has no effect on counting. it will be loaded on the next CLK pulse and counting will continue from the new count. c) New count ‡ If a new count is written during counting. The Gate has no effect on the output.MODE 4 : Software Triggered Strobe a) Normal operation 1) The output will be initially high 2) The output will go low for one CLK pulse after the terminal count (TC). .

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‡ 3) The output will go low for one CLK pulse after the terminal count (TC). ‡ 2) The counting is triggered by the rising edge of the Gate. b) Retriggering If the triggering occurs on the Gate input during the counting. the counter will be loaded with the new count on the next CLK pulse and counting will continue from there. ‡ c) New count ‡ If a new count is written during counting. If the trigger occurs after the new count is written but before the terminal count. . the current counting sequence will not be affected. the initial count is loaded on the next CLK pulse and the counting will be continued until the terminal count is reached.MODE 5 : Hardware triggered strobe Retriggerable a) Normal operation ‡ 1) The output will be initially high.

ADC
‡ ADC0808/ADC0809 8-Bit P Compatible A/D Converters with 8-Channel Multiplexer ‡ The 8-bit A/D converter uses successive approximation as the conversion technique. ‡ The 8-channel multiplexer can directly access any of 8-singleended analog signals. ‡ Key Specifications: Resolution 8 Bits Single Supply 5 VDC Low Power 15 mW Conversion Time 100 s

successive approximation

This code is fed into the DAC which then supplies the analog equivalent of this digital code (Vref/2) into the comparator circuit for comparison with the sampled input voltage. Then the next bit is set to 1 and do the same test. otherwise. ± A successive approximation register block designed to supply an approximate digital code of Vin to the internal DAC. The successive approximation register is initialized so that the (MSB) is equal to a digital 1.The successive approximation circuit typically consists of four block: ± A sample and hold circuit to acquire the input voltage (Vin). ± An internal reference DAC that supplies the comparator with an analog voltage equivalent of the digital code output of the SAR for comparison with Vin. the bit is left a 1. continuing this binary search until every bit in the SAR has been tested. ± An analog voltage comparator that compares Vin to the output of the internal DAC and outputs the result of the comparison to the successive approximation register (SAR). . If this analog voltage exceeds Vin the comparator causes the SAR to reset this bit. The resulting code is the digital approximation of the sampled input voltage and is finally output by the DAC at the end of the conversion (EOC).

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CHANNEL 0 .END OF CONVERSION . CONTROL WORD . 01 XRA A XRA A XRA A XRA A MVI A.START PULSE LOOP: .STOP PULSE . 18H OUT CE MVI A.Program for analog to digital conversion MVI A. 10H OUT CE MVI A. 00 IN D8 ANI 01 CPI 01 JNZ LOOP INC0 STA 4200 HLT .

00 OUT C0H CALL DELAY MVI A. 0FFH DCR C JNZ L2 DCR B JNZ L1 RET . port address DAC CALL DELAY JMP START DELAY: L1: L2: MVI B.Program for digital to analog conversion square wave START: MVI A. 05 MVI C. FF OUT COH .

port address of DAC INR A JNZ L1 .Program for digital to analog conversion Saw tooth wave form START: L1: MVI A. 00 OUT 0C0H .

L OUT C0H INR L JNZ L1 MVI L. 00H MOV A. 0FFH MOV A. L OUT C0 DCR L JNZ L2 JMP START L2: .Program for digital to analog conversion Triangular waveform START: L1: MVI L.

Universal Asynchronous Receiver Transmitter (UART .8251) .

formatting.Synchronous vs. There are two categories depending on the clocking of the data on the serial link: Synchronous protocols--each successive datum in a stream of data is governed by a master clock and appears at a specific interval in time. ‡ There are special IC chips made for serial data communications. Asynchronous A communication protocol is a convention for data transmission that include such functions as timing. with no specific clock control governing the relative delays between data. control. These chip is called UART (universal asynchronous receiver transmitter) and USART (universal synchronous-asynchronous receiver-transmitter) 8251. . ‡ Asynchronous protocols--successive data appear in the data stream at arbitrary times. and data presentation.

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Transfer Types .

g. computer. modem ‡ RS-232C A widely accepted interface standard originally developed to foster data communication on public telephone network through a modem This has been adapted to the communication of terminals (PCs) directly to computers.g.‡ ‡ DTE ± ± DCE ± ± ± data terminal equipment e. terminal data communication equipment connects DTE to communication lines e. .

DTE Connections .

25-Pin RS232 Connector .

9-Pin RS232 Connector

TTL to RS-232

RS-232 Frame Format
Example

Start bit

0 b0 b1

« ASCII

bn p s1 s 2
Parity Stop bit

111101000001111
Idle

A

8251 Block Diagram .

‡ The UART is a universal asynchronous receiver/transmitter. which is modeled on the real-world Intel® 8251 peripheral interface adapter component. the UART consists of three main blocks. In the model we are considering. a serial transmit block a serial receive block and a CPU Interface (I/F) block. .

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Mode Instruction (Asynchronous) .

Mode Instruction (Synchronous) .

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Command Register .

Status Register .

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