Architectural Considerations

A Review of Some Architectural Concepts

Organization of the Computing System
Input/ Output Memory

System Interconnection

Processor

The Computing System ± Top Level Structure

the memory and the I/O subsystems. ‡ Input/Output Sub-System ± Moves information between the computing system and its external environment. ‡ System Interconnection ± Some mechanism that provides for communication among the processor. . ‡ Memory Sub-System ± Stores data and programs.Organization of the Computing System ‡ Processor ± Controls the operation of the computing system and performs its data processing functions.

The Processor Registers Arithmetic and Logic Unit Internal Interconnection Control Unit The Processor .

and registers. .The Processor ‡ Control Unit ± Controls the operation of the processor. ALU. ‡ Arithmetic and Logic Unit (ALU) ± Performs the system¶s data processing functions ‡ Registers ± Internal storage for the processor ‡ Internal Interconnection ± A mechanism that provides communication among the control unit.

The Registers ‡ A number of registers exit within the processor and are intended for the temporary storage of information needed frequently and urgently. ± Stack Pointer. . ‡ Can only be used for specific functions. ‡ Can be classified into: ± General Purpose Registers. ‡ Can be used as the programmer requires. ± Pointers. ± Special Purpose Registers. ± Accumulator.

‡ Bring the next instruction from memory into the processor.The Operation of the Processor ‡ Processors mainly operate based on a 3state cycle: ± Fetch. ‡ Determine what is required. ± Execute. ± Decode. ‡ Do it. 0124828147 :) .

‡ The contents of the IR are decoded to tell the processor what operation to perform and what the operands for the operation are. it is read ± in the form of a group of bits known as an opcode ± using the processor¶s data bus into yet another special register ± the Instruction Register (IR). ‡ The processor uses its internal register and the ALU to perform the required operation. ‡ During the fetch cycle. ‡ When the instruction is ready. .Details of the 3-State Cycle ‡ A special register in the processor ± known as the program counter (PC) ± always holds the address of the next instruction for execution. the contents of the PC are copied to another special register ± Memory Address Register (MAR) ± which is connected to the address bus output of the processor.

‡ The flags register together with the AC are collectively known as the Program Status Word ± PSW. ‡ Overflow occurs when an arithmetic operation on signed numbers produces a wrong result because the result has more bits than can be held by the registers. . carry.The ALU ‡ The ALU is made up of several functional blocks that perform different arithmetic and logical operations on the operands. ‡ The ALU operations may generate certain conditions that are saved in the flags register. zero and overflow. ± Some typical flags are: sign.

‡ Maximum number of bits that can be accessed at once. ‡ How permanent is permanent? ‡ Memory is measured by two numbers: ± The address space. ± Could be temporary or permanent. ‡ How many different locations there are. . ± Both of these values may have different meanings depending on whether one is looking from the point of view of the processor or the memory. ± The access width.Memory Sub-System ‡ Memory in a computing system is used for the storage of programs and data.

. ± However. ‡ It is up to the programmer to keep the program(s) and data separate.Memory Sub-System ‡ Data and programs cannot co-exist. ± Most computing systems treat memory as one continuous address space. some systems have physically separate program and data storage with separate address spaces.

± Cost ‡ As a rule of thumb. the more expensive it would be. ‡ Types: ± RAM ± Random Access Memory ‡ Dynamic ± DRAM ‡ Static ± SRAM ± ROM ± Read Only Memory ‡ Erasable ± EPROM ‡ Electrically Erasable ± EEPROM .Memory ‡ Many different types that vary in ± Access speed. ± Erasability. the more useful the memory technology is. ± Volatility.

. ± Can be made non-volatile by using a battery for backup power.Memory ± RAM ‡ The proper name is Read/Write Memory. ‡ Allows both read and write operations. ± Both operations are performed electrically. ± But no one will understand what you are talking about. ± Used for temporary storage only. ‡ Volatile. the contents become invalid. ± If the power is disconnected.

‡ Refreshing is done by reading and re-writing each word every few milliseconds. ± Therefore. ‡ Charge on a capacitor decays naturally. DRAM needs refreshing even when powered to maintain the data. .Memory ± RAM ± DRAM ‡ Uses only one transistor per bit. ± Data is stored as charge in capacitors.

± Faster. . ± More complex construction. ‡ No refreshing is needed. ± No charges to leak. ± More expensive. ‡ Larger cell. Less dense.Memory ± RAM ± SRAM ‡ Consists of internal flip flop like structures that store the binary information.

‡ Non volatile. . ‡ Manufactured with the data wired into the chip. ± No room for mistakes. ‡ Not very effective for end-users.Memory ± ROM ‡ Read but cannot write.

± Erasing can be repeated a relatively large but limited number of times (~100.Memory ± EPROM ‡ Uses MOS transistors with insulating material that changes behavior when exposed to ultraviolet light. ‡ Non volatile. ‡ More expensive than PROM. ± Before writing. ± Erasing time ~20 minutes. ‡ Electrically read and written. . ALL cells must be erased by exposure to ultraviolet light.000 times). ± Programmed electrically and erased optically.

‡ Non volatile. ± Write takes a relatively long time (~100Qsec/byte).000 times. ± Can be erased only about 10. except that the insulating material is much thinner. ‡ Updatable in place. ‡ More expensive and less dense than EPROM. ‡ Can be written to any time without erasing the previous contents. ± Only the bytes addressed are modified. . ± Its operation can be inverted using voltage.Memory ± EEPROM ‡ Uses the same floating-gate transistors.

± In other words. .Memory ± The Stack ‡ The stack is an area of memory identified by the programmer for temporary storage of information. ‡ The stack is a LIFO structure. the programmer defines the bottom of the stack and the stack grows up into reducing address range. ± Last In First Out. ‡ The stack normally grows backwards into memory.

then the information is copied from the location pointed to by the SP. ± There must be a pop for every push. ‡ The information is copied to the location pointed to by the SP. ± Information is retrieved from the stack using a ³pop´ operation. ± This pointer is used to constantly point to the ³top of the stack. .Memory ± The Stack ‡ Processors usually contain a special register known as the Stack Pointer (SP). then the SP is decremented. ‡ The SP is incremented.´ ± Information is saved on the stack using a ³push´ operation.

‡ How soon after the previous access can the memory be accessed again. ‡ How long it takes from the time the address is ready until the data becomes ready. .Memory ± Speed ‡ The speed of memory is measured by two numbers: ± Access Time. ± Cycle Time.

‡ Can be classified into: ± Serial ‡ Single wire with the data being transferred sequentially. ± Parallel ‡ Multiple wires with the data being transferred concurrently. memory and one or more peripherals. ‡ Several possible implementation techniques: ± Programmed ± Interrupt driven .The I/O Sub-System ‡ Interface between the processor.

± Memory-mapped .Programmed I/O ‡ Processor has direct control over I/O ± Sensing status ± Read/write commands ± Transferring data ‡ CPU waits for I/O module to complete operation ‡ Wastes CPU time ‡ Two types: ± I/O port-based.

‡ Each port is identified by a unique port number. ± Physically. . ± The hardware uses the port number to activate (enable) the proper port. ± It produces the port number on its address bus output when it is attempting to access the port.I/O port-based I/O ‡ I/O ports are connections consisting of groups of parallel bits connecting into and out of the computing system. ± The processor uses special instructions to access these ports. the ports are made of either tri-state buffers for input or latches for output.

± I/O devices and memory locations cannot have the same address. ‡ Therefore. we lose memory area when we use memory-mapped I/O. .Memory-mapped I/O ‡ Some systems allow ³memory-mapped´ I/O where the I/O devices are treated like memory locations. ± The processor would use memory access instructions to access these devices.

‡ An interrupt is defined as ³an event requiring immediate attention.´ ± Extremely important in real-time environments.Interrupt-driven I/O ‡ Instead of having the processor waste time constantly checking on the I/O devices. ‡ When the processor is interrupted. . ± The ISR is written to handle the specific event that occurred. ± An ISR may interrogate an I/O device to determine the required activity and perform it. we can have the devices ³interrupt´ the processor when they need attention. it branches to a special routine known as an ³interrupt service routine´ (ISR).

Measuring the Speed of a Processor ‡ The proper way to measure the speed of a processor is not by counting Hz. ‡ What¶s the proper way? ± One aspect of the speed of a processor is ³throughput´. ± The match between the processor and its bus and memory can affect the apparent overall speed of the system.´ . ± The best method for comparing processor is to compare their performance on standardized applications known as ³benchmarks. ± Another aspect is how well does the processor¶s instruction set support the expected usage of the processor. Which is defined as the number of instructions executed per second.

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