Testing in its broadest sense means to examine a product

and to ensure that it functions and exhibits the properties and capabilities that it was designed to possess.  Main purpose of testing is to detect malfunctions in the product hardware and to locate their causes so that they may be eliminated. Testing terms: OtbT : object to be tested DUT : device under test CUT : circuit under test Ls : Latches CN : Combinational Networks

These rely primarily on mechanical means and not on use of additional circuits in an otbT for the purpose of facilitating its testing. Examples include use of extra I/O for additional test points, improvement of test features. Characteristics:  They are used for testing system parts only outside the system.  They rely on feeding signals directly through the test interface during listing.  They rely on the use of tester-driven timing.

 High costs for test equipment . Uncertainties in output sensing.  Large volume of data to be processed. Uncertainties in input feeding.DIFFICULTIES IN TESTING Shortage of I/O points. Noise disturbances.      . Signal distortions in interface connections.test generation and execution.)  Difficulty in synchronizing test objects timing with tester timing. (Rejection of good parts reduces apparent yield.

it will. Murphy¶s Law .FAULTS If anything can go wrong.

0 or X) which differs from that expected that is violates the original circuit equation. Fault Types:  SAO : Stuck at µ0¶ (short with ground rail)  SA1 : Stuck at µ1¶ (short with Vdd) . A fault is defined to have occurred when a circuit variable assumes a value(1.FAULT DEFINITION In any circuit composed of logic gates. there is the possibility of the occurrence of a fault.

 Process variation and abnormalities.  Photolithographic defects.FAULT TYPES AND MODELS Examples of physical defects include  Defects in silicon substrate. . opens. transistor stuck-on or stuck-off. Excessive change in threshold voltage and excessive change in steady state currents. Resistive shorts and opens.  Oxide defects. Electrical faults caused: Shorts.  Mask contamination and scratches.

KINDS OF FAULTS  Single faults  Multiple faults. .

X4 .X2+X3.CIRCUIT FOR AO1 EQUATIONS: X7=X6+X5 X5=X1.X4 X7=X1.X2 X6=X3.

A test for SA0 at x1 also covers SA0 at x5 and x7. : 2 * 2 * 7C2 = 84 Fault combinations are not unique.KINDS OF FAULTS  Single faults  Multiple faults. . No of single fault locations : 7 No of single faults : 2 * 7 = 14 No of double fault combs.

 All inputs to an AND gate at SA1 is equivalent to an AND gate whose output is at SA1.  One or more inputs to an AND gate at SA0 is equivalent to an AND gate whose output is at SA0. Thus any gate output fault has an equivalent single stuck fault or multiple stuck fault.  All inputs to an OR gate at SA0 is equivalent to an OR gate whose output is at SA0. .FAULT EQUIVALENCES  One or more inputs to an OR gate at SA1 is equivalent to an OR gate whose output is at SA1.

g) is not detected by any test in Tg. .MASKING OF FAULTS Definition: Let Tg be a test that detects a fault g. We can say that a fault f functionally masks the fault g iff the multiple faults (f.

 SSFs can be used to model other type of faults.SINGLE STUCK FAULT MODEL Single stuck-fault model (SSF) is the classical or standard fault model. the number of SSFs in a circuit is small.  it is independent of technology.  compared to other fault models. Its usefulness results from the following attributes:  it presents many different physical faults. .

B.AND-NAND BLOCK X=AND(A.D) A A B B C C D D sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 A 1 0 1 1 1 1 1 1 B 1 1 1 0 1 1 1 1 C 1 1 1 1 1 0 1 1 D 1 1 1 1 1 1 1 0 X 1 0 1 0 1 0 1 0 Y 0 1 0 1 0 1 0 1 .D) Y=NAND(A.C.B.C.

SA1) 3N combinations are possible.The test sequence can thus be obtained by finding out the combinations. For N=100 we get 5. .1047 combinations which is a very large data to process. For a single stack model containing N nodes.SA0. Complementary circuits can be tested in the similar fashion. where in each node can be in one of the 3 states (good.

EXISTENCE FUNCTION Developing a test sequence: x6=x3.x2 x7=x5+x6 Rules for labeling the nodes:  Primary inputs are labeled with the lowest indexed variables.x4 x5=x1.  Fan outs are labeled separately. .

X4 X7=X1.X4 .CIRCUIT FOR AO1 EQUATIONS: X7=X6+X5 X5=X1.X2+X3.X2 X6=X3.

x4 x6 x5+x6 x7 DF. F G x1.G : x5¶x1x2 x6¶x3x4 x7¶x5 x7¶x6 G.F = 0 where F is the set of inputs and G is the set of outputs.xp) F=G DF.x1«.F : x5x1¶ x6x3¶ x5x2¶ x6x4¶ x7x6¶x5¶ .EQUATIONS Fi(x0.x2 x5 x3.xp)=Gi(xo.x1«.G +DG.

Instead of 7 variable K map use a Marquand chart. These are the ones in the existence function circuit. After cancellation. . take the remaining points.EXISTENCE FUNCTION GENERATOR Mark all the points which are covered by at least one of the terms. Move from one point to a place where there is a change in output. ( No of ones = 16).

Each of the input variables is tested independently for a change in value from 0 to 1 and again from 1 to 0. Each of the intermediate variable is also tested in the process. The complete test sequence is 5-7-6-14-10-11-9-13-5. . Each output variable is thereby tested for its ability to change value from a 1 to 0 and from a 0 to 1.Longest chain will produce the desired test sequence.

The test sequence covers all detectable single faults.ADVANTAGES OF TEST SEQUENCES  Test sequence can be produced by a hardware unit     instead of the usual software unit. Since at least one of the outputs change on the application of an input. Continuous resetting between tests is not necessary. This helps in reducing resetting. . The test sequence is closed i. detection of a failure is logically straightforward.e it returns to the initial state.

Bridging circuits. Faults in CMOS circuits. Multiple faults simultaneously presented in the system.DRAWBACKS OF SINGLE STACK FAULT MODEL Does not take into account other kinds of faults such as AC-faults.     .

DESIGN FOR TESTABILITY Testable means capable of being ascertained as being fault free or not. The aim of testability is to make the parts testable not only on test fixtures separately from the system but also within the system when the parts are connected.e the capability of locating faults at least down to the smallest repair-replaceable unit . It should also include diagnosability i.

THREE KEY FUNCTIONS  Control Setting the conditions for the tests so that stimuli can be supplied to the object to be tested.  Observation Obtaining the response to the stimuli so that the behavior can be evaluated.  Isolation Making the control and observation possible and more reliable. .

 Built in Self Testing. (BIST) .TECHNIQUES  Ad-hoc Testable Design Techniques  Initialize sequential circuit  Avoid redundancy logic  Avoid asynchronous logic  Avoid redundant circuits.

But if we have sub-circuits .  Use of switches Ex: For a 32 bit counter checking is very difficult. .testing will be easier. Switches will be placed throughout.AD-HOC DESIGN The three main features are  Partition and Multiplexer techniques.


Components:  Pseudo Random Pattern Generator (PRPG)  Output Random Analyzer (ORA) .BUILT IN SELF TECHNIQUES In built-in-self-techniques (BIST) parts of the circuits are used to test the circuit itself. On line BIST is used to perform test under normal operation where as off line BIST for testing offline.


P(x) = x^5 + x^4 + x^2 + 1 G(x) with the sequence {1 1 1 1 0 1 0 1} G(x) = x^7 + x^6 + x^5 + x^4 + x^2 + 1 and R(x) = x^4 + x^2 which corresponds to the register(0 0 1 0 1) . R(x) is the remainder and Q(x) is the quotient.OUTPUT RANDOM ANALYZER Cyclic Redundancy Check G(x) = Q(x) P(x) + R(x) where P(x) is the characteristic polynomial (output of the CUT).

The on chip storage of a fault dictionary containing all the test inputs with the corresponding outputs is prohibitively expensive in terms of the chip area. . Alternative is to compare the outputs of 2 identical circuits for the same inputs assuming that the probability that the two devices will have the same kind of faults is less.