L38: Viterbi Decoder

SungKyunKwan Univ.

VADA Lab.

1

Viterbi Decoder
Convolutional Encoder
K = 3 (Constraint Length) R = 1/2 (Rate)
a j=u j+u j- 1 +u j- 2 + +

U

uj

aj

bj

V
Co d e wo rd

Info rm a tio n s e q ue nc e

A1

A0
+ b j=u j+u j- 2

A(3,1/2) Co nvo lutio na l e nc o d e r
SungKyunKwan Univ. VADA Lab.
2

Viterbi Decoder
Tim e S ta te 0 1 2 3 4 5 6

00

00

00

00

11

11

11

10
10 01 01

10

11

01

00

.......

01

11

10

Fig . 2.

Trellis d iag ram fo r a (2, 1/ 2) c o nvo lutio nal c o d e

Information sequence : U = (0,0,1,0,1,0,...) Output codeword : V = (00,00,11,10,00,10,...)
SungKyunKwan Univ. VADA Lab.
3

VADA Lab.Viterbi Decoder Viterbi Decoder Re c e ive d S ig na l BMU BM ACS U SP S MU De c o d e d Da ta PMM Vite rb i d e c o d e r s truc ture SungKyunKwan Univ. 4 .

This new partial path metric is compared with all the other new partial metric corresponding to all the other transitions entering that state. Add-Compare-Select Unit(ACSU) : To find the survivor path entering each state. stored in the SMU.Viterbi Decoder Branch Metric Unit(BMU) : The branch metrics measure the difference the received symbol and the symbol that causes the transitions between states in the trellis. The path metric of the survivor path of each state is updated and stored back into the PMM. The transition that has the minimum partial path metric is chosen to be the survivor path of the state. the branch metric of a given transition is added to its corresponding partial path metric(PM) stored in the path metric memory (PMM). Survivor memory Unit(SMU) : The survivor path are SungKyunKwan Univ. A traceback mechanism is applied on the SMU during 5 . VADA Lab.

6 . VADA Lab.Viterbi Decoder Low power ACSU VLSI architecture Conventional ACSU VLSI architecture S0 S0 sa sa S0 sb S1 Butterfly structure sb SungKyunKwan Univ.

Viterbi Decoder (s a . 7 .1 (s b . VADA Lab. S 0 ) BMi (s a ) PMi.1 (s b . S 1 ) BMi Ad d e r Co m p Ad d e r Ad d e r Co m p Ad d e r (S 1 ) Mi (S 0 ) Mi Architecture of conventional ACSU SungKyunKwan Univ. S 1 ) BMi (s b ) PMi. S 0 ) BMi (s a .

S 0 ) BMi (s a ) PMi. S 0 ) BMi (s a .1 + (s a . 8 . comparing with the conventional ACSU design SungKyunKwan Univ. S 0 ) BMi The area and power of the lower power ACSU design are reduced by 20% and 30%.1 - (s b ) PMi. respectively.1 > (s b . Solution] ÷Algorithm (s a ) PMi. S 0 ) BMi > (s b ) PMi.1 + (s b .Viterbi Decoder [SKKU. VADA Lab.

VADA Lab.Viterbi Decoder [SKKU. ISLPED¶99] SungKyunKwan Univ. Solution] Low power ACSU VLSI architecture [C-Y Tsui. 9 .

a d d (b ) < a d d .c o p a re (a) Lower power ACSU architecture (b) Conventional ACSU architecture The power consumption of architecture (a) is larger than that of architecture (b) by more than 17% because of glitch power dissipation SungKyunKwan Univ. DAC¶96] A B ¡ ¡   ¢   A B + C D X Y C D X Y < (a ) c o p a re .Viterbi Decoder [SKKU. 10 ¡ ¢   . Solution] Glitch minimization [Raghunathan. VADA Lab.

VADA Lab. B SungKyunKwan Univ.Viterbi Decoder [SKKU. 11 . Fs =1 = A . Solution] Glitches in control logic A B 0 1 + C D 0 1 C D S X Y < S & CLK F s =0 .

. 12 .. Sparso¶91] ACSU TraceBack Unit 1 TraceBack Unit 2 TraceBack Unit 3 . TraceBack Unit 10 Tra c e .Viterbi Decoder Low power traceback VLSI architecture Systolic Viterbi. traceback decoder[J..Ba c k Units The s truc ture o f s ys to lic Vite rbi de c o de r SungKyunKwan Univ.. VADA Lab.

00....Viterbi Decoder Tim e S ta te 0 0 1 0 2 0 3 1 2 1 3 0 0 1 2 3 4 5 6 00 2 0 1 0 1 0 3 1 2 1 3 0 10 4 0 2 0 1 0 3 0 2 0 01 p a th m e tric .) SungKyunKwan Univ..11. d e c is io n ve c to r 2 0 10 2 0 2 1 2 1 2 1 11 Seq uence of s taes of the trace.b ack methode Received codeword : V = (00..10....00.10. 13 . VADA Lab..

Viterbi Decoder Tim e un it 0 0 X X d e c is io n ve c to r s ta te with s m a lle s t p a th m e tric 1 ACSU 2 ACSU 0 0 0 0 0 0 X X 3 ACSU 0 0 0 0 0 0 0 0 0 0 X X 4 ACSU 1 1 0 1 0 0 0 0 0 0 0 0 0 0 X X SungKyunKwan Univ. VADA Lab. 14 .

Viterbi Decoder Ti 10 10 "0" 11 "1" 11 ACSU 12 SungKyunKwan Univ. . § ©¨ ¨§ su i d = 5K . . . T7 1 0 1 1 u i T1 0 1 0 0 0 ACSU 11 01 ACSU 10    T9 0 0 0 0 ¦ ¥ ¤£ T8 0 1 0 0 T6 0 0 0 0 T5 1 1 0 1 T4 1 1 0 1 T3 0 0 0 0 T2 0 0 0 0 T1 0 0 x x T1 1 T1 0 1 1 1 0 1 0 0 0 T9 0 0 0 0 T8 0 1 0 0 T7 1 0 1 1 T6 0 0 0 0 T5 1 1 0 1 T4 1 1 0 1 T3 0 0 0 0 T2 0 0 0 0 T1 0 0 x x 10 0 1 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 0 0 0 1 1 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 x x 11 00 VADA Lab. 15 .

0 0 0 0 11 0 0 0 0 1 0 1 1 00 0 0 0 1 1 0 0 0 10 1 1 0 1 0 0 0 1 01 0 1 0 0 1 1 1 0 01 1 0 0 0 0 0 0 0 10 0 1 0 0 1 0 1 1 00 0 0 0 0 1 1 0 1 10 1 1 0 1 0 0 0 0 10 0 0 0 0 0 0 x x 00 19 ACSU 20 ACSU 1 1 1 1 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 0 0 0 1 1 0 1 1 1 0 1 0 0 0 0 0 0 0 0 01 10 01 00 10 11 00 01 01 00 0 . 1 1 1 1 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 0 0 0 24 ACSU 01 00 10 11 00 01 1 SungKyunKwan Univ. 16 . . . VADA Lab.Viterbi Decoder . . .

SungKyunKwan Univ. 17 . This system consumes a great dynamic power consumption due to switching activities of registers which is almost 80% of the total power consumption because every data in TBU shifts for every cycle. VADA Lab.Viterbi Decoder Systolic array decoder The systolic array viterbi decoder is organized to input the decision vector and the smallest path metric out of the ACSU and to output the decode bit by shifting every register for every cycle.

18 .  A            2 A        CONTROL BLOCK CONTROL BLOCK CONTROL BLOCK 1 A   X X VADA Lab.Viterbi Decoder [SKKU. Solution] Our low power trace-back unit Tim e unit X X X X 3 SungKyunKwan Univ.

b a c k T8 0 1 0 0 T2 0 0 0 0 T3 0 0 0 0 T4 1 1 0 1 T5 1 1 0 1 T6 0 0 0 0 T7 1 0 1 1 T9 0 0 0 0 9 ACSU C O NTRO L BLO C K 0 0 X X 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 1 0 0 0 0 1 0 1 1 0 1 0 0 0 0 0 0 1 0 0 0 1 1 10 ACSU C O NTRO L BLO C K 0 0 X X 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 1 0 0 0 0 1 0 1 1 0 1 0 0 0 0 0 0 1 0 1 0 0 0 1 1 1 0 0 1 11 ACSU C O NTRO L BLO C K SungKyunKwan Univ. Solution] . T1 0 0 X X Tra c e . 19 . .Viterbi Decoder [SKKU. . VADA Lab.

0 0 X X 0 0 0 0 0 0 0 0 1 0 1 1 0 1 1 1 0 1 1 0 0 0 0 0 1 0 1 1 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 1 1 1 0 0 1 0 1 0 0 0 0 0 1 0 1 1 1 0 1 1 0 0 0 1 0 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 19 ACSU 0 0 C O NTRO L B LO C K 0 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 0 1 0 0 0 0 0 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 0 0 1 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 0 0 0 0 0 1 0 1 1 0 1 1 0 0 0 0 1 0 0 0 0 0 1 1 1 1 0 1 20 ACSU 0 0 0 C O NTRO L B LO C K 0 0 0 0 1 1 0 1 1 1 0 1 1 0 0 0 0 0 1 0 1 1 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 1 1 1 0 0 1 0 1 0 0 0 0 0 1 0 1 1 1 0 1 1 0 0 0 1 0 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 21 ACSU 0 1 0 C O NTRO L B LO C K SungKyunKwan Univ. .Viterbi Decoder [SKKU. . . 20 . VADA Lab. Solution] .

but by shifting the lower 2-bit only. to the left SungKyunKwan Univ. The register array. was provided to finally output decoded bit. VADA Lab. which stores the value of trace-back from the CB. which is the smallest path metric. Solution] After decision vector and the smallest path metric generated from ACSU are transferred to the Control Block (CB). not by shifting all higher 4-bit decision vector as in the classical TBU. the CB outputs the decision vector and the smallest path metric with the right cycle using a counter and a multiplexer. 21 .Viterbi Decoder [SKKU.

b a c k U n it Lo w P o w e r Tra c e .ba c k Unit Tra c e . VADA Lab. Solution] Experimental Result (area 11% .b a c k U n it SungKyunKwan Univ. 22 . power 40% ) Ar e a 8000 7000 6000 5000 g a te s 4000 3000 2000 1000 0 2 3 K 4 1600 1400 1200 P o w e r Di s s i pa t i o n p o w e r(uW 1000 800 600 400 200 0 2 3 4 K Tra c e .Viterbi Decoder [SKKU.ba c k Unit Lo w Po we r Tra c e .

VADA Lab. 23 .h.Lee . Algorithm c o nve rg e p o int time n+1 time n Tra c e b a c k p ro c e s s ing SungKyunKwan Univ.Viterbi Decoder [Stanford Solution] Low Power Asynchronous Viterbi Decoder Stanford] [Y.

: . . .Viterbi Decoder [Stanford Solution] : . route B. A . Loop A. 24 . VADA Lab. SungKyunKwan Univ. route . . route trace back node 5 trellis traceback .

VADA Lab.Viterbi Decoder [Stanford Solution] Implementation Self-precharge & Self-requesting if not found Previous path Input Port ddress RD/WR Control Surviving Path Memory M U X Shift Reister race ack Unit scillator Ring Comparison ogic Request Request form CS ddress RD/WR Control Memory Management Unit if Path is not found cknowledge to CS if path is found Self-timed TBU block diagram SungKyunKwan Univ. 25 .

Viterbi Decoder Self-timed TBU ACS request request . TBU previous path memory update self. self-requesting . surviving path memory previous path memory . TBU . VADA Lab. precharging. TBU request SungKyunKwan Univ. . ACS 26 . ACS scknowledgement . .

K.8mW at 2Mbps operation under 1. 1999. Chang. Y. K. Suzuki.5Qm CMOS technology and is operative at 20Mbps under 3. 27 . CICC Abstract y This paper presents a low-power bit-serial Viterbi decoder chip with the coding rate K=1/3 and the constraint length K=9(256 states) y The Add-Compare-Select(ACS) units have been designed using bit-serial arithmetic and a power efficient trace-back scheme and an application-specific memory have been developed for the traceback operation.Low-Power Bit-Serial Viterbi Decoder H. Parhi ³Low-Power Bit-Serial Viterbi Decoder for 3rd Generation W-CDMA System´. VADA Lab.8V SungKyunKwan Univ. y The chip was implemented using 0.8V.3V and 2Mbps under 1. The power dissipation is only 9. N.

Low-Power Bit-Serial Viterbi Decoder Architecture Overview y 256 bit-serial ACS units are placed in parallel and each ACS unit include state metrics storage y Trace-back block. VADA Lab. a 256 x 48 bit memory is required for the survivor path length of 48 SungKyunKwan Univ. 28 .

VADA Lab. 29 .Low-Power Bit-Serial Viterbi Decoder Bit-Serial Viterbi Decoder Chip Diagram SungKyunKwan Univ.

Low-Power Bit-Serial Viterbi Decoder Bit-Serial ACS Unit Bit-serial ACS unit SungKyunKwan Univ. 30 . VADA Lab.

31 .Low-Power Bit-Serial Viterbi Decoder y Each ACS unit has three full-adders. y Two of them are used to add the state metric and the branch metric and the third one is used to compare two new state metrics y Reducing the overhead down to 17% of the whole area of the ACS unit SungKyunKwan Univ. VADA Lab.

VADA Lab. 32 .Low-Power Bit-Serial Viterbi Decoder Trace Back Strategy Trace Back operation SungKyunKwan Univ.

Low-Power Bit-Serial Viterbi Decoder y The memory size required in this paper is twice as large as the minimum memory size(256 x 2). 24 decoded bits are obtained consecutively. SungKyunKwan Univ. VADA Lab. y After 48 ³TRACE BACK´ operations. 33 . a read pointer and a write pointer are required and the speed of the read pointer should be three times as fast as that of the write pointer y This operation was implemented with single-port memories using a time-multiplexed access method. y Two separate pointers. namely.

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