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A COMPREHENSIVE TUTORIAL
± System design approach with HDLs ± History of VHDL ± Why VHDL ?
± Simulation Cycle ± Digital Simulator
Modeling of Hardware Language Basics
± Building Blocks in VHDL ± Design Units and Libraries
Objects and Data Types Structural Description
± Basic Features ± Configuration Specification ± Configuration Declaration
± Process Statement ± Behavioral Modeling - Sequential View ± Behavioral Modeling - Concurrent View
± A complex system can be easily decomposed into smaller pieces : improves modularity ± Allows a design to be simulated and synthesized before being manufactured.Introduction System Design Approach with HDLs ± HDL is mostly related to the front end part of the design flow where a system is described with programming language constructs. . » » » Eliminates hardware prototyping expenses Reduces design time Increases design reliability at lower costs/time req.
) Typical Design Algorithm HDL Description (Behavioral) Register Transfer Level simulation and verification Level of abstraction flow Synthesizer Structural Description Technology mapping (with ready-made primitives) + Floor Planning Physical Layout .Introduction(contd.
Introduction(contd. box) level to gate level Capability of mixing descriptions ± Design Exchange ± Large Scale Design and Design re-use .) Why VHDL ? ± Public Availability Developed initiated under Government Contract Now is an IEEE standard ± Design Methodology and Design Technology Support ± Technology and Process Independent ± Wide Range of Descriptive capabilities Digital System (e.g.
capabilities.Simulation Fundamentals Purpose of simulation is to verify the behavior of a system by applying stimulation at the inputs and monitoring the response of the system over a period of time. no precise value is required. There are three types of simulators : ± ± ± Purely analog simulator. In digital simulation only logic level of the measured quantity is determined. In analog simulation the precise values of the measured quantities are determined . A simulator with both digital and analog simulation Purely digital simulator.
Maintains node values at logic level. The design contains a number of concurrently operating blocks connected with each other by signals. Maintains a time wheel to model propagation of time. Evaluates circuit behavior at intervals of time. .Simulation Fundamentals(contd. The interval is chosen as the smallest unit of time after which a node can change its state.) The system is described with a Hardware Description Language (HDL).
± Makes no assumptions about the technology. timing model and structural model are integrated. . ± A VHDL process models a block and a VHDL signal models the connection between different blocks. ± Multiple levels of abstraction for modeling Behavioral Structural Dataflow ± Behavioral model.Modeling Hardware The VHDL Language ± A language for describing digital and analog systems.
Structural Model Digital circuits consist of components and interconnection between them A component can in turn be composed of subcomponents and their interconnections A component interacts with other components through pins Component is modeled as entity Component pins are modeled as ports Interconnections between components are modeled as signals .
Behavioral Model ehavioral The behavior of a component is modeled inside an architecture body of the entity It may be described using a collection of concurrently executing statements A concurrent statement is sensitive to a set of input signals and is executed whenever any of its sensitive signal changes its value A concurrent statement called process statement can contain one or more sequential statements A set of sequential statements can be clubbed together in a subprogram .
The structure of the entity is not explicitly specified but it can be implicitly deduced. . Architecture MYARCH of MYENT is begin SUM <= A xor B after 8ns end MYARCH.Dataflow Model The flow of data through the entity is modelled primarily using concurrent signal assignment statements.
end process. in2. Out1 : out bit). wait on In1. end behavioral. . in2 : in bit. architecture behavioral of Xor_gate is begin process begin Out1 <= In1 xor In2. end Xor_gate .A simple Example entity Xor_gate is port (in1.
VHDL Libraries Design Units A VHDL library is a host dependent storage facility for intermediate-form representations of analyzed design units A design unit is a VHDL construction that can be independently analyzed and stored in a design library. Primary design unit ± entity decl. there can be only one primary unit of same name but there can be multiple secondary units by same name A secondary unit can have name same as primary unit . package decl and configuration decl Secondary design unit ± architecture body and package body In a library. A design unit may be a primary or a secondary one.
subprogram body . declarations. statements Architecture Body ± declarations.list Subprogram Specification ± declarations statements Package Declarations ± declarations Package Bodies ± declarations. port.Building Blocks in VHDL Entity Declaration ± generic. statements Subprogram Declaration ± parameter .
port interface_list. .ENTITY provides a name to the component contains the port definitions in the interface list can contain some generic definitions which can be used to override default values entity identifier is generic interface_list. declarations begin statements end [entity] [identifier].
Example entity Adder is port ( A : in Bit. B : in Bit. Sum : out Bit. A B Sum Cout Adder . end Adder. Cout : out Bit ).
Architecture encapsulates the behavior and timing information contains a number of concurrent statements there can be multiple architecture bodies for a given entity architecture identifier of entity_name is declarations begin statements end [architecture] [identifier]. .
B) Sum <= A or B after 5 ns. end Behavioral_Desc . Cout <= A and B after 6 ns.ExampleExample-1 architecture Behavioral_Desc of Adder is begin process (A. end process.
declarations component Or_Comp port ( X : in Bit. . Out : out Bit). Y : in Bit. end component. Out => SUM). begin -. B1 : And_Comp port_map ( X => A. y =>B. Out => Cout). Out : out Bit). end Struct_Desc. Y : in Bit.component instantiations A1 : Or_Comp port_map ( X => A. end component. component And_Comp port ( X : in Bit. y =>B.ExampleExample-2 architecture Struct_Desc of Adder is -.
Subprograms Subprograms are of two types : functions and procedures A subprogram consists of a sequence of declarations and statements which can be repeated from different locations in VHDL descriptions subprograms can be overloaded functions can be used for operator overloading procedures can assign values to its parameter objects while functions can not A subprogram can be separated into its subprogram declaration and subprogram body .
.specification » procedure identifier interface_list » [pure | impure] function identifier interface_list return type_mark Full form of subprogram body is subprogram-specification is declarations begin statements end identifier.Subprograms (contd.) Full form of subprogram declaration is subprogram-specification. Two forms of subprogram .
Examples of function declaration ± Object class of parameter is implicit function Mod_256 (X : Integer) return Byte. Parameter of type FILE has no mode. If no mode is specified. . ± Object class of parameter is explicit function Mod_256(constant X : in Integer) return Byte. If no class is specified parameters are interpreted as being of class constant.Functions Intended to be used strictly for computing values and not for changing value of any objects associated with the function¶s formal parameters All parameters must be of mode in and class signal or constant or File. the parameter is interpreted as having mode in.
end if. -. end Min. .Function Specification function Min (X.Example Function declaration function Min (X. Y : Integer) return Integer. Y : Integer) return Integer is begin if (X < Y) then return X. else return Y.
Examples of procedure declaration ± Object class of parameter is implicit procedure Mod_256 (X : inout Integer). Parameter of type FILE has no mode.Procedures Procedures are allowed to change the values of the objects associated with its formal parameters Parameters of procedures may of mode in. out or inout If no mode is specified the parameter is interpreted as having mode in. ± Object class of parameter is explicit procedure Mod_256(variable X : inout Integer). If no class is specified parameters of mode in are interpreted as being of class constant and parameters of mode out or inout are interpreted as being of class variable. .
end case.Example Procedure declaration --. end ModTwo.Procedure Specification Procedure ModTwo (X : inout Integer) is begin case X is When 0 | 1 => null. .X is of class variable Procedure ModTwo (X : inout Integer). -. When others X := X mod 2.
µz¶). shared variables and files). end logic. object declarations (signal.Packages Allows data types. to be shared by multiple design units. component declarations etc. subprograms. . function invert (Input : Three_level_logic) return Three_level_logic. package identifier is declarations end [package] [identifier]. µ1¶. constants. Example : package logic is type Three_level_logic is (µ0¶.
.Package Body Package declarations and bodies are separately described Package declarations contain public and visible declarations Items declared inside package body is not visible outside the package body Package body has the same name as the corresponding package declaration package body identifier is declarations end [package body] [identifier].
subprogram body of function invert function invert (Input: Three_level_logic) return Three_level_logic is begin case Input is when µ0¶ => return µ1¶.Package Body (contd.) Example of a package body for package logic package body logic is -. end invert. when µ1¶ => return µ0¶. when µZ¶ => return µZ¶. end logic. .
std_logic_1164.all. So if those use clauses are sufficient for the descriptions inside the architecture.Logic. Makes Three_level_logic in package Logic in library work visible » use work.Three_level_logic. . then no explicit use clause is necessary for the architecture Simple examples : Makes all items of package std_logic_1164 in library ieee visible » use ieee.USE CLAUSE Use clause preceding an unit makes all the elements of a package or a particular element of a package visible to the unit An architecture body inherits the use clauses of its entity.
Three_level_logic. use my_lib.Use Clause (contd. entity Inverter is port (X : in Three_level_logic.Invert. end inverter. Y : out Three_level_logic).) library my_lib.Logic.Logic. use my_lib. .
configuration referenced in a configuration declaration must be analyzed before the configuration declaration is analyzed A library clause makes library visible and an use clause makes the units inside the library visible to other units library Basic_Library.all. architecture.Logic. . Use Logic.Analysis Rules for Units Units can be separately analyzed provided following rules are obeyed ± a secondary unit can be analyzed only after its primary unit is analyzed ± a library unit that references another primrary unit can be analyzed only after the referred unit has been analyzed ± an entity. Use Basic_Library.
Objects and Data Types Something that can hold a value is an object (e. every object has a type. i. the type determining the kind of value the object can hold VHDL is strongly typed language The type of every object and expression can be determined statically.e the types are determined prior to simulation.g signal) In VHDL. Three basic VHDL data types are ± integer types ± floating point types ± enumerated types Data types can be user defined .
Real and Physical types are called numeric types Composite Type Access Type Record Array File Type .Data Types Data type Scalar Type Integer Float Physical Enumeration Integer and enumeration types are called discrete types Integer.
BLUE).) Scalar Type » Most atomic » Can be ordered along a single scale Integer types type Byte is range -128 to 127. type Color_set is (RED. Enumerated Types consists of enumeration literal ± a literal is either an identifier or a character literal type Three_Level_Logic is (µ0¶. µz¶). . Floating types type fraction_type is range 100.1 to 200. type Bit_pos is range 7 downto 0. µ1¶.1.Data Types(contd. GREEN.
Data Types : Scalar Type (contd. Any value of a physical type is an integral multiple of the primary unit of measurement for the type Example type Time is range -(2**31 -1) to (2**31 -1) units fs . --.) Physical Type Values of physical type represent measurement of some physical quantity such as time.primary unit ps = 1000 fs. --.secondary unit ns = 1000 ps.secondary unit end units. --. distance etc. .
± bit_string and physical literal.6#e+4 43.Literal These are symbols whose value is immediately evident from the symbol Six Literal Types ± integer. characters.3 sec .6E-4 ± ³ABC()%´ ± B´1100´ X´Ff´ O´70´ ± 15 ft 10 ohm 2. Examples ± 2 19878 16#D2# 8#720# 2#1000100 ± 1. strings.3333 8#43.9 65971. floating.
Composite type are used to define collection of
Can be decomposed into smaller atomic types Composite Types are of two types
Records - heterogeneous composite Record Type definition specifies one or more elements,
each element having a different name and possibly a different type.
type OpCode is (add, sub, compl); type address is range 16#0000# to 16#FFFF#; type instruction is record
Opc_field : OpCode; Op1 : Address; Op2 : Address;
Arrays - homogenous composite type
± type Word is array (15 downto 1) of Bit;
Can have multiple dimensions
± type Arr2Dim is array
(integer range1 to 3, integer range 5 to 7) of integer;
Each dimension must be of discrete type
± integer or enumerated
Can be constrained or unconstrained
array has bounds specified
± unconstrained array has no bounds
type Matrix is array (Row range 1 to 10. . Column) of Boolean. Column range 1 to 40 ) of Boolean. ± range is a subtype indication type Column is range 1 to 80. type Matrix is array (Row.Constrained Arrays The type and range are both specified by discrete range Two Forms ± simple range specification type Word is array (15 downto 1) of Bit. type Severity_level_stats is array(Note to Failure) of Integer. type Row is range 1 to 24.
Unconstrained Arrays The type of each dimension is given but range bounds and direction is not specified ± type Screen is array (Integer range <>. ± type String is array (Positive range <>) of Character. Two predefined unconstrained array ± type Bit_vector is array (Natural range <>) of Bit. Integer range <>) of Pixel. Useful in defining interface list having variable number of bits in ports .
positional ± (Numerator => 155. µ0¶) -.named ± ( Low | Falling => µ0¶) -.named . µ0¶. each element specifies values of an element of the array or the record Value association may be named or positional Examples ± (155. 203) (µ1¶. Denominator=>200) -.Aggregates Values of composites can be given in aggregate notation An aggregate is a parenthesized list of element associations.
When an objet of access type is declared. The objets of an access type can only belong to variable class. default null .access type declaration variable MOD_PTR : PTR. delay : time. --. They are similar to pointers in Pascal or C language.access variable. Example : type module is record size : integer.Access Type Values belonging to an access type are pointers to a dynamically allocated object of some other type. type PTR is access module. the default value of that objet is null. end record. --.
. read.txt´. or tested for an end-of-file condition by using special procedures and functions that are implicitly declared for every FILE type Example : type intFileType is file of integer. file F1 : intFileType. written to. file F2 : intFileType is ³myFile.File Type > > > Objects of FILE types represent files in the host environment Provides a mechanism by which a VHDL design may communicate with host environment A file can be opened. closed.
Error. True)..1) to (2**31 . Each implementation can define range of pre-defined types differently Scalar Types : ± type Integer is -(2**31 ... ± type Severity_Level is (Note. Composite Types : ± type Bit_vector is array (Natural range <>) of Bit.. µa¶. SOH.1) ± type Real is -16#0.. DEL). Warning.. ± type Character is (NUL. µ1¶).. .. PrePre-Defined Types . ± type String is array (Positive range <>) of Character. Failure).. . ± type Bit is (µ0¶. µb¶.7FFF_FF8#E+32 ± type Boolean is (False.7FFF_FF8#E+32 to 6#0.
º S_byte (3 downto 1) --. ± signal S_mem : S_memory.slice of three elements º S_mem (2**15 -1 to 2**16 -1) --.Referencing Elements of Composite Can be referenced in entirety or by element An indexed name is used to refer to an element The type of an indexed name is the type array element A slice name is a reference to a contiguous subset of elements in an one-dimensional array Examples ± type Byte is array (7 downto 0) of Bit. ± type S_memory is array (0 to 2**16 -1) of Byte. ± signal S_byte : Byte.slice of one element .slice of 2**15 elements º S_mem (0) (0 downto 0) --.
Subtypes A subtype is a type with a constraint A value belongs to a subtype of a given type if it belongs to the type and satisfies the constraint The given type is called the base type of the subtype Subtypes of a type are fully compatible with each other Two ways to constraint a type by a subtype ± a range constraint that defines a subset of values of a scalar type subtype LowerCase is Character range µa¶ to µz¶. ± to specify an index constraint of a array dimension of unconstrained type subtype Register is Bit_Vector (7 downto 0). .
unit.Attributes Attribute is a named characteristic It may belong to the following classes of items in VHDL ± ± ± ± ± ± ± type. and if it does have a value. group. configurations and packages components statement labels literal. file A particular attribute for a particular item may have a value. variable and constants entities. subtypes procedure. the same may referenced as ± name ¶attribute_identifier Attributes may be pre-defined or user-defined . architectures. functions signals.
) Pre-defined attributes for scalar subtypes ± µleft. µlow ± Example type Bit_position is range 15 downto 0.Attributes (contd. µright. Bit_position¶left = 15 Bit_position¶low = 0 Bit_position¶right = 0 Bit_position¶high = 15 . µhigh.
µright. Pre-defined attributes for any physical subtype or any discrete subtype ± µpos. µhigh. µsucc.1) ± For a physical or discrete type T. µpred. µleftof. µlow. with ascending range T¶rightof(x) = T¶succ(x) T¶leftof(x) = T¶pred(x) Pre-defined attributes for constrained array subtypes and array objects ± µleft. µreverse_range .) ± For any physical or discrete type T T¶succ(x) = T¶val(T¶pos(x) + 1) T¶pred(x) = T¶val(T¶pos(x) . µlength. µrightof ± Example Bit_position¶pos(15) = 15 Bit_position¶val(15) = 15 Attributes (contd. µval. µrange.
Attributes (contd. Cout : int_type. associates a user-defined attribute with one or more named entities and defines a value of that attribute of that attribute for that named entity signal Cin. ± Attribute Specification : . type int_type is range 1 to 100. attribute INDEX : int_type. type_mark. attribute CAPACITANCE of all : signal is 10 pF.) User Defined Attribute : ± Attribute declaration syntax: attribute identifier : type_mark. attribute INDEX of Cout : signal is 5.
accessing the attribute value s1 <= s3¶SIG_NUM. --. s3 : int_subtype. --.for s2.attribute specification attribute SIG_NUM of s1 : signal is 1. s3 begin --. architecture att_example of att_example is subtype int_subtype is integer range 1 to 100. signal s1. --. --.assigns value 3 to signal s1 end .attribute declaration attribute SIG_NUM : int_subtype. --.Attributes (contd.for s1 only attribute SIG_NUM of others : signal is 3.) Example : entity att_example is end. s2.
± signal enable : Bit := µ0¶. Signals are like wires.Objects Four types of objects ± signals. . variables.txt´. ± variable fetch : Boolean := TRUE. Variables have no hardware equivalent. ± constant ROM_size : integer := 16#FFFF#. Constants are assigned only once. A file declaration declares a file of specified type. constants and files Signals and variables can be assigned values in succession. ± variable address : integer range 0 to ROM_size := 10. ± type integer_file is file of integer. Every object must be of a type and has to be defined in its declaration. ± file F1 : integer_file is ³test.
Within the sequence of statements these are considered as constants and hence can¶t be modified. Procedure Parameters . variable or file. ³out´ or ³inout´. components.Object class must be constant. .Mode should be ³in´.constants º Ports (entity. blocks) . . º Indexes of Loop and Generate statements . signal or file.Mode should be ³in´.Object class may be constant. .signals º Subprograms º º Function Parameters . signal.Objects (contd.) Following are Implicitly defined Objects º Generics .
Specifies interfaces or potential points of communication between units. local component declaration. buffer(for ports only) or linkage(for ports only) ± Data type Interface Lists . The object in a single interface element have three properties in common ± Object Class : signal. variable or file ± Mode : in. out. block statement and subprogram specification Each interface element declares one or more interface objects. Four VHDL constructs that specify this ± entity declaration. constant. inout.
.Association Lists Actual communication path between separate units. Four VHDL constructs that specify this ± Component instantiation statement ± binding indication ± block statement ± subprogram call Association may be named or positional.
No separate binding is required. The component needs to be bound to some actual entity(architecture) with a configuration. Block Statement Generate Statement Configuration Specification Configuration Declaration . Direct instantiation statement (VHDL 93 feature) No component needs to declared.Structural Description Basic Features ± Component Instantiation Statement It is concurrent statement. It can be done by Instantiation of a declared Component A component is instantiated. An entity(architecture) can be directly instantiated.
i.e. Component instantiation can be done by » Instantiating a declared component and providing binding information to bind it with actual entity(architecture) » Directly instantiating an entity(architecture).Basic Features Structural description of a piece of hardware is a description of what its sub-components are and how the sub-components are connected Structural description is more concrete than behavioral description. No separate component declaration and binding information is needed. (: VHDL 93 feature) . correspondence between a given portion of description and a portion of hardware is easier to see in structural descriptions Component Instantiation statement is basic unit of structural Description.
only the external view of the child component (the names. instantiated_unit ::= [component] component_name | entity entity_name [(architecture_identifier)] | configuration configuration_name . types and directions of ports) is visible The statement identifies the child component and specifies the connectivity of the local signals or ports of parent component with the ports of child component General Form of the statement label: instantiated_unit generic map association-list port map association-list.Component Instantiation Component Instantiation statement specifies an instance of a component (child component) occurring inside another component (parent component) At the point of instantiation.
the port association list associates an actual with a local The associated actual must be » an object of class signal » open » static expression if port mode is ³in´ .g through a visible package) A port of Component Declaration is called a local In a component instantiation statement. (e.Component Instantiation Generic/Port map associations are omitted if the corresponding component declaration lacks generics/ports The component_name must reference a component declared by a component declaration. The component declaration need not occur in the architecture body containing the instantiation but it must be visible at the point of instantiation.
Example architecture Parent_body of Parent is component And2 -. . signal S1. I2 : Bit.Component Declaration port ( I1. I2=>S2. S2. begin Child : And2 port map ( I1=>S1. -Instance end Parent_body. end component. S3 : Bit. O1 : out Bit). O1=>S3).
Entity Vs Component ENTITY Entity is a library unit which can be compiled separately and it never occurs inside another library unit Entity declaration declares something that really ³exists´ in the design library COMPONENT Component Decl only occurs inside a library unit. It may occur inside a Package Decl or an architecture body Component declaration merely declares a template that does not exist in the design library .
then the actual must also be writable ± Association with a local of mode out or inout creates a source for the actual. It follows that an actual. and if the local is writable. may not be associated with more than one locals of mode out or inout . then the actual must also be readable. which is not a resolved signal.Port Association VHDL imposes three kinds of restrictions based on type mode and resolvability. on the association of an actual with local ± VHDL requires that the type of actual be the same as the type of the local ± VHDL requires that if the local is readable.
Outputs : out Bit_vector (1 to 8)). architecture Invert_8 of Invert_8 is component Inverter port ( I1 : Bit. Outputs(I)). end generate. O1 : out Bit). end Invert_8. . end component. begin G: for I in 1 to 8 generate inv : Inverter port map (Inputs(I). end Invert_8.Example entity Invert_8 is port ( Inputs : in Bit_vector (1 to 8).
the number of instantiated sub-components. ± The only mode permitted is in. the range of subtypes. Typical use of generics are to parameterize timing. Allowed inside ± Entity Declarations ± Component Declarations ± Blocks . ± The only object type permitted is constant. and the size of array objects (in particular the size of ports) Generics are declared as interface elements.Generics Generics provide a channel for static information to be communicated to a design-block from its environment.
eI2 => cI2. . begin AND1 : gate generic map (cg => 3) port map (cI1 => s1. end component.and_gate(and_gate_arch) generic map (eg => cg) port map (eI1 => cI1. cO => s3). eO => cO). architecture and_gate_arch of and_gate is begin --.implementation not shown end. architecture top of top is signal s1. cI2 : in bit_vector(1 to cg). port (eI1. eO : out bit_vector(1 to eg)). s2. entity top is end.entity and_gate is Example generic (eg : integer). eI2 : in bit_vector(1 to eg). end. for all : gate use entity work. cI2 => s2. component gate generic (cg : integer). cO : out bit_vector(1 to cg)). port (cI1. s3 : bit_vector(1 to 3). end.
. block statement part Block Header Block header explicitly identifies certain values. Block Statement Part Block statement part consists a set of concurrent statements. These items are local to block scope. constant. subprogram. signal «etc can be declared in the block declarative part. subtype. Blockinternal block representing a portion of a Statement A block statement defines an design. signals which are to be imported from the enclosing environment into the block and associated with formal generics and ports Block Declarative Part Type. Blocks may be hierarchically nested to support design decomposition A block may have three parts » block header. block declarative part.
port map (bp1 => sig_a).block declarative part signal sig_b : integer. generic map (bg => con_a). end block. constant con_a : time := 1 ns. end . port (bp1 : in integer).Example entity ent is end. begin --. --. begin B : block --.block header part generic (bg : time). architecture arc of ent is signal sig_a : integer.block statement part sig_b <= sig_a after bg.
A generate statement provides a mechanism for iterative or conditional elaboration of a portion of description Consists of a generation-scheme and a set of enclosed concurrent statements Following VHDL concurrent statements may be enclosed by the generate statement ± Process statement ± Block Statement ± Concurrent assertion statement ± concurrent signal assignment ± concurrent procedure call ± concurrent instantiation statement ± another generate statement
Generate Statements (contd.)
General Form is label-identifier : generation-scheme generate concurrent-statements end generate identifier; There are two kinds of generation scheme ± if-scheme ± for-scheme
entity Invert_8 is port ( Inputs : in Bit_vector (1 to 8); Outputs : out Bit_vector (1 to 8)); end Invert_8; architecture Invert_8 of Invert_8 is component Inverter port ( I1 : Bit; O1 : out Bit); end component; begin G: for I in 1 to 8 generate inv : Inverter port map (Inputs(I), Outputs(I)); end generate; end Invert_8;
± component_specification Identifies which instances are configured Consists of an instantiation label (or a label list) followed by colon and the component name Specifies mapping between the component and the entity It may also contain a generic/port association list ± binding_indication .Configuration Specification This construct allows the designer to specify the selection of entity declaration and architecture body for each component instance. General Form is for component_specification use binding_indication .
± for all : And_gate use entity work.Configuration Specification Example ± for U1. Use of others means that the configuration specification applies to all the instantiations of the given component except for those instances which are already configured by the preceding configuration specifications . U2 : Inverter use entity work.Inv2(Inv2_body).And_gate1(And_gate1). Instantiation label allows two key words all and others Use of all means that the configuration specification applies to all the instantiations of the given component.Inv1(Inv1_body). ± for others : Inverter use entity work.
This has following two benefits ± Provides support for top-down design methodology ± Allows a designer to take advantage of a library of reusable components. The binding of a component instance to design entities can be performed by configuration specification which appears in the declarative part of the design-block in which the the corresponding component instance resides. leaving the component in the design-block unbound. the user can defer the binding of the component instance until later. Configuration declaration provides the mechanism for specifying such deferred binding. Otherwise. .Configuration Declaration Configures sub-component hierarchy.
component configuration for instantiations in intel end for.for architecture ARCH_COMM_BOARD end FULL_SLOT. . --.for PROCESSOR « --.for intel end for.SPARC(intel) generic map (Clock => 40 ns). Consider the configuration declaration for an entity COMM_BOARD that fits into a full PC slot Example configuration FULL_SLOT of COMM_BOARD is for ARCH_COMM_BOARD for CPU : PROCESSOR use entity std_parts. --. --. for intel --.configuration of other different units end for.
Sequential View ± Signal Assignment ± Delay in Signal Assignments ± Variable Assignment ± Sequential Statements Conditional Control Iterative Control Assertion Statement .Behavioral Description Sequential vs Concurrent Process Statement ± Wait Statement Behavioral Modeling .
Behavioral Description (contd.Concurrent View ± Concurrent Signal Assignment ± Conditional Signal Assignment ± Selected Signal Assignment Resolved Signals .) Behavioral Modeling .
sequential and concurrent level. Sequential statements are executed in the order in which they appear. ± The sequential level involves programming the behavior of each process that will be used in the model. Used for algorithmic descriptions. .Sequential vs Concurrent In VHDL there are two levels at which designer must define the behavior of a discrete system. with no defined relative order. Process statements are executed concurrently but the statements inside a process statement are executed sequentially. ± A concurrent statement executes asynchronously. Concurrent statements are used for data-flow and structural descriptions ± The process statement is a concurrent statement which delineates set of sequential statements.
The behavior of the process is described with a set of sequential statements.Process Statement The process statement is a concurrent statement that defines a specific behavior to be executed when the process becomes active. . General Form is : process_label: process declarations begin statements end process.
The process remains suspended until its reactivation condition is met .) A process is either active or suspended A process becomes active when any of the signal read by the process changes its value All active processes are executed concurrently A process may be suspended upon execution of a wait statement in the process.Process Statement (Contd.
e. ± signal sensitivity wait on signal-list. It is illegal to use wait statement in a process with a sensitivity list Every process is executed once upon initialization . ± condition wait until condition.Wait Statement Three kind of reactivation condition can be specified in a wait statement ± timeout wait for time-expression. Conditions can be mixed. B until Enable = 1. it is possible to designate sensitivity signals using a sensitivity list.g wait on A. If a process is always sensitive to one set of signals.
In2) begin Output <= In1 or In2. --. wait on In1. In2.this process is sensitive to signals In1 and In2 Or_process : process (In1. . end process.Example The following process implements a simple OR gate---.this is equivalent to Or_process : process begin Output <= In1 or In2. end process.
Sequential Assignment This assignment occurs in a process or subprogram It is sequentially executed There are two fundamental types of assignment ± Signal Assignment ± Variable assignment .
Simplest form signal_name <= value. This assigns value to the current value of the signal at the beginning of the next cycle .Signal Assignment A signal is comprised of a current value and a projected waveform The current value always holds the value of the signals as read by other process The projected waveform contains scheduled values on this signal at future times.
Signal Assignment (contd.) Delay in signal assignment ± It is possible to assign values with a delay ± Delay is relative to current time ± If no explicit delay is specified a delta delay is assumed ± General Form : signal_value <= value after time-expression .
Example Consider this Example signal A : Bit := 0. end process. assert ( B = A) report ³ B is not equal to A´ severity error. wait on B. P1 : process begin B <= A. Will the message be printed ? . signal B : Bit := 1.
If source process is in another component it is taken from the port . .Signal Drivers A driver is a collection of value time pairs referred to as transactions Every concurrent statement which assigns to a signal creates a driver for that signal Only one driver is allowed for a signal unless it is a resolved signal Initial value of the driver is taken from the default value of the declaration which is visible to the source process.
Delay in Signal Assignment There are two types of delay that can be applied when assigning a time/value pair into the driver of a signal ± Inertial Delay ± Transport Delay .
no output change occurs. The value appears at the output after the specified inertialdelay. An input value must remain stable for a specified time (pulse rejection limit) before the value is allowed to propagate to the output.Inertial Delay Inertial delay models the delays often found in switching circuits. Inertial signal assignment has the form : signal_object <= [ [ reject pulse-rejection-limit ] inertial ] expression after inertial-delayvalue. If the input is not stable for specified rejection limit (pulse rejection limit). Example : Z <= reject 4 ns inertial A after 10ns .
Transport Delay This delay models pure propagation delay. ie. any change in the input (no matter how small) is transported to the output after the specified delay time period To use a transport delay model. the keyword transport must be used in a signal assignment statement Ideal delay modeling can be obtained by using this delay model. where spikes would be propagated through instead of being ignored .
i. The variable assignment updates the value immediately after the assignment without any delay .e it is never re-initialized Variables declared in subprograms are reinitialized whenever the subprogram is called General Form of variable assignment is ± variable_name := expression.Variable Assignment A variable is declared in a process or a subprogram When a variable is declared with a process it retains its value throughout the simulation.
e statements are executed when a given condition is true VHDL provides two types of conditional control statements ± if then elsif ± case end case .Conditional Control These sequential statements provide conditional control i.
If Statement General form is if condition then statement elsif condition then statement else statement end if. .
. wait on In1. end if. else Out <= µ1¶ after Delay. In2. elsif In1 = µX¶ or In2 = µX¶ then Out <= µX¶ after Delay.Example And_process : process begin if In1 = µ0¶ or In2 = µ0¶ then Out <= µ0¶ after Delay. end process.
Case Statement General Form is case expression is when value => statements when value | value => statements when discrete_range => statements when others => statements end case .
Example Select_process : process begin case X is when 1 => Out <= µ0¶. when 2 | 3 => Out <= µ1¶. end process . when others => out <= µX¶. end case.
Iterative Control In this control the execution iterates over the statements until some condition is met VHDL provides iterative control inform three kinds of loop statements ± Simple loop ± for loop ± while loop .
Simple Loop Simple loop encloses a set of statements in a structure which is set to loop forever General Form is loop_label : loop statements end loop loop_label. .
Loop2 :loop B := B . wait. end process. begin Loop1 :loop A := A + 1. end loop Loop1. . end loop Loop2.Example P1 : process variable A : Integer :=0. B := 20. variable B : Integer.A.
While Loop General Form of for loop: loop_label: for loop_variable in range loop statements end loop loop_label.For Loop. . General Form of while loop: loop_label: while condition loop statements end loop loop_label.
end loop Loop2. end process. Loop2: while B >= (A * A) loop B := B .Example P1 : process variable B : Integer := 1. . wait. end loop Loop1.A. begin Loop1: for A in 1 to 10 loop B := 20.
± exit loop_label when condition. end loop Loop1. end process. . B := 20. B : Integer :=0. P1 : process variable A. begin Loop1 :loop A := A + 1.Exitsequential statement closely associated Statement Exit statement is a with loops and causes the loop to be exited Exit statement has two general forms : ± exit loop_label. exit Loop1 when A = 20.
if var1 = var2 then execution jumps to the end of the loop.e last statement k := k + 1. k := k + 1. null. and then loop execution resumes with else new value of j.Next Statement Next statement is used to advance control to the next iteration of the loop General Form is : next loop_label when condition. is not elsif var1 < var2 executed. Example : for j in 1 to 10 loop When next statement is executed. Loop identifier j increments var1 := var1 + 1. next. . end if. end loop. i.
. Error and Failure ± If no message is given the default message is ³Assertion Violation´. ± When the condition is FALSE the message is sent to system output with an indication of the severity of the message ± The severity levels are Note. The default level is Error Example assert (A = B) report ³A is not equal to B´ severity Error.Assertion Statement The assertion statement has the syntax assert condition report message severity level. Warning.
Concurrent Signal Assignment A concurrent signal assignment statement represents an equivalent process that assigns values to signals Simple example of concurrent signal assignment is target_sig <= source_sig after delay_period. It is one of the primary mechanisms for modeling the data-flow behavior of an entity There are two forms of concurrent signal assignment : 1) conditional signal assignment 2) selected signal assignment .
end arch_sub. in2) begin Out1 <= In1 . .Example architecture arch_sub of sub is begin process (in1.In2 after Delay. end process.
. Signal Assignment is done when condition is true. waveformN-1 when conditionN-1 else waveformN.Conditional Signal Assignment This is a special form of concurrent signal assignment. General Form is: target <= options waveform1 when condition1 else . The behavior is similar to that of an if statement in a process statement .
end Conditional. architecture ConditionalEq of AND_gate is begin process(A. else Y <= transport µ0¶ after Delay.Example architecture Conditional of AND_gate is begin Y <= transport µ1¶ after Delay when A=µ1¶ and B=µ1¶ else µ0¶ after Delay. .B) begin if A=µ1¶ and B=µ1¶ then Y <= transport µ1¶ after Delay. end process. end ConditionalEq.
. .Selected Signal Assignment Selected Signal Assignment behaves very much like the case statement in a process statement General Form is: with expression select target <= options waveform1 when choices1. waveformN when choicesN. .
package body gate is procedure Or_gate(signal In1. end gate. In2 : bit. signal Out1 : out bit).A Package with a procedure modeling the functionality of an OR gate package gate is procedure Or_gate(signal In1. signal Out1 : out bit) is begin Out1 <= In1 or In2.Complete Example Example 1 -. end Or_gate. In2 : bit. end gate. .
Behavioral Description of a Half Adder entity Half_adder is generic ( AB_to_sum : TIME := 0 ns. port ( A : in bit.Half Adder Example 2 -. Sum : out bit. Carry : out bit ). . end Half_adder. AB_to_carry : TIME := 0 ns ). B : in bit.
Carry <= A and B after AB_to_carry. wait on A. .) architecture Behavioral of Half_adder is begin process begin Sum <= A xor B after AB_to_sum. end process.B. end Behavioral.Half Adder (contd.
-. Carry_in : in bit. . B : in bit.all.Structural Description of a Full Adder that instantiates Half Adder and Uses procedure Or_gate from the package gate.gate. end Full_adder. Sum : out bit. Carry_out : out bit ).Full Adder Example 2 -.use the Package gate entity Full_adder is port ( A : in bit. use WORK.
end component. AB_to_carry : TIME := 0 ns ).Full Adder (contd. port ( A : in bit. Carry : out bit ).Half_adder(behavioral).) architecture structural of Full_adder is component Half_adder generic ( AB_to_sum : TIME := 0 ns. Sum : out bit. . for all : Half_adder use entity work. B : in bit.
Temp_sum. Temp_carry1).) signal Temp_sum : bit. U1 : Half_adder generic map (5 ns. B => Carry_in. Carry_out). Carry => Temp_carry2). 5 ns) port map (A. signal Temp_carry1 : bit.Full Adder (contd. B. end structural. signal Temp_carry2 : bit. begin U0 : Half_adder generic map (5 ns. Temp_carry2. U3 : Or_gate ( Temp_carry1. . 5 ns) port map (A => Temp_sum. Sum => Sum.
library testpackage.all.Component declaration for Full Adder port ( A : in bit. entity fa_test is -.all. end component. B : in bit.textio. Carry_in : in bit. for all : Half_adder use entity work. Sum : out bit.all. Carry_out : out bit ). use STD.Full_adder(Structural .standard. use testpackage. architecture bench of fa_test is component Full_adder -.Entity for the test bench end fa_test.testpackage.Test Bench library STD. use STD.
Carry_out : bit. begin rando := 1. Carry_in : bit. file dataout : text is out "data. signal temp : bit_vector(0 to 31). Carry_in <= temp(29). Carry_in. . signal Sum. B. B.out". begin a1: Full_adder port map ( A. Sum. A <= temp(31). B <= temp(30). variable rando : integer. Carry_out). a2: process variable sttr : line.) signal A.Test Bench (contd.
write(sttr. string('(" Sum = ")).Test Bench (contd. write(sttr. wait. write(sttr. B).) for i in 0 to 40 loop temp <= int2vec(rando). rando := (rando * 3)/2 +1. string('(" Carry_in = ")). end bench. wait for 0 ns. sttr). write(sttr. write(sttr. write(sttr. . Sum). string('(" B = ")). end process. write(sttr. write(sttr. end loop. writeline (dataout. Carry_in). wait for 1 ms. string('(" Carry_out = ")). write(sttr. A). string('(" A = ")). write(sttr. Carry_out).
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