Microprocessor System Design Input / Output Peripheral Interfacing

Omid Fatemi (omid@fatemi.net)

University of Tehran 1

Outline

‡ Peripheral devices
± Input devices ± Output devices

‡ 8 bit / 16-bit IO ‡ Simple Input device - interfacing switches ‡ Simple Output device - interfacing LEDs ‡ 8255 PPI ‡ 8255 modes ‡ 16-bit data bus to 8-bit peripherals or memory devices
University of Tehran 2

Peripheral

‡ is an input and/or output device ‡ like a memory chip, it is mapped to a certain location (called the port address) ‡ unlike a memory chip, a peripheral is usually mapped to a single location

University of Tehran 3

al University of Tehran 4 . al ‡ You can write to an output device using the command out dx. you can write to an output device ‡ You can write to a memory chip using the command mov [bx].Output Device ‡ like a memory chip.

you can read from an input device ‡ You can read from a memory chip using the command mov al. dx University of Tehran 5 .Input Device ‡ like a memory chip. [bx] ‡ You can read from an input device using the command in al.

peripheral ‡ Same instruction vs.Memory mapped vs. independent ‡ More IO ports vs. independent instruction ‡ Entire address bus vs. 65536 ports ‡ More commands and operations ‡ Uses memory space University of Tehran 6 . part of address bus ‡ Same control signals vs.

Two formats for IN / OUT Format 1 ‡ IN AL. AL ‡ Example: ± BACK: IN AL.port# IN AL. 100 JNZ BACK Format 2 ‡ MOV DX. port# Or ‡ OUT port#.22H CMP AL. DX Or ‡ MOV DX. port# OUT DX. AL University of Tehran 7 .

648H OUT DX. AX . IOW Setup time Address (649) and ALE High byte (76). 648H OUT DX.AX = 76A9H ‡ Address bus and ALE ‡ Word (76A9).8bit vs 16bit IO ‡ 8088 case: ‡ MOV DX. IOW Setup time ‡ 8086 case: ‡ MOV DX. AX .AX = 76A9H ‡ ‡ ‡ ‡ ‡ ‡ Address bus and ALE Low byte (A9). IOW ‡ Setup time University of Tehran 8 .

Creating a Simple Output Device ‡ Use 8-LED¶s University of Tehran 9 .

55 out dx. al : : : University of Tehran 10 .Use 8 LED¶s A19 A18 : A0 D7 D6 D5 D4 D3 D2 D1 D0 8088 Minimum Mode IOR IOW : mov al.

Creating a Simple Output Device ‡ Use 8-LED¶s ‡ Use a chip and an address decoder such that the LED¶s will respond only to the command out and a specific address (let¶s assume that the address is F000) University of Tehran 11 .

F000 out dx. 55 mov dx.Use of 74LS245 and Address Decoder A19 A18 : A0 D7 D6 D5 D4 D3 D2 D1 D0 B0 A0 B1 A1 B2 A2 B3 A3 B4 A4 74LS245 B5 A5 B6 A6 B7 A7 E IOR IOW DIR 5V 8088 Minimum Mode A A A A A A A A A A A A A A A A IOW 1111119876543210 543210 : mov al. al : University of Tehran 12 .

Creating a Simple Output Device ‡ ‡ ‡ ‡ Use 8-LED¶s Loses the data Solution? Use a chip and an address decoder such that the LED¶s will not only respond to the command out and a specific address (let¶s assume that the address is F000) but will also latch the data University of Tehran 13 .

55 mov dx.Use of 74LS373 and Address Decoder A19 A18 : A0 D7 D6 D5 D4 D3 D2 D1 D0 Q0 D0 Q1 D1 Q2 D2 Q3 D3 Q4 D4 74LS373 Q5 D5 Q6 D6 Q7 D7 LE IOR IOW OE 8088 Minimum Mode A A A A A A A A A A A A A A A A IOW 1111119876543210 543210 : mov al. al : University of Tehran 14 . F000 out dx.

Creating a Simple Input Device ‡ Use 8-Switches (keys) ‡ Use a chip and an address decoder such that the keys will be read only to the command in and a specific address (let¶s assume that the address is F000) ‡ How to interface a switch to computer? University of Tehran 15 .

F000 in al. dx : University of Tehran 16 Same address for input and output? .Use of 74LS245 and Address Decoder A19 A18 : A0 D7 D6 D5 D4 D3 D2 D1 D0 B0 A0 B1 A1 B2 A2 B3 A3 B4 A4 74LS245 B5 A5 B6 A6 B7 A7 E IOR IOW DIR 5V 8088 Minimum Mode A A A A A A A A A A A A A A A A IOR 1111119876543210 543210 : mov dx.

How do you know if a user has pressed a button? ‡ By Polling ‡ By Interrupt University of Tehran 17 .

FF L1 : : University of Tehran 18 . dx al.Polling A19 A18 : A0 D7 D6 D5 D4 D3 D2 A0 A1 A2 A3 A4 A6 A7 E IOR IOW B0 B1 B2 B3 B4 B6 B7 DI 5V 74LS245 B5 A5 8088 Mi i Mode D1 D0 L1: A A A A A A A A A A A A A A A A IOR 1111119876543210 543210 mov in cmp je dx. F000 al.

AL ? University of Tehran 19 .Output Port Design T1 ± T4 of OUT 99H.

5FH ? University of Tehran 20 .Input Port Design T1 ± T4 of IN AL.

8255 PPI University of Tehran 21 .

Control word University of Tehran 22 .

Modes of Operation ‡ Mode 0 ± simple input or output ‡ Mode 1 ± input or output with handshaking ‡ Mode 2 ± bideirectional IO with handshaking University of Tehran 23 .

Port addresses University of Tehran 24 .Example .

Solution University of Tehran 25 .

Example ± Programming 8255 University of Tehran 26 .

Solution University of Tehran 27 .

BSR mode University of Tehran 28 .

AL ‡ B) ± MOV AL. 0xxx1100 OUT 93H.Example for BSR ‡ Program 8255 for the following ± A) set PC2 to high ± B) Use PC6 to generate a square wave of 66% duty cycle ‡ Solution ‡ A) ± MOV AL. 00000101B OUT 93H. AL CALL Delay CALL Delay MOV AL. 0xxx1101 OUT 93H. AL CALL Delay JMP AGAIN University of Tehran 29 .

MODE 1 Output Operation University of Tehran 30 .

Output with handshake ‡ #OBFa : ± CPU has written a byte ‡ #ACKa: ± Data has been picked up by receiving device ‡ INTRa: ± After rising edge of #ACKa ‡ INTEa (interrupt enable) ± Internal flipflop ± Controlled by PC6 University of Tehran 31 .

MODE 1 Timing (output) University of Tehran 32 .

Interrupt vs. Polling ‡ CPU is interrupted whenever necessary ‡ CPU can serve many devices ‡ Require more hardware University of Tehran 33 .

Using status to Poll University of Tehran 34 .

Solution University of Tehran 35 .

MODE 1 Input Operation University of Tehran 36 .

Input with handshake ‡ #STB (in): ± Device provides data to an input port ‡ IBF (out): ± Data has been latched by 8255 ‡ INTR (out): ± After activation of IBF ‡ INTE (interrupt enable) ± Internal flip-flop ± Controlled by PC4 and PC2 University of Tehran 37 .

MODE 1 Timing (input) University of Tehran 38 .

MODE 2 Operation University of Tehran 39 .

IBM PC IO MAP University of Tehran 40 .

Decoding by 74138 University of Tehran 41 .

8255 Address in PC University of Tehran 42 .

99H OUT 63.Use of 8255 ports in PC MOV AL. AL University of Tehran 43 .

Pentium. III. IV (64/36) ± PPC 60x (32 or 64/32) ‡ All 80x86 processors use a 16-bit address for i/o University of Tehran 44 . II. PII (64/32) ± Pentium Pro.80x86 family ‡ 16-bit Processors ± 8088 (8-bit data / 20-bit address) ± 8086/186 (16-bit data / 20-bit address) ± 80286 (16-bit data / 24-bit address) ‡ 32-bit Processors ± 80386 (16/24 or 32/32 common) ± 80486 (32/32).

8 And 16 bit Organizations ‡ 8088 ± Data is organized into byte widths ± The 1MB memory is organized as 1M x 8-bits ‡ 8086/80186 ± Data is organized into word widths ± The 1MB memory is organized as 512kB x 16-bits ‡ 80286/80386SX ± Data is organized into word widths ± The 16MB memory is organized as 8MB x 16-bits University of Tehran 45 .

actual address bus is 36 bits) University of Tehran 46 .32 and 64 bit Organizations ‡ ‡ 80386DX/80486 ± ± Data is organized into double word widths ± ± The 4GB memory is organized as 1GB x 32-bits ‡ ‡ Pentium Pro/Pentium 1-4 ± ± Data is organized into quad word widths ± ± The 4GB memory is organized as 512MB x64-bits ‡ (on P2-4.

AX #513. with the value 513 .513 MOV [4].W MOVE.Little Endian / Big Endian for the 68000: MOVE. D0 D0.W for the 80x86: MOV AX.4 . store AX into memory 4 University of Tehran 47 . load AX (16 bits). move value 513 into the lower 16 bits of D0 . store the lower word of D0 into memory 4 .

‡ 1M byte of memory is organized as: ‡ 512K * 16 bit ‡ The memory is word-aligned ‡ Access to even addresses is aligned and simple ‡ Example: 0102H and 0304H stored in [4H] What happens on mov AX.[5]? Motorola family of the MC680x0 forbids non-aligned access University of Tehran 48 .[4]? What happens on mov AX.Memory Alignment in 16-bit Micro ‡ We have 16-bit data bus ‡ Why not use it for memory access.

Memory Bank Select ‡ 8086/186/286/386SX has 16 Data Lines D15-D0 ‡ 6264 Only has 8 I/O7 ± I/O0 ‡ Must Use a ³Memory Bank´ ± 1 SRAM for Storing Bytes with ³Even Addresses´ (« 0 2 ) ± 1 SRAM for Storing Bytes with ³Odd´ Addresses´ (« 1 3 ) ‡ 8086 has BHE Control Signal ± (Bank High Enable) ‡ Can Use Combination of A0 and BHE to Determine Type of Access ± ± ± ± ± BHE 0 0 1 1 A0 0 1 0 1 Access Type 1 word (16-bits) Odd Byte (D15-D8) Even Byte (D7-D0) No Access University of Tehran 49 .

Interfacing two 512KB Memory to the 8088 Microprocessor (review) AX BX CX DX CS SS DS ES BP SP SI DI IP 3F1C 0023 0000 FCA1 XXXX XXXX 2000 XXXX XXXX XXXX XXXX XXXX XXXX A18 : A0 D7 : D0 RD WR CS 7FFFF 7FFFE 7FFFD : 20023 20022 20021 20020 : 00001 00000 12 98 2C : 33 45 92 A3 : D4 97 MEMR MEMW RD WR CS A19 A18 : A0 D7 : D0 A18 : A0 D7 : D0 7FFFF 7FFFE 7FFFD : 20023 20022 20021 20020 : 00001 00000 36 25 19 : 13 7D 12 29 : 95 23 University of Tehran 50 .

Interfacing two 512KB Memory to the 8086 Microprocessor How to connect data lines? How about chip select? What to connect address lines? AX BX CX DX CS SS DS ES BP SP SI DI IP 3F1C 0023 0000 FCA1 XXXX XXXX 4000 XXXX XXXX XXXX XXXX XXXX XXXX D15 : D8 A18 : A0 D7 : D0 RD WR BHE# CS 7FFFF 7FFFE 7FFFD : 20023 20022 20021 20020 : 00001 00000 12 98 2C : 33 45 92 A3 3F : D4 97 MEMR MEMW RD WR CS A0 A19 : A1 D7 : D0 A18 : A0 D7 : D0 7FFFF 7FFFE 7FFFD : 20023 20022 20021 20020 : 00001 00000 36 25 19 : 13 7D 12 1C 29 : 95 23 MOV [0040]. AL? MOV [0041]. AX? University of Tehran 51 . AH? MOV [0040].

Decoding Circuit with Bank Select University of Tehran 52 .

Even address for one and odd addresses for other OUT port#. AX outputs to both of them!!! University of Tehran 53 .Interfacing 8-bit Peripherals to 16-bit Data Bus ‡ The Problem? ‡ Solutions: ± 1) two separate PPI devices.

Interfacing 8-bit Peripherals to 16-bit Data Bus (2) ‡ Solutions: ± 2) Hi / Lo byte copier. ± Outputting to odd-addressed ports: » Hi/Lo byte copier copies data from D8-D15 to D0-D7 ± Inputting a byte form odd-addressed ports: » Hi/Lo byte copier copies data from D0-D7 to D8-D15 ± The logic now resides in chipsets. University of Tehran 54 .

Hi/Lo Copier in PC University of Tehran 55 .

ISA Bus expansion slot ‡ Only 16-bit (even 32-bit or higher data bus) ‡ Speed is limited to 8MHz University of Tehran 56 .

Linear Select Address Decoding What is the address range and aliases? University of Tehran 57 .

Buffering Selected IO Address Range

Range of addresses? Blocking others.

University of Tehran 58

PC Interface Card

‡ From BitPardaz

University of Tehran 59

I/O Programming with C and BASIC
Assembly OUT port#, AL IN AL, port# OUT DX, AX IN AX, DX Microsoft C outp (port#, byte) var=inp(port #) Borland C BASIC

ouportb(port Out port#, #, byte) byte var=inportb( port#) Var = INP (port#) Out port#, word ??

Outpw(port#, Outport(port word) #, word)

word=inpw(p word=inport( Var = INP ort#) port#) (port#)??
University of Tehran 60

Example University of Tehran 61 .

it changes the direction of the movement.Example Polling program? ‡ The program makes a ³running LED´ effect (initially moving from down to up). University of Tehran 62 . When the highest button is pressed. Every time the lowest button is pressed. the program terminates.

A19 A18 : A0 D7 D6 D5 D4 D3 D2 D1 D0 5V The Circuit 8088 Minimum Mode B0 A0 B1 A1 B2 A2 B3 A3 B4 A4 74LS245 B5 A5 B6 A6 B7 A7 E DIR D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 74LS373 D5 Q5 D6 Q6 D7 Q7 A A A A A A A A A A A A A A A A IOR 1111119876543210 543210 LE OE IOR IOW University of Tehran 63 AAAAAAAAAAAAAAAAIOW 1111119876543210 543210 .

L1 F000 00 01 al FFFF L4: mov bl. L1 L4 al. dx. jmp L6 test al. cmp al.Trace what the program does: mov mov mov out mov dec jnz cmp jne rol cmp jne jmp ror cmp jne dx. al. in al. jz L7 mov al. al. jmp L1 al dx FF 01 FF 80 bl L1: L2: 00 L5: 1 01 L6: L7: 1 80 L3: University of Tehran 64 . cx L2 ah. L3 al. jnz L5 xor ah. je L6 test al. ah. al. cx.

dx instruction is executed ‡ the microprocessor will not know that the user has pressed the button University of Tehran 65 .What¶s the problem with polling in the sample program? ‡ Running LED takes time ‡ User might remove his/her finger from the switch ‡ before the in al.

1 cmp al. al mov cx. F000 mov ah. cmp al. je L6 test al.Problem with Polling mov dx. jz L7 mov al. jnz L5 xor ah. 01 dx. jmp L1 al dx FF 01 FF 80 bl L1: out L2: dec L5: L6: L7: L3: ror University of Tehran 66 . 80 jne L1 L4: mov bl. jmp L6 test al. FFFF cx jnz L2 cmp ah. 01 jne L1 jmp L4 al. 00 mov al. 00 jne L3 rol al. 1 cmp al. in al.

‡ The peripheral will interrupt the processor when data is available University of Tehran 67 .Interrupt ‡ The microprocessor does not check if data is available.

I¶ll check the bucket every 5 minutes to see if it is already full so that I can transfer the content of the bucket to the drum.Polling vs. Input Memory Device QP POLLING University of Tehran 68 . Interrupt instruction While studying.

Interrupt instruction I¶ll just study. I can then transfer the content of the bucket to the drum. When the speaker starts playing music it means that the bucket is full. Input Memory Device Interrupt request QP INTERRUPT University of Tehran 69 .Polling vs.

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