Static Rams are composed of memory cells that reuse the FF used in processor register. static and dynamic.SEMICONDUCTOR MEMORY Semiconductor memories fall under two categories. Difference between static & dynamic RAM are the methods used to address the cell & transfer data to or from them Difference between static & dynamic RAM are the methods used to address the cell & transfer data to or from them .

RAM UNIT ADDRESS DECODER INTERNAL SIGNAL CONTROL LINES STORAGE CELL UNIT ADDRESS REGISTER READ DRIVES ADDRESS BUS TIMING AND CONTROL UNIT R/W R/W ADDRESS BUS .

RAM CELL ADDRESS LINES MEMORY CELL R/W CONTROL LINES DATA LINES .

these circuits sense. Cells in each column are connected to a SENSE/WRITE circuit by two bit lines During a Read operation. During a Write operation Sense/write circuits receive i/p information and store in cells of selected word. This is driven by the address decoder on the chip. or read the information stored in the cells selected by a word line and transmit this information to the output data lines. Each row of cells constitutes a memory word and all cells of a row are connected to a common line referred to as the word line.INTERNAL ORGANIZATION OF HIPS EMORY Memory cell are usually organized in the form of an array. .in which each cell is capable of storing one bit of information.

ORGANI ATION OF BIT CELL IN A MEMORY W0 C I A0 A1 W1 A2 ADDRESS A3 DECODER MEMORY CELLS MEMORY CELLS W15 ORGANISATION OF BIT CELL IN MEMORY CHIP SENSE WIRE CIRCUIT B1 SENSE/ CIRCUIT SENSE WIRE CIRCUIT B2 SENSE CIRCUIT SENSE WIRE CIRCUIT B3 R/ CS .

.STATIC MEMORY Here a small memory chip consisting of 16 words of 8bits each which is 16*8 organization  the data i/p & o/p of each sense/write circuit are connected to a single bi-directional data line connected to the data bus of a computer.  memory stores 128 bits & requires 14 external connections for address & control line &two lines for power supply & ground connections.

STATIC RAM CELL CMOS CELLL .

.Asynchronous DRAMS Synchronous DRAMS Dynamic RAM are less expensive RAM·s that contains cells that do not retain their state indefinitely.

BIT LINE BIT LINES WORD LINE WORD LINE T T C C .

INTERNAL ORGANIZATION OF A 2M*8 DYNAMIC MEMORY CHIP RAS ROW ADDRESS LATCH ROW DECODER 4096*(512*8) CELL ARRAY SENSE/WRITE CIRCUIT CS R/W CAS COLUMN ADDRESS LATCH COLUMN DECODER D7 D0 .

capacitor begins to discharge.Here information is stored in dynamic memory cell in the form of a charge on a capacitor and this charge can be maintained for only tens of milliseconds. information stored in cell can be retrieved correctly only if it leads before the charge on capacitor drops below some threshold value. Content of the cell must be periodically refreshed by restoring the capacitor charge to full value. . A DRAM cell diagram To store information in DRAM cell . transistor T is turned on & voltage is applied to the bit line. This is due to the capacitor·s leakage resistance . This charges the capacitor After transistor turned off.

If capacitor charge is above the threshold value. Then READ operation is initiated. it representsvalue 1 & sense amplifier drives the bit line to full voltage & refreshes the capacitor During a READ or WRITE operation the row address is applied first & is loaded into the row address latch in response to a signal pulse on the i/p of chip. Then column address is applied toaddress pin and loaded into the column address latch under control of column address signal.SENSE amplifier does the job of detecting whether the charge is above or below the threshold value. Information in latch is decoded & bit cell is selected & the data in cell will be available on data line. .in which all cells on selected rows are read & refreshed.

A refresh circuit in DRAM chips refreshes each cell periodically Timing of memory device is controlled asynchronously. A specialized memory controller circuit provides necessary control signals that govern thetiming. . Processor takes into account the delay in response of memory & is referred to as asynchronous DRAMS.

SYNC RONOUS DRAMS .

Synchronous DRAM (SDRAM) ‡ Access is synchronized to an external clock ‡ The processor/master issues the instruction and address information to the DRAM ‡ DRAM responds after a set number of clock cycles ‡ The processor/master does not have to wait ² can do other tasks while the SDRAM is processing the request ‡ SDRAM employs a burst mode using a mode register to set up a stream of data to be synchronously fed onto the bus ‡ DDR-SDRAM. allows data to be sent twice per clock cycle (leading and trailing edge) . double data rate SDRAM.

ADVANTAGES Cache DRAM Integrates a small SRAM cache (16 Kb) onto a DRAM chip ‡ Used as a true cache consisting of a number of 64 bit lines ‡ Used as a buffer to support the serial access of a block of data .

V & MAHADARSHINI.MAHESWARI.G .

Sign up to vote on this title
UsefulNot useful