This action might not be possible to undo. Are you sure you want to continue?

)

and A Kuehlmann (Cadence)

1

Logic Synthesis Logic Synthesis

Boolean Functions and Circuits Boolean Functions and Circuits

2

Remember: What is Logic Synthesis? Remember: What is Logic Synthesis?

Given: Finite-State Machine F(X,Y,Z, , ) where:

D D

XX YY

P

H

P H

X: Input alphabet

Y: Output alphabet

Z: Set of internal states

: X x Z Z (next state function)

: X x Z Y (output function)

P

H

Target: Circuit C(G, W) where:

G: set of circuit components g {Boolean gates,

flip-flops, etc}

W: set of wires connecting G

These are Boolean Functions!!

3

The Boolean Space B The Boolean Space B

n n

B = { 0,1}

B

2

= {0,1} X {0,1} = {00, 01, 10, 11}

BB

0 0

BB

1 1

BB

2 2

BB

3 3

BB

4 4

Karnaugh Maps: Boolean Cubes:

4

Boolean Functions Boolean Functions

p

!

!

! ! ! ! !

2

2

2 2

2 2

Boolean Function: ( ) :

{ , }

( , ,..., ) ;

- , ,... are

- , , , ,... are

- essentiall : a s eac verte of to or

E a l

vari

e:

{(( , ), ),(( ,

a les

literals

n

n

n i

n

f x B B

B

x x x x B x B

x x

x x x x

f B

f x x x x

! ! ! !

1 2 1 2

),1),

(( 1, ), 1),(( 1, 1), )} x x x x 1

x

2

x

1

1

x

2

x

1

5

Boolean Functions Boolean Functions

! ! !

! ! !

! |

! ! |

!

1 1

1 0

1

0 1

- The of is { | ( ) 1} (1)

- The of is { | ( ) 0} (0)

- if , is the i.e. 1

- if ( ), is

Onset

Offset

tautology.

not satisfyabl , i.e. 0

- if ( ) ( ) , t

e

hen a

n

n

n

f x f x f f

f x f x f f

f f f

f f f f

f x g x for all x f

1

nd

- we say

are equi a

instea

le

nt

d of

g

f f

- literals A is a aria le or its ne ation and re resents a lo i l fun tion iteral x x

Literal x

1

re resents the lo i fun tion f where f = {x| x

1

= 1}

Literal x

1

re resents the lo i fun tion where = {x| x

1

= 0}

x

3

x

1

x

2

x

1

x

2

x

3

f = x

1

f = x

1

6

Set of Boolean Functions Set of Boolean Functions

There are 2

n

ertices in input space B

n

There are 2

2

n

distinct logic functions.

± ach subset of ertices is a distinct logic function:

f

B

n

x

1

x

2

x

3

0 0 0 1

0 0 1 0

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 0

x

1

x

2

x

3

Truth Table or Function table:

7

Boolean Operations Boolean Operations - -

ND, OR, COMPL M NT AND, OR, COMPL M NT

Gi en two Boolean functions:

f : B

n

÷B

g : B

n

÷B

The AND operation h = f g is defined as

h = {x | f(x)=1 · g(x)=1}

The OR operation h = f + g is defined as

h = {x | f(x)=1 v g(x)=1}

The COMPL M NT operation h = ^f is defined as

h = {x | f(x) = 0}

8

Cofactor and Quantification Cofactor and Quantification

Gi en a Boolean function:

f : B

n

÷B, with the input ariable (x

1

,x

2

,«,x

i

,«,x

n

)

The positi e cofactor h = f

xi

is defined as

h = {x | f(x

1

,x

2

,«,1,«,x

n

)=1}

The negati e cofactor h = f

xi

is defined as

h = {x | f(x

1

,x

2

,«,0,«,x

n

)=1}

The existential quantification of ariable x

i

h = n x

i

. f is defined as

h = {x | f(x

1

,x

2

,«,0,«,x

n

)=1 v f(x

1

,x

2

,«,1,«,x

n

)=1}

The uni ersal quantification of ariable x

i

h = V x

i

. f is defined as

h = {x | f(x

1

,x

2

,«,0,«,x

n

)=1 · f(x

1

,x

2

,«,1,«,x

n

)=1}

9

Representation of Boolean Functions Representation of Boolean Functions

We need representations for Boolean Functions for two

reasons:

± to represent and manipulate the actual circuit we are ³synthesizing´

± as mechanism to do efficient Boolean reasoning

Forms to represent Boolean Functions

± Truth table

± List of cubes (Sum of Products, Disjuncti e Normal Form (DNF))

± List of conjuncts (Product of Sums, Conjuncti e Normal Form

(CNF))

± Boolean formula

± Binary Decision Tree, Binary Decision Diagram

± Circuit (network of Boolean primiti es)

10

Truth Table Truth Table

Truth table (Function Table): Truth table (Function Table):

The truth table of a function f : B

n

÷B is a tabulation of its alue at

each of the 2

n

ertices of B

n

.

In other words the truth table lists all mintems

xample: f = abcd + abcd + abcd +

abcd + abcd + abcd +

abcd + abcd

The truth table representation is

- intractable for large n

- canonical

Canonical means that if two functions are the same, then the

canonical representations of each are isomorphic.

abcd f

0 0000 0

1 0001 1

2 0010 0

3 0011 1

4 0100 0

5 0101 1

6 0110 0

7 0111 0

abcd f

8 1000 0

9 1001 1

10 1010 0

11 1011 1

12 1100 0

13 1101 1

14 1110 1

15 1111 1

11

Boolean Formula Boolean Formula

A Boolean formula is defined as an expression with the following

syntax:

formula ::= µ(µ formula µ)¶

| < ariable>

| formula ³+´ formula (OR operator)

| formula ³´ formula (AND operator)

| ^ formula (complement)

xample:

f = (x

1

x

2

) + (x

3

) + ^^(x

4

(^x

1

))

typically the ³´ is omitted and the µ(µ and µ^¶ are simply reduced by priority,

e.g.

f = x

1

x

2

+ x

3

+ x

4

^x

1

12

Cubes Cubes

A cube is defined as the AND of a set of literal functions (³conjunction´

of literals).

xample:

C = x

1

x

2

x

3

represents the following function

f = (x

1

=1)(x

2

=0)(x

3

=1)

x

1

x

2

x

3

c = x

1

x

1

x

2

x

3

f = x

1

x

2

x

1

x

2

x

3

f = x

1

x

2

x

3

13

Cubes Cubes

If C f, C a cube, then C is an implicant of f.

If C B

n

, and C has k literals, then |C| co ers 2

n-k

ertices.

xample:

C = xy B

3

k = 2 , n = 3 => |C| = 2 = 2

3-2.

C = {100, 101}

An implicant with n literals is a minterm.

14

List of Cubes List of Cubes

Sum of Products: Sum of Products:

A function can be represented by a sum of cubes (products):

f = ab + ac + bc

Since each cube is a product of literals, this is a ³sum of products´

(SOP) representation

A SOP can be thought of as a set of cubes F

F = {ab, ac, bc}

A set of cubes that represents f is called a co er of f.

F

1

={ab, ac, bc} and F

2

={abc,abc,abc,abc}

are co ers of

f = ab + ac + bc.

15

Binary Decision Diagram (BDD) Binary Decision Diagram (BDD)

f = ab+a¶c+a¶bd

1

0

c

a

b b

c c

d

0 1

c+bd

b

root

node

c+d

d

Graph representation of a Boolean function f

- ertices represent decision nodes for ariables

- two children represent the two subfunctions

f(x = 0) and f(x = 1) (cofactors)

- restrictions on ordering and reduction rules

can make a BDD representation canonical

16

Boolean Circuits Boolean Circuits

Used for two main purposes

± as representation for Boolean reasoning engine

± as target structure for logic implementation which gets restructured

in a series of logic synthesis steps until result is acceptable

fficient representation for most Boolean problems we ha e in CAD

± memory complexity is same as the size of circuits we are actually

building

Close to input representation and output representation in logic

synthesis

17

Definitions Definitions

Definition:

A Boolean circuit is a directed graph C(G,N) where G are the gates and

N G-G is the set of directed edges (nets) connecting the gates.

Some of the ertices are designated:

Inputs: I G

Outputs: O G, I · O =

ach gate g is assigned a Boolean function f

g

which computes the

output of the gate in terms of its inputs.

18

Definitions Definitions

The fanin FI(g) of a gate g are all predecessor ertices of g:

FI(g) = {g¶ | (g¶,g) N}

The fanout FO(g) of a gate g are all successor ertices of g:

FO(g) = {g¶ | (g,g¶) N}

The cone CON (g) of a gate g is the transiti e fanin of g and g itself.

The support SUPPORT(g) of a gate g are all inputs in its cone:

SUPPORT(g) = CON (g) · I

19

Example Example

I

O

6

FI(6) = {2,4}

FO(6) = {7,9}

CONE(6) = {1,2,4,6}

SUPPORT(6) = {1,2}

1

5

3

4

7

8

9

2

20

Circuit Function Circuit Function

Circuit functions are defined recursi ely:

If G is implemented using physical gates that ha e positi e (bounded)

delays for their e aluation, the computation of h

g

depends in general on

those delays.

Definition:

A circuit C is called combinational if for each input assignment of C for

t÷· the e aluation of h

g

for all outputs is independent of the internal

state of C.

Proposition:

A circuit C is combinational if it is acyclic.

if

( ,..., ), ,..., ( ) otherwise

i

i j k

i i

g

g g g j k i

x g I

h

f h h g g FI g

®

±

!

¯

±

°

21

Cyclic Circuits Cyclic Circuits

Definition:

A circuit C is called cyclic if it contains at least one loop of the form:

((g,g

1

),(g

1

,g

2

),«,(g

n-1

,g

n

),(g

n

,g)).

In order to check whether the loop is combinational or sequential, we

need to deri e the loop function h

loop

by cutting the loop at gate g

...

...

g

22

Cyclic Circuits Cyclic Circuits

...

...

...

g

g

h

loop

( , ) ( ' ,..., ' ), ,..., ( )

if

' if

( ' ,..., ' ),

j k

i

i j k

loop g g g j k

i i

g i

g g g

h h x v f h h g g FI g

x g I

h v g g

f h h g

! !

! !

,..., ( ) otherwise

j k i

g FI g

®

±

¯

±

°

...

23

Cyclic Circuits Cyclic Circuits

( , ) ( , ) 1

loop v loop v

h x v h x v !

h

loop

x

i

v

The following equation computes the sensiti ity of h

with respect to v:

For any solution x, h

loop

will toggle if toggles.

negati e feedback - oscillator (astable multi ibrator)

positi e feedback - flip-flop (bistable multi ibrator)

24

Cyclic Circuits Cyclic Circuits

Theorem: A circuit loop in ol ing gate g is combinational if:

Theorem: Output y of a circuit containing a loop with gate g is

combinational if:

³Either the loop is combinational or the output does not depend on

the loop alue.´

25

Circuit Representations Circuit Representations

For general circuit manipulation (e.g. synthesis):

Vertices ha e an arbitrary number of inputs and outputs

Vertices can represent any Boolean function stored in different ways,

such as:

± other circuits (hierarchical representation)

± Truth tables or cube representation (e.g. SIS)

± Boolean expressions read from a library description

± BDDs

Data structure allow ery general mechanisms for insertion and

deletion of ertices, pins (connections to ertices), and nets

± general but far too slow for Boolean reasoning

26

Circuit Representations Circuit Representations

For efficient Boolean reasoning (e.g. a SAT engine):

Circuits are non-canonical

± computational effort is in the ³checking part´ of the reasoning

engine (in contrast to BDDs)

Vertices ha e fixed number of inputs (e.g. two)

Vertex function is stored as label, well defined set of possible function

labels (e.g. OR, AND,OR)

on-the-fly compaction of circuit structure

± allows incremental, subsequent reasoning on multiple problems

27

Boolean Reasoning Engine Boolean Reasoning Engine

Engine Interface:

void INIT()

void QUIT()

Edge VAR()

Edge AND(Edge p1,

Edge p2)

Edge NOT(Edge p1)

Edge OR(Edge p1

Edge p2)

...

int SAT(Edge p1)

Engine application:

- tra erse problem data structure and build

Boolean problem using the interface

- call SAT to make decision

Engine Implementation:

...

...

...

...

External reference pointers attached

to application data structures

28

Basic Approaches Basic Approaches

Boolean reasoning engines need: Boolean reasoning engines need:

± ± a mechanism to build a data structure that represents the problem a mechanism to build a data structure that represents the problem

± ± a decision procedure to decide about SAT or UNSAT a decision procedure to decide about SAT or UNSAT

Fundamental trade Fundamental trade- -off off

± ± canonical data structure canonical data structure

data structure uniquely represents function data structure uniquely represents function

decision procedure is tri ial (e.g., just pointer comparison) decision procedure is tri ial (e.g., just pointer comparison)

example: Reduced Ordered Binary Decision Diagrams example: Reduced Ordered Binary Decision Diagrams

Problem: Size of data structure is in general exponential Problem: Size of data structure is in general exponential

± ± non non- -canonical data structure canonical data structure

systematic search for satisfying assignment systematic search for satisfying assignment

size of data structure is linear size of data structure is linear

Problem: decision may take an exponential amount of time Problem: decision may take an exponential amount of time

29

AND AND- -INVERTER Circuits INVERTER Circuits

Base data structure uses two-input AND function for ertices and

INVERTER attributes at the edges (indi idual bit)

± use De¶Morgan¶s law to con ert OR operation etc.

Hash table to identify and reuse structurally isomorphic circuits

f

g

g

f

30

Data Representation Data Representation

Vertex:

± pointers (integer indices) to left and right child and fanout ertices

± collision chain pointer

± other data

Edge:

± pointer or index into array

± one bit to represent in ersion

Global hash table holds each ertex to identify isomorphic structures

Garbage collection to regularly free un-referenced ertices

31

Data Representation Data Representation

0456

left

right

next

fanout

1345

«.

8456

«.

6423

«.

7463

«.

0

1

hash alue

left pointer

right pointer

next in collision chain

array of fanout pointers

complement bits

Constant

One Vertex

zero

one

0456

0455

0457

...

...

Hash Table

0456

left

right

next

fanout

0

0

32

Hash Table Hash Table

Algorithm HASH_LOOKUP(Edge p1, Edge p2) {

index = HASH_FUNCTION(p1,p2)

p = &hash_table[index]

while(p != NULL) {

if(p->left == p1 && p->right == p2) return p;

p = p->next;

}

return NULL;

}

Tricks:

- keep collision chain sorted by the address (or index) of p

- that reduces the search through the list by 1/2

- use memory locations (or array indices) in topological order of circuit

- that results in better cache performance

33

Basic Construction Operations Basic Construction Operations

Algorithm AND(Edge p1,Edge p2){

if(p1 == const1) return p2

if(p2 == const1) return p1

if(p1 == p2) return p1

if(p1 == ^p2) return const0

if(p1 == const0 || p2 == const0) return const0

if(RANK(p1) > RANK(p2)) SWAP(p1,p2)

if((p = HASH_LOOKUP(p1,p2)) return p

return CREATE_AND_VERTEX(p1,p2)

}

34

Basic Construction Operations Basic Construction Operations

Algorithm OR(Edge p1,Edge p2){

return (NOT(AND(NOT(p1),NOT(p2))))

}

Algorithm NOT(Edge p) {

return TOOGLE_COMPLEMENT_BIT(p)

}

35

Cofactor Operation Cofactor Operation

Algorithm POSITIVE_COFACTOR(Edge p,Edge v){

if(IS_VAR(p)) {

if(p == v) {

if(IS_INVERTED(v) == IS_INVERTED(p)) return const1

else return const0

}

else return p

}

if((c = GET_COFACTOR(p)) == NULL) {

left = POSITIVE_COFACTOR(p->left, v)

right = POSITIVE_COFACTOR(p->right, v)

c = AND(left,right)

SET_COFACTOR(p,c)

}

if(IS_INVERTED(p)) return NOT(c)

else return c

}

36

Cofactor Operation Cofactor Operation

- similar algorithm for NEGATIVE_COFACTOR

- existential and uni ersal quantification build from AND, OR and COFACTORS

Question: What is the complexity of the circuits resulting from quantification?

37

SAT and Tautology SAT and Tautology

Tautology:

± Find an assignment to the inputs that e aluate a gi en ertex to ³0´.

SAT:

± Find an assignment to the inputs that e aluate a gi en ertex to ³1´.

± Identical to Tautology on the in erted ertex

SAT on circuits is identical to the justification part in ATPG

± First half of ATPG: justify a particular circuit ertex to ³1´

± Second half of ATPG (propagate a potential change to an output)

can be easily formulated as SAT (will be co ered later)

Basic SAT algorithms:

± branch and bound algorithm as seen before

branching on the assignments of primary inputs only (Podem

algorithm)

branching on the assignments of all ertices (more efficient)

38

General Da is General Da is- -Putnam Procedure Putnam Procedure

search for consistent assignment to entire cone of requested ertex by

systematically trying all combinations (may be partial!!!)

keep a queue of ertices that remain to be justified

± pick decision ertex from the queue and case split on possible

assignments

± for each case

propagate as many implications as possible

± generate more ertices to be justified

± if conflicting assignment encountered

» undo all implications and backtrack

recur to next ertex from queue

Algorithm SAT(Edge p) {

queue = INIT_QUEUE()

if(IMPLY(p) return TRUE

return JUSTIFY(queue)

}

39

General Da is General Da is- -Putnam Procedure Putnam Procedure

Algorithm JUSTIFY(queue) {

if(QUEUE_EMPTY(queue)) return TRUE

mark = ASSIGNMENT_MARK()

v = QUEUE_NEXT(queue) // decision vertex

if(IMPLY(NOT(v->left)) {

if(JUSTIFY(queue)) return TRUE

} // conflict

UNDO_ASSIGNMENTS(mark)

if(IMPLY(v->left) {

if(JUSTIFY(queue)) return TRUE

} // conflict

UNDO_ASSIGNMENTS(mark)

return FALSE

}

40

Example Example

First case for 9:

Queue Assignments

1

6

2 5

8

7

3

4

9

9

0

1

6

2 5

8

7

3

4

9

9

0

9

9

7

4

5

1

2

0

1

1

1

1 0

1

Conflict!!

- undo all assignments

- backtrack

SAT(NOT(9))??

41

Example Example

Second case for 9:

First case for 5:

Assignments

1

6

2 5

8

7

3

4

9

5

6

0

9

7

8

5

6

0

1

0

0

0

1

Queue

1

6

2 5

8

7

3

4

9

0

9

7

8

5

6

2

3

0

1

0

0

0

1

0

Note:

- ertex 7 is justified

by 8->5->7

0

Solution cube: 1 = x, 2 = 0, 3 = 0

42

Implication Procedure Implication Procedure

Fast implication procedure is key for efficient SAT sol er!!!

± don¶t mo e into circuit parts that are not sensitized to current SAT

problem

± detect conflicts as early as possible

Table lookup implementation (27 cases):

± No implications:

± Implications:

x

x

x

x

1

x

1

x

x

0

x

0

0

1

0

0

0

0

x

0

0

1

0

0

1

1

1

0

x

x

x

0

x

0

0

x

x

x

1

x

1

1

1

x

1

43

Implication Procedure Implication Procedure

± Implications:

± Conflicts:

± Case Split:

x

1

0

1

x

0

1

1

x

1

0

x

0

1

x

1

1

0

x

x

0

0

x

1

0

0

1

0

1

1

x

0

1

1

0

1

44

Ordering of Case Splits Ordering of Case Splits

arious heuristics work differently well for particular problem classes

often depth-first heuristic good because it generates conflicts quickly

mixture of depth-first and breadth-first schedule

other heuristics:

± pick the ertex with the largest fanout

± count the polarities of the fanout separately and pick the ertex with

the highest count in either one

± run a full implication phase on all outstanding case splits and count

the number of implications one would get

some cases may already generate conflicts, the other case is

immediately implied

pick ertices that are in ol ed in small cut of the circuit

== 0?

³small cut´

45

Learning Learning

Learning is the process of adding ³shortcuts´ to the circuit structure that

a oids case splits

± static learning:

global implications are learned

± dynamic learning:

learned implications only hold in current part of the search tree

Learned implications are stores as additional network

Back to example:

± First case for ertex 9 lead to conflict

± If we were to try the same assignment again (e.g. for the next SAT call), we

would get the same conflict => merge ertex 7 with Zero- ertex

1

6

2 5

8

7

3

4

9

0

0

1

1

1

1 0

1

Zero Vertex

- if rehashing is in oked

ertex 9 is simplified and

and merged with ertex 8

46

Static Learning Static Learning

Implications that can be learned structurally from the circuit

± Example:

± Add learned structure as circuit

(( ) 0) ( ) 0) ( 0) x y x y x · | · · | |

Zero Vertex

Use hash table to find structure in circuit:

Algorithm CREATE_AND(p1,p2) {

. . . // create new vertex p

if((p¶=HASH_LOOKUP(p1,NOT(p2))) {

LEARN((p=0)&(p¶=0)(p1=0))

}

if((p¶=HASH_LOOKUP(NOT(p1),p2)) {

LEARN((p=0)&(p¶=0)(p2=0))

}

47

Back to Example Back to Example

Original second case for 9:

Assignments

1

6

2 5

8

7

3

4

9

5

6

0

9

7

8

5

6

0

1

0

0

0

1

Queue

Second case for 9 with static learning:

1

6

2 5

8

7

3

4

9

0

9

7

8

5

6

a

3

0

1

0

0

0

1

Zero Vertex

a

b

1

0

Solution cube: 1 = x, 2 = x, 3 = 0

48

Static Learning Static Learning

Socrates algorithm: based on contra-positi e:

foreach vertex v {

mark = ASSIGNMENT_MARK()

IMPLY(v)

LEARN_IMPLICATIONS(v)

UNDO_ASSIGNMENTS(mark)

IMPLY(NOT(v))

LEARN_IMPLICATIONS(NOT(v))

UNDO_ASSIGNMENTS(mark)

}

Problem: learned implications are far too many

± solution: restrict learning to non-tri ial implications

± mask redundant implications

( ) ( ) x y y x

x y

1

0

0

0

(( 0) ( 1)) (( 0) ( 1)) x y y x ! ! ! !

x y

0

1

Zero Vertex

0

0

49

Recursi e Learning Recursi e Learning

Compute set of all implications for both cases on le el i

± static implications (y=0/1)

± equi alence relations (y=z)

Intersection of both sets can be learned for le el i-1

Apply learning recursi ely until all case splits exhausted

± recursi e learning is complete but ery expensi e in practice for

le els > 2,3

± restrict learning le el to fixed number -> becomes incomplete

(( 1) ( 1) ( 0) ( 1)) ( 1) x y x y y ! ! · ! ! !

x

y

0

x

y

0

x

y

0

1

0

1

1

1

1

x

y

0

1

x

x

50

Recursi e Learning Recursi e Learning

Algorithm RECURSIVE_LEARN(int level) {

if(v = PICK_SPLITTING_VERTEX()) {

mark = ASSIGNMENT_MARK()

IMPLY(v)

IMPL1 = RECURSIVE_LEARN(level+1)

UNDO_ASSIGNMENTS(mark)

IMPLY(NOT(v))

IMPL0 = RECURSIVE_LEARN(level+1)

UNDO_ASSIGNMENTS(mark)

return IMPL1 · IMPL0

}

else { // completely justified

return IMPLICATIONS

}

}

51

Dynamic Learning Dynamic Learning

Learn implications in sub-tree of search

cannot simply add permanent structure because not globally alid

± add and remo e learned structure (expensi e)

± add the branching condition to the learned implication

of no use unless we prune the condition (conflict learning)

± use implication and assignment mechanism to assign and undo

assigns

e.g. dynamic recursi e learning with fixed recursion le el

Dynamic learning of equi alence relations (Stalmarck procedure)

± learn equi alence relations by dynamically rewriting the formula

52

Dynamic Learning Dynamic Learning

Efficient implementation of dynamic recursi e learning with le el 1:

± consider both sub-cases in parallel

± use 27- alued logic in the IMPLY routine

{level0-value ´ level1-choice1 ´ level1-choice2}

{{0,1,x} ´ {0,1,x} ´ {0,1,x}}

± automatically set learned alues for le el0 if both le el1 choices

agree

0 0

0

{x,1,0}

{x,x,1}

{1,1,1}

1

x

x

53

Conflict Conflict- -based Learning based Learning

Idea: Learn the situation under which a particular conflict

occurred and assert it to 0

imply will use this ³shortcut´ to detect similar conflict earlier

Definition:

An implication graph is a directed Graph I(G¶,D), G¶ G are the gates

of C with assigned alues

g

=x, D G- G are the edges, where each

edge (g

i

,g

j

) D reflects an implication for which an assignment of gate

g

i

lead to the assignment of gate g

j

.

0 (decision ertex)

0 (decision ertex)

1

2

3

4

0

1

1¶

2¶

3¶

4¶

Circuit:

Implication graph:

54

Conflict Conflict- -based Learning based Learning

The roots of the implication graph correspond to the decision ertices,

the leafs corresponds to the implication frontier

There is a strict implication order in the graph from the roots to the leafs

± We can completely cut the graph at any point and identical alue

assignments to the cut ertices, we result in identical implications toward

the leafs

C

1

C

2

C

n-1

C

n

(C

1

: Decision ertices)

Cut assignment (C

i

)

55

Conflict Conflict- -based Learning based Learning

If an implication leads to a conflict, any cut assignment in the

implication graph between the decision ertices and the conflict will

result in the same conflict!

(C

i

Conflict) (NOT(Conflict) NOT(C

i

))

We can learn the complement of the cut assignment as circuit

± find minimal cut in I (costs less to learn)

± find dominator ertex if exists

± restrict size of cuts to be learned, otherwise exponential blow-up

56

Non Non- -chronological Backtracking chronological Backtracking

If we learned only cuts on decision ertices, only the decision ertices

that are in the support of the conflict are needed

The conflict is fully symmetric with respect to the unrelated decision

ertices!!

± Learning the conflict would pre ent checking the symmetric parts again

BUT: It is too expensi e to learn all conflicts

Decision le els:

5

4

1

3

6

2

6

5

4

3

2

1

Decision Tree:

57

Non Non- -chronological Backtracking chronological Backtracking

We can still a oid exploring symmetric parts of the decision tree by

tracking the supporting decision ertices for all conflicts.

If no conflict of the first choice on a decision ertex depends on that ertex,

the other choice(s) will result in symmetric conflicts and their e aluation can

be skipped!!

By tracking the implications of the decision ertices we can skip

decision le els during backtrack

0

1

2

3

4

{2,4} {2,4,0}

{2,3}

{4,3} {4,0}

{2,0}

58

Modified Justify Algorithm Modified Justify Algorithm

Algorithm JUSTIFY(queue) {

...

if((decision_levels0 = IMPLY(NOT(v->left))) == ) {

if((decision_levels0 = JUSTIFY(queue)) == ) return

} // conflict

UNDO_ASSIGNMENTS(mark)

if((decision_levels1 = IMPLY(v->left)) == ) {

if((decision_levels1 = JUSTIFY(queue)) == ) return

} // conflict

UNDO_ASSIGNMENTS(mark)

decision_levels = decision_levels0 decision_levels1;

return decision_levels;

}

59

D D- -Algorithm Algorithm

In addition to controllability, we need to check obser ability of a

possible signal change at a ertex:

Two implementations:

± D-algorithm using fi e- alued logic {0,1,x,D,D}

inject D at internal ertex

expect D or D at one of the circuit outputs

± regular SAT problem based on replicated fanout structure

ertex need to be justified to 1 (0)

alue change must be obser able

at the output

60

Fi e Fi e- -Valued Implication Rules Valued Implication Rules

~

0

0

~

~

&

\ 0 ~

0 0 0 0 0 0

0 ~

0

0 0

~ 0 ~ 0 ~

**Remember: What is Logic Synthesis?
**

Given: Finite-State Machine F(X,Y,Z, P, H ) where:

X

P H

Y

D

X: Y: Z: P: H:

Input alphabet Output alphabet Set of internal states XxZ Z (next state function) XxZ Y (output function) These are Boolean Functions!!

Target: Circuit C(G, W) where: G: set of circuit components g {Boolean gates, flip-flops, etc} W: set of wires connecting G

2

**The Boolean Space B
**

B = { 0,1} B2 = {0,1} X {0,1} = {00, 01, 10, 11} Karnaugh Maps: B0 B1 B2 B3 B4

n

Boolean Cubes:

3

x . ).(( x1 ! 1. } x ! ( x . x2 .x .(( x ! .1). are literals .x . are varia les . x2 ! 1). 1 x2 x1 4 . x2 .essentiall : f E a le: (( x1 ! 1.. x 2 ! )....... x 2 ! ). )} x1 1 a s eac verte of B n to or x2 f ! {(( x ! . 1).. xi B .Boolean Functions Boolean Function: f ( x ) : B n p B B!{ . xn ) B n .. x2 . x2 ! ).. x2 .

literals A literal is a aria le or its ne a tion x x and re resents a lo i fun tion Literal x1 re resents the lo i fun tion f where f = {x| x1 = 1} Literal x1 re resents the lo i fun tion where = {x| x1 = 0} f = x1 x3 x2 x1 f = x1 x3 x2 x1 5 .if f 0 ! n .e.Boolean Functions . f is the tautology. then f and g are equi alent . i.if f 1 ! .we say f instead of f 1 .The Offset of f is { x | f ( x ) ! 0} ! f 1(0) ! f 0 . f is not satisfyabl e.e. f | 1 (f 1 ! ). i.if f ( x ) ! g ( x ) for all x .The Onset of f is { x | f ( x ) ! 1} ! f 1(1) ! f 1 . f | 0 n n .

There are 2 ± ach subset of ertices is a distinct logic function: f Bn 6 .Set of Boolean Functions Truth Table or Function table: x1x2x3 000 1 0 001 010 1 011 0 100 1 101 0 110 1 111 0 x3 x2 x1 There are 2n ertices in input space Bn n 2 distinct logic functions.

COMPL M NT ND. Gi en two Boolean functions: f : Bn p B g : Bn p B The AND operation h = f g is defined as h = {x | f(x)=1 g(x)=1} The OR operation h = f g is defined as h = {x | f(x)=1 g(x)=1} The COMPL M NT operation h = ^f is defined as h = {x | f(x) = 0} 7 . OR.Boolean Operations AND.

«.«. f is defined as h = {x | f(x1.xn) The positi e cofactor h = fxi is defined as h = {x | f(x1.x2.«.Cofactor and Quantification Gi en a Boolean function: f : Bn p B.«.xn)=1 f(x1.«.1.x2.xn)=1 f(x1.x2.1.«.xi.x2.xn)=1} The uni ersal quantification of ariable xi h = xi . with the input ariable (x1.«.x2. f is defined as h = {x | f(x1.xn)=1} 8 .«.0.«.0.«.xn)=1} The existential quantification of ariable xi h = xi .«.«.x2.1.«.«.xn)=1} The negati e cofactor h = fxi is defined as h = {x | f(x1.x2.0.

Representation of Boolean Functions We need representations for Boolean Functions for two reasons: ± to represent and manipulate the actual circuit we are ³synthesizing´ ± as mechanism to do efficient Boolean reasoning Forms to represent Boolean Functions ± Truth table ± List of cubes (Sum of Products. Disjuncti e Normal Form (DNF)) ± List of conjuncts (Product of Sums. Binary Decision Diagram ± Circuit (network of Boolean primiti es) 9 . Conjuncti e Normal Form (CNF)) ± Boolean formula ± Binary Decision Tree.

Truth Table Truth table (Function Table): The truth table of a function f : Bn p B is a tabulation of its alue at each of the 2n ertices of Bn. 10 .canonical 0 1 2 3 4 5 6 7 abcd 0000 0001 0010 0011 0100 0101 0110 0111 f 0 1 0 1 0 1 0 0 8 9 10 11 12 13 14 15 abcd 1000 1001 1010 1011 1100 1101 1110 1111 f 0 1 0 1 0 1 1 1 Canonical means that if two functions are the same.intractable for large n . then the canonical representations of each are isomorphic. In other words the truth table lists all mintems xample: f = abcd + abcd + abcd + abcd + abcd + abcd + abcd + abcd The truth table representation is .

Boolean Formula A Boolean formula is defined as an expression with the following syntax: formula ::= | | | | xample: f = (x1x2) + (x3) + ^^(x4 (^x1)) typically the ³´ is omitted and the µ(µ and µ^¶ are simply reduced by priority. f = x1x2 + x3 + x4^x1 11 µ(µ formula µ)¶ < ariable> formula ³+´ formula formula ³´ formula ^ formula (OR operator) (AND operator) (complement) .g. e.

Cubes A cube is defined as the AND of a set of literal functions (³conjunction´ of literals). xample: C = x1x2x3 represents the following function f = (x1=1)(x2=0)(x3=1) c = x1 f = x1x2 f = x1x2x3 x3 x2 x1 x3 x2 x1 x3 x2 x1 12 .

101} An implicant with n literals is a minterm. then C is an implicant of f. C a cube. n = 3 => |C| = 2 = 23-2. C = {100. then |C| co ers 2n-k ertices. xample: C = xy B3 k = 2 . and C has k literals. If C Bn.Cubes If C f. 13 .

abc. ac.List of Cubes Sum of Products: A function can be represented by a sum of cubes (products): f = ab + ac + bc Since each cube is a product of literals. bc} A set of cubes that represents f is called a co er of f. 14 . this is a ³sum of products´ (SOP) representation A SOP can be thought of as a set of cubes F F = {ab. bc} and F2={abc.abc} are co ers of f = ab + ac + bc. ac. F1={ab.abc.

ertices represent decision nodes for ariables .two children represent the two subfunctions f(x = 0) and f(x = 1) (cofactors) .Binary Decision Diagram (BDD) Graph representation of a Boolean function f .restrictions on ordering and reduction rules can make a BDD representation canonical f = ab+a¶c+a¶bd root node c+bd c c 1 d d 0 0 1 15 a b c b b c+d .

Boolean Circuits Used for two main purposes ± as representation for Boolean reasoning engine ± as target structure for logic implementation which gets restructured in a series of logic synthesis steps until result is acceptable fficient representation for most Boolean problems we ha e in CAD ± memory complexity is same as the size of circuits we are actually building Close to input representation and output representation in logic synthesis 16 .

Definitions

Definition: A Boolean circuit is a directed graph C(G,N) where G are the gates and N GvG is the set of directed edges (nets) connecting the gates. Some of the ertices are designated: Inputs: I G Outputs: O G, I O = ach gate g is assigned a Boolean function fg which computes the output of the gate in terms of its inputs.

17

Definitions

The fanin FI(g) of a gate g are all predecessor ertices of g: FI(g) = {g¶ | (g¶,g) N} The fanout FO(g) of a gate g are all successor ertices of g: FO(g) = {g¶ | (g,g¶) N} The cone CON (g) of a gate g is the transiti e fanin of g and g itself. The support SUPPORT(g) of a gate g are all inputs in its cone: SUPPORT(g) = CON (g) I

18

Example

8 1 4 2 5 3

FI(6) = {2,4} FO(6) = {7,9} CONE(6) = {1,2,4,6} SUPPORT(6) = {1,2}

7

6 9

O

I

19

the computation of hg depends in general on those delays.....Circuit Function Circuit functions are defined recursi ely: if g i I ®xi ± hgi ! ¯ f ± gi (hg j . 20 . Proposition: A circuit C is combinational if it is acyclic. Definition: A circuit C is called combinational if for each input assignment of C for tpg the e aluation of hg for all outputs is independent of the internal state of C. hgk ).. g j .... g k FI ( g i ) otherwise ° If G is implemented using physical gates that ha e positi e (bounded) delays for their e aluation.

.g1).g)).(g1.g2).Cyclic Circuits Definition: A circuit C is called cyclic if it contains at least one loop of the form: ((g. .gn)... g .(gn-1. In order to check whether the loop is combinational or sequential..(gn. we need to deri e the loop function hloop by cutting the loop at gate g 21 .«.

.... g FI ( g ) otherwise f j k i gk ° gi g j 22 . g ...Cyclic Circuits hloop .... ...... h ' gk )..... hloop ! h( x. v) ! f g ( h ' g j .. g k FI ( g ) ®xi if gi I ± if g i ! g h ' gi ! ¯ v ± (h ' .. g g .... h ' ).. . g j .

v ) v hloop ( x.Cyclic Circuits xi v hloop The following equation computes the sensiti ity of h with respect to v: hloop ( x.oscillator (astable multi ibrator) positi e feedback . hloop will toggle if toggles.flip-flop (bistable multi ibrator) 23 . v ) v ! 1 For any solution x. negati e feedback .

´ 24 .Cyclic Circuits Theorem: A circuit loop in ol ing gate g is combinational if: Theorem: Output y of a circuit containing a loop with gate g is combinational if: ³Either the loop is combinational or the output does not depend on the loop alue.

Circuit Representations For general circuit manipulation (e. SIS) ± Boolean expressions read from a library description ± BDDs Data structure allow ery general mechanisms for insertion and deletion of ertices.g. such as: ± other circuits (hierarchical representation) ± Truth tables or cube representation (e.g. synthesis): Vertices ha e an arbitrary number of inputs and outputs Vertices can represent any Boolean function stored in different ways. pins (connections to ertices). and nets ± general but far too slow for Boolean reasoning 25 .

g.OR) on-the-fly compaction of circuit structure ± allows incremental. well defined set of possible function labels (e. two) Vertex function is stored as label.g. AND. subsequent reasoning on multiple problems 26 .g. a SAT engine): Circuits are non-canonical ± computational effort is in the ³checking part´ of the reasoning engine (in contrast to BDDs) Vertices ha e fixed number of inputs (e. OR.Circuit Representations For efficient Boolean reasoning (e.

. int SAT(Edge p1) External reference pointers attached to application data structures Engine Implementation: .call SAT to make decision Engine Interface: void INIT() void QUIT() Edge VAR() Edge AND(Edge p1..tra erse problem data structure and build Boolean problem using the interface ... Edge p2) Edge NOT(Edge p1) Edge OR(Edge p1 Edge p2) .... ....Boolean Reasoning Engine Engine application: .. 27 . .

Basic Approaches Boolean reasoning engines need: ± a mechanism to build a data structure that represents the problem ± a decision procedure to decide about SAT or UNSAT Fundamental trade-off trade± canonical data structure data structure uniquely represents function decision procedure is tri ial (e. just pointer comparison) example: Reduced Ordered Binary Decision Diagrams Problem: Size of data structure is in general exponential ± non-canonical data structure non systematic search for satisfying assignment size of data structure is linear Problem: decision may take an exponential amount of time 28 ..g.

ANDAND-INVERTER Circuits Base data structure uses two-input AND function for ertices and INVERTER attributes at the edges (indi idual bit) ± use De¶Morgan¶s law to con ert OR operation etc. Hash table to identify and reuse structurally isomorphic circuits f f g g 29 .

Data Representation Vertex: ± pointers (integer indices) to left and right child and fanout ertices ± collision chain pointer ± other data Edge: ± pointer or index into array ± one bit to represent in ersion Global hash table holds each ertex to identify isomorphic structures Garbage collection to regularly free un-referenced ertices 30 .

.. 0456 0 left 1 right next fanout . 0455 0456 0457 . Constant One Vertex zero 1345 «. 7463 «.. hash alue left pointer right pointer next in collision chain array of fanout pointers 0456 0 left 0 right next fanout 31 Hash Table 6423 «.. complement bits .Data Representation one 8456 «.

that reduces the search through the list by 1/2 .use memory locations (or array indices) in topological order of circuit .keep collision chain sorted by the address (or index) of p .p2) p = &hash_table[index] while(p != NULL) { if(p->left == p1 && p->right == p2) return p.that results in better cache performance 32 . Edge p2) { index = HASH_FUNCTION(p1. } return NULL.Hash Table Algorithm HASH_LOOKUP(Edge p1. p = p->next. } Tricks: .

p2)) return p return CREATE_AND_VERTEX(p1.p2) } 33 .Basic Construction Operations Algorithm AND(Edge p1.p2) if((p = HASH_LOOKUP(p1.Edge p2){ if(p1 == const1) return p2 if(p2 == const1) return p1 if(p1 == p2) return p1 return const0 if(p1 == ^p2) if(p1 == const0 || p2 == const0) return const0 if(RANK(p1) > RANK(p2)) SWAP(p1.

Basic Construction Operations Algorithm NOT(Edge p) { return TOOGLE_COMPLEMENT_BIT(p) } Algorithm OR(Edge p1.Edge p2){ return (NOT(AND(NOT(p1).NOT(p2)))) } 34 .

Cofactor Operation Algorithm POSITIVE_COFACTOR(Edge p.c) } if(IS_INVERTED(p)) return NOT(c) else return c } 35 .right) SET_COFACTOR(p.Edge v){ if(IS_VAR(p)) { if(p == v) { if(IS_INVERTED(v) == IS_INVERTED(p)) return const1 else return const0 } else return p } if((c = GET_COFACTOR(p)) == NULL) { left = POSITIVE_COFACTOR(p->left. v) right = POSITIVE_COFACTOR(p->right. v) c = AND(left.

OR and COFACTORS Question: What is the complexity of the circuits resulting from quantification? 36 .Cofactor Operation .similar algorithm for NEGATIVE_COFACTOR .existential and uni ersal quantification build from AND.

± Identical to Tautology on the in erted ertex SAT on circuits is identical to the justification part in ATPG ± First half of ATPG: justify a particular circuit ertex to ³1´ ± Second half of ATPG (propagate a potential change to an output) can be easily formulated as SAT (will be co ered later) Basic SAT algorithms: ± branch and bound algorithm as seen before branching on the assignments of primary inputs only (Podem algorithm) branching on the assignments of all ertices (more efficient) 37 . SAT: ± Find an assignment to the inputs that e aluate a gi en ertex to ³1´.SAT and Tautology Tautology: ± Find an assignment to the inputs that e aluate a gi en ertex to ³0´.

General Da is-Putnam Procedure is search for consistent assignment to entire cone of requested ertex by systematically trying all combinations (may be partial!!!) keep a queue of ertices that remain to be justified ± pick decision ertex from the queue and case split on possible assignments ± for each case propagate as many implications as possible ± generate more ertices to be justified ± if conflicting assignment encountered » undo all implications and backtrack recur to next ertex from queue Algorithm SAT(Edge p) { queue = INIT_QUEUE() if(IMPLY(p) return TRUE return JUSTIFY(queue) } 38 .

General Da is-Putnam Procedure isAlgorithm JUSTIFY(queue) { if(QUEUE_EMPTY(queue)) return TRUE mark = ASSIGNMENT_MARK() v = QUEUE_NEXT(queue) // decision vertex if(IMPLY(NOT(v->left)) { if(JUSTIFY(queue)) return TRUE } // conflict UNDO_ASSIGNMENTS(mark) if(IMPLY(v->left) { if(JUSTIFY(queue)) return TRUE } // conflict UNDO_ASSIGNMENTS(mark) return FALSE } 39 .

Example SAT(NOT(9))?? 1 2 3 4 7 5 8 6 9 0 Queue 9 Assignments 9 First case for 9: 1 2 3 1 0 1 4 5 8 6 1 1 7 1 0 9 0 9 9 7 4 5 1 2 Conflict!! .backtrack 40 .undo all assignments .

3 = 0 41 . 2 = 0.ertex 7 is justified by 8->5->7 2 3 First case for 5: 1 0 2 3 0 5 8 6 0 1 0 4 0 7 0 1 9 0 9 7 8 5 6 2 3 Solution cube: 1 = x.Example Second case for 9: 1 4 0 7 8 6 0 5 1 0 0 1 9 0 Queue 5 6 Assignments 9 7 8 5 6 Note: .

Implication Procedure Fast implication procedure is key for efficient SAT sol er!!! ± don¶t mo e into circuit parts that are not sensitized to current SAT problem ± detect conflicts as early as possible Table lookup implementation (27 cases): ± No implications: x x x 0 0 x x 1 1 0 0 x 1 x 1 1 1 x 0 x 0 0 1 0 0 0 0 ± Implications: 0 x x x 0 x 0 0 x x x 1 x 1 1 1 x 42 1 .

Implication Procedure ± Implications: x 1 0 1 x 0 1 1 x 1 0 x 0 1 x ± Conflicts: 0 x 1 0 0 1 0 1 1 x 0 1 1 0 1 1 1 0 ± Case Split: x x 0 43 .

Ordering of Case Splits arious heuristics work differently well for particular problem classes often depth-first heuristic good because it generates conflicts quickly mixture of depth-first and breadth-first schedule other heuristics: ± pick the ertex with the largest fanout ± count the polarities of the fanout separately and pick the ertex with the highest count in either one ± run a full implication phase on all outstanding case splits and count the number of implications one would get some cases may already generate conflicts. the other case is immediately implied pick ertices that are in ol ed in small cut of the circuit == 0? ³small cut´ 44 .

Learning Learning is the process of adding ³shortcuts´ to the circuit structure that a oids case splits ± static learning: global implications are learned ± dynamic learning: learned implications only hold in current part of the search tree Learned implications are stores as additional network Back to example: ± First case for ertex 9 lead to conflict ± If we were to try the same assignment again (e. we would get the same conflict => merge ertex 7 with Zero. for the next SAT call).g.if rehashing is in oked ertex 9 is simplified and and merged with ertex 8 .ertex Zero Vertex 1 2 3 1 0 1 4 5 8 6 45 1 1 7 1 0 9 0 .

// create new vertex p if((p¶=HASH_LOOKUP(p1. . .p2)) { LEARN((p=0)&(p¶=0) (p2=0)) } Zero Vertex 46 .p2) { .NOT(p2))) { LEARN((p=0)&(p¶=0) (p1=0)) } if((p¶=HASH_LOOKUP(NOT(p1).Static Learning Implications that can be learned structurally from the circuit ± Example: (( x y ) | 0) ( x y ) | 0) ( x | 0) ± Add learned structure as circuit Use hash table to find structure in circuit: Algorithm CREATE_AND(p1.

Back to Example Original second case for 9: 1 2 3 4 0 5 8 6 0 1 0 7 0 1 9 0 Queue 5 6 Assignments 9 7 8 5 6 Second case for 9 with static learning: 1 2 3 0 4 0 5 8 6 0 a 1 0 7 0 1 9 0 9 7 8 5 6 a 3 47 1 b Zero Vertex Solution cube: 1 = x. 3 = 0 . 2 = x.

Static Learning Socrates algorithm: based on contra-positi e: ( x y) ( y x ) foreach vertex v { mark = ASSIGNMENT_MARK() IMPLY(v) LEARN_IMPLICATIONS(v) UNDO_ASSIGNMENTS(mark) IMPLY(NOT(v)) LEARN_IMPLICATIONS(NOT(v)) UNDO_ASSIGNMENTS(mark) } 0 0 x 0 y 1 (( x ! 0) ( y ! 1)) (( y ! 0) ( x ! 1)) 1 x Problem: learned implications are far too many ± solution: restrict learning to non-tri ial implications ± mask redundant implications 0 y 0 0 Zero Vertex 48 .

Recursi e Learning Compute set of all implications for both cases on le el i ± static implications (y=0/1) ± equi alence relations (y=z) Intersection of both sets can be learned for le el i-1 (( x ! 1) ( y ! 1) ( x ! 0) ( y ! 1)) ( y ! 1) 1 1 y x y 0 y 1 x 0 0 1 x y x 1 0 x 1 x 0 Apply learning recursi ely until all case splits exhausted ± recursi e learning is complete but ery expensi e in practice for le els > 2.3 ± restrict learning le el to fixed number -> becomes incomplete 49 .

Recursi e Learning Algorithm RECURSIVE_LEARN(int level) { if(v = PICK_SPLITTING_VERTEX()) { mark = ASSIGNMENT_MARK() IMPLY(v) IMPL1 = RECURSIVE_LEARN(level+1) UNDO_ASSIGNMENTS(mark) IMPLY(NOT(v)) IMPL0 = RECURSIVE_LEARN(level+1) UNDO_ASSIGNMENTS(mark) return IMPL1 IMPL0 } else { // completely justified return IMPLICATIONS } } 50 .

Dynamic Learning Learn implications in sub-tree of search cannot simply add permanent structure because not globally alid ± add and remo e learned structure (expensi e) ± add the branching condition to the learned implication of no use unless we prune the condition (conflict learning) ± use implication and assignment mechanism to assign and undo assigns e. dynamic recursi e learning with fixed recursion le el Dynamic learning of equi alence relations (Stalmarck procedure) ± learn equi alence relations by dynamically rewriting the formula 51 .g.

x} ´ {0.Dynamic Learning Efficient implementation of dynamic recursi e learning with le el 1: ± consider both sub-cases in parallel ± use 27.1.1.x} ´ {0.x}} ± automatically set learned alues for le el0 if both le el1 choices agree x 1 0 {x.1.1.1} 0 52 .x.alued logic in the IMPLY routine {level0-value ´ level1-choice1 ´ level1-choice2} {{0.0} {1.1} x 0 {x.1.

D).gj) D reflects an implication for which an assignment of gate gi lead to the assignment of gate gj. Circuit: 0 (decision ertex) 1 2 3 4 1 4¶ 53 Implication graph: 1¶ 0 (decision ertex) 2¶ 3¶ 0 . G¶ G are the gates of C with assigned alues g{x. D Gv G are the edges. where each edge (gi.ConflictConflict-based Learning Idea: Learn the situation under which a particular conflict occurred and assert it to 0 imply will use this ³shortcut´ to detect similar conflict earlier Definition: An implication graph is a directed Graph I(G¶.

the leafs corresponds to the implication frontier Cut assignment (Ci) There is a strict implication order in the graph from the roots to the leafs ± We can completely cut the graph at any point and identical alue assignments to the cut ertices.ConflictConflict-based Learning The roots of the implication graph correspond to the decision ertices. we result in identical implications toward the leafs C1 C2 Cn-1 Cn (C1: Decision ertices) 54 .

otherwise exponential blow-up 55 . any cut assignment in the implication graph between the decision ertices and the conflict will result in the same conflict! (Ci Conflict) (NOT(Conflict) NOT(Ci)) We can learn the complement of the cut assignment as circuit ± find minimal cut in I (costs less to learn) ± find dominator ertex if exists ± restrict size of cuts to be learned.ConflictConflict-based Learning If an implication leads to a conflict.

only the decision ertices that are in the support of the conflict are needed Decision Tree: 2 3 1 3 6 2 6 5 4 1 Decision le els: 5 4 The conflict is fully symmetric with respect to the unrelated decision ertices!! ± Learning the conflict would pre ent checking the symmetric parts again BUT: It is too expensi e to learn all conflicts 56 .NonNon-chronological Backtracking If we learned only cuts on decision ertices.

0} .4.0} {4.4} {2.3} {2. If no conflict of the first choice on a decision ertex depends on that ertex. the other choice(s) will result in symmetric conflicts and their e aluation can be skipped!! By tracking the implications of the decision ertices we can skip decision le els during backtrack 0 1 2 3 4 {2.0} 57 {2.3} {4.NonNon-chronological Backtracking We can still a oid exploring symmetric parts of the decision tree by tracking the supporting decision ertices for all conflicts.

} 58 .Modified Justify Algorithm Algorithm JUSTIFY(queue) { .. return decision_levels. if((decision_levels0 = IMPLY(NOT(v->left))) == ) { if((decision_levels0 = JUSTIFY(queue)) == ) return } // conflict UNDO_ASSIGNMENTS(mark) if((decision_levels1 = IMPLY(v->left)) == ) { if((decision_levels1 = JUSTIFY(queue)) == ) return } // conflict UNDO_ASSIGNMENTS(mark) decision_levels = decision_levels0 decision_levels1..

D-Algorithm In addition to controllability.1. we need to check obser ability of a possible signal change at a ertex: ertex need to be justified to 1 (0) alue change must be obser able at the output Two implementations: ± D-algorithm using fi e.x.D} inject D at internal ertex expect D or D at one of the circuit outputs ± regular SAT problem based on replicated fanout structure 59 .D.alued logic {0.

Fi e-Valued Implication Rules e- ~ 0 0 ~ ~ \ 0 ~ & 0 0 0 0 0 0 0 ~ 0 0 ~ 0 ~ 0 ~ 0 60 .

- Chapter04.Doc1.HTML
- lec06
- Test3_2200_sol
- CC2510-LN2-CombinLogic
- 4366 Chapter7 testing of vlsi circuits
- ClaseEtcI-4
- 03-WorkComb
- Class Notes Digital Lec14
- Solved Exercise Boolean Algebra
- Discrete Structure
- Chapter 6 - Boolean - EE
- hw2 sol
- Boolean Algebra
- Logic
- Presentation Ffnal
- Digital Electronics
- Positive&Negative Logic
- NAND NOR Implementation
- cap2_katz[1]
- lec04_Logic Synthesis.pdf
- EEL3712_6
- Ee177 Supplement 2
- Lecture 21
- 03-WorkComb
- ch3-2-revised_2013-03-16
- Switching Theory & Logic Design Notes_unit 2
- 5323_n_17306
- 09.Combinatorial.pdf
- Ch3 B Algebra
- lab03
- 002-functions-and-circuits

Are you sure?

This action might not be possible to undo. Are you sure you want to continue?

We've moved you to where you read on your other device.

Get the full title to continue

Get the full title to continue reading from where you left off, or restart the preview.

scribd