You are on page 1of 27

1.

LOGISTICS
2. CONTACT INFORMATION
3. SYLLABUS
4. COURSE MATERIALS
5. EVALUATION PATTERN
6. GRADING POLICY
7. COURSE INFORMATION & STRUCTURE
8. WHAT IS THE COURSE ABOUT?
LOGISTICS
• LECTURES IN SEMINAR HALL OR IN
YOUR CLASS ROOM
• SLOT: F
• TIMINGS:
MONDAY : 9 - 10AM
WEDNESDAY: 10.15 - 11.15AM
FRIDAY : 11.15AM – 12.15 NOON
CONTACT INFORMATION
INSTRUCTOR: Subashini.R
Mail-id: suba@nitc.ac.in
Phone: Office - 2286811
CSU 215 COMPUTER ORGANISATION ( Pre-requisite: CSU 202 Logic Design )
L T P Cr
302 4
Module I (11 + 10 Hours)
Computer abstraction and technology: basic principles, hardware components, Measuring performance: evaluating, comparing
and summarizing performance.
Instructions: operations and operands of the computer hardware, representing instructions, making decision, supporting
procedures, character manipulation, styles of addressing, starting a program.
 
Module II (10 + 6 Hours)
Computer arithmetic: signed and unsigned numbers, addition and subtraction, logical operations, constructing an ALU,
multiplication and division, floating point representation and arithmetic.
 
Module III (10 + 6 Hours)
The processor: building a data path, simple and multicycle implementations, microprogramming, exceptions, Case study:
Pentium Pro implementation.
 
Module IV (11 + 6 Hours)
Memory hierarchy: caches, cache performance, virtual memory, common framework for memory hierarchies, Case study:
Pentium Pro memory hierarchy.
Input/output: I/O performance measures, types and characteristics of I/O devices, buses, interfaces in I/O devices, design of an
I/O system.
  
References:
D. A. Pattersen and J. L. Hennesy, Computer Organisation and Design: The Hardware/ Software Interface, 3/e, Morgan
Kaufman, Singapore, 2004.
 
V. P. Heuring and H. F. Jordan, Computer System Design and Architecture, Addison Wesley, New Delhi, 1997.
COURSE MATERIALS
Primary Textbook:
1) Computer Organization and Design: The
Hardware/Software Interface
David A. Patterson, John L. Hennessy,
Third edition.
2) VHDL Starter’s Guide, 2nd Edition,
Yalamanchili.
EVALUATION PATTERN
MID-TERM TEST #1 – 15 MARKS
MID-TERM TEST #2 – 15 MARKS
SURPRISE TEST - 5 MARKS
ASSIGNMENT - 15 MARKS

END-SEM EXAMINATION – 50 MARKS


MAKE-UP EXAM
• NO MAKE UP EXAM FOR THE SURPRISE
TEST
• MAKE UP FOR THE MID-TERM TEST, ONLY
FOR GENUINE REASONS
• REQUEST FOR MAKE-UP EXAM HAS TO BE
GIVEN WITHIN FIVE WORKING DAYS
• A STUDENT HAS TO WRITE A MAKE-UP
EXAM, MAXIMUM FOR 3 HOURS
• MAKE-UP EXAM WILL BE CONDUCTED ONLY
AFTER THE END-SEM EXAM
ATTENDANCE
• YOUR ATTENDANCE SHOULD BE >= 80%
• INDIVIDUALS SHOULD KEEP A COUNT OF
HOW MANY DAYS THAT YOU ARE
ABSENT FOR THE CLASSES
Assignment
• Simulator for MIPS - SPIM
• For modeling simple digital systems - VHDL
Divide the students into groups of 6.
1. Seminar – Topic either from SPIM or VHDL or an
example SPIM program or VHDL (similar to
Booth’s algorithm)
2. Identify the problem (similar to Reverse Polish
Notation Calculator )
3. Write the code and show the demo.
4. Submit your results
GRADING POLICY
• RELATIVE GRADING

• BUT, SEE TO THAT YOU ARE IN THE


SAFE SIDE BY EARNING TOTAL
MARKS >= 40
ACADEMIC INTEGRITY
• You are encouraged to discuss assignments with
anyone you feel may be able to help you (except during
exams)
• Everything you turn in must be your work or that of your
team
• Encouraged collaboration:
• Verbal discussion of problems/solutions
• Diagrams, notes, other communication aids
• Unacceptable
• Copying of program code or text by any means
• Giving/receiving help on exams, or using any notes/aid
beyond those explicitly permitted
Outline
1. Structure and functionality of computers – a
survey
2. Data representation
3. Computer Arithmetics
4. Instruction set
5. Data path and control
6. Instruction level parallelism
7. Memory Hierarchy
8. Multiprocessors
TENTATIVE SCHEDULE
Lecture No. Topics to be covered Reference to T1

01, 02 Introduction Ch. 1

03, 04, 05 MIPS Architecture & Instruction Set Ch. 2

06 Computer Arithmetic Ch. 3.1 – 3.5

07,08 Floating Point Arithmetic Ch 3.6 – 3.10

09, 10 Role of Performance Ch. 4

11,12, 13 Data path Design Ch. 5.1 – 5.4

14, 15 Control Hardware Appendix – C

16, 17, 18 MCI, Exceptions & Microprogramming Ch. 5.5 – 5.9

19, 20 Memory Organisation- Introduction ---

21, 22 Cache Memory Organisation Ch. 7.1 – 7.3

23, 24, 25 Main Memory & Interleaving Ch. 7.4 – 7.9

26, 27 I/O Organisation Ch. 8

28, 29 Pipelining – Design Issues Ch. 6.1 – 6.3

30, 31 Data Hazards Ch. 6.4 – 6.5

32, 33 Control Hazards Ch. 6.6

34, 35 Static Branch Prediction ---

36 Dynamic Branch Prediction ---

37 Advanced Concepts in pipelining Ch. 6.9

38, 39 Modern Processors ---

40, 41, 42 Parallel Processing Ch. 9


What is Computer Organization?
“Computer Organization”
• How computer systems are organized and
designed
Two major sub-topics
• Instruction set architecture
• How are programs expressed to the computer?
• Microarchitecture
• How is the hardware that executes programs
implemented?
Big Picture…….
Instruction Set Architecture (ISA)
The Interface between Hardware and Software

Software
__________________________________
Instruction Set Architecture (ISA)
__________________________________

Hardware
The Processor (or Central Processing Unit)

Executes instructions, which are represented as


bit patterns
• Contains a register file, which holds data that
will be referenced by instructions
• Has a program counter that holds the address of
the instruction being executed
• Can access memory
Memory

Set of locations, each of which holds a piece of


data
• Use address to select the location we want to
access
• Random-access: time to access a piece of data
is independent of which address the data is
stored in
• Nice theory, not true in practice, as we’ll see
I/O

Interact with humans: keyboard, mouse,


monitor
• Interact with other machines: network
• Long-term data storage: hard disk, CD-
ROM,etc.
Levels of Transformation
Task or Application
__________________________________
Algorithm
__________________________________
Program
__________________________________
Machine Language (ISA)
__________________________________
Microarchitecture
__________________________________
Logic
__________________________________
Circuits
__________________________________
Devices
Multiprogramming

Most computers have only one processor, but run


multiple programs at the same time.
• Present the illusion that these programs are running at the same time
• “Only one processor” is another statement that’s becoming
increasingly untrue over time
• This is called multiprogramming
• Originally used because computers were expensive enough that one
machine had to support many users
• Now used more because we want to do many things at the same
time
Multiprogramming

Basic idea: Computer switches between


programs fast enough (60+ times/second)
that the human never notices
• Processor has a timer interrupt that goes
off at the end of each time slice
• When timer interrupt occurs, operating
system intervenes and switches the
program that’s executing (context switch)
Context Switch

State (program counter, register contents) of


program A saved out to memory
• State of program B copied in
• Execution resumes
• Issue: How do we prevent program B from
accessing program A’s data?

You might also like