11/2/2011 Anirudh Radhakrishnan 1

1HL ARM71DMI 1HL ARM71DMI
Introduction And Architecture Introduction And Architecture
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IN1RODUC1ION 1O ARM IN1RODUC1ION 1O ARM
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History of ARM History of ARM
Acron started in 1983 Acron started in 1983
Bv 1985 design oí íirst commercial RIS( Bv 1985 design oí íirst commercial RIS(
machine called Acron RIS( Machine ARM,. machine called Acron RIS( Machine ARM,.
In 1990 there were 12 engineers and 1 (LO. In 1990 there were 12 engineers and 1 (LO.
with no customers and a little monev. with no customers and a little monev.
In 1990`s 1I incorporated ARM íor mobile In 1990`s 1I incorporated ARM íor mobile
phones phones
Bv 1998 there were 13 millionaires in companv. Bv 1998 there were 13 millionaires in companv.
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Origin Of the Name ARM71DMI Origin Of the Name ARM71DMI
ARM ARM -- cron cron ##isc isc achine achine Now Now A Ad·anced d·anced RRisc isc M Machine achine,,
1 1 -- 1he 1humb 16 bit instruction set. 1he 1humb 16 bit instruction set.
D D -- On chip Debug support. On chip Debug support.
M M -- Lnhanced Multiplier Lnhanced Multiplier
I I -- Lmbedded I(L hardware to gi·e break point Lmbedded I(L hardware to gi·e break point
and watch point support. and watch point support.
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ARM Ieatures ARM Ieatures
RIS( RIS(
32 bit 2 bit general purpose processor processor
ligh períormance . low power consumption and ligh períormance . low power consumption and
small size small size
Large . regular Register lile Large . regular Register lile
toaa´.tore toaa´.tore architecture architecture
!ipelining !ipelining
Uniíorm and íixed Uniíorm and íixed--length32 bit, instruction length32 bit, instruction--ARM, ARM,
33--address instruction address instruction
Simple addressing modes Simple addressing modes
contd contd--
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(onditional execution oí the instructions (onditional execution oí the instructions
(ontrol o·er both ALU and Shiíter in e·erv data (ontrol o·er both ALU and Shiíter in e·erv data
processing instruction processing instruction
Multiple load´store register instructions Multiple load´store register instructions
Abilitv to períorm 1clk cvcle general shiít & Abilitv to períorm 1clk cvcle general shiít &
ALU operation in 1 instruction ALU operation in 1 instruction
(oprocessor instruction interíacing (oprocessor instruction interíacing
1lUMB architecture 1lUMB architecture--dense 16 dense 16--bit compressed bit compressed
instruction set, instruction set,
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1HUMB Instruction Set (1 variant) 1HUMB Instruction Set (1 variant)
re re--encoded subset oí ARM instruction encoded subset oí ARM instruction
lalí the size oí ARM instructions16 bit, lalí the size oí ARM instructions16 bit,
Greater code densitv Greater code densitv
On execution 16 bit thumb transparentlv decompressed On execution 16 bit thumb transparentlv decompressed
to íull 32 bit ARM without loss oí períormance to íull 32 bit ARM without loss oí períormance
las all the ad·antages oí 32 bit core las all the ad·antages oí 32 bit core
Low períormance in time Low períormance in time--critical code critical code
Doesn`t include some instruction needed íor exception Doesn`t include some instruction needed íor exception
handling handling
contd contd--
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0° more instructions than ARM code 0° more instructions than ARM code
30° less external memorv power than ARM code 30° less external memorv power than ARM code
\ith 32 bit memorv \ith 32 bit memorv
--ARM code 0° íaster than 1humb code ARM code 0° íaster than 1humb code
\ith 16 bit memorv \ith 16 bit memorv
--1humb code 5° íaster than Arm code 1humb code 5° íaster than Arm code
lor best períormance lor best períormance
--use 32 bit memorv and ARM code use 32 bit memorv and ARM code
lor best cost and power eííiciencv lor best cost and power eííiciencv
--use 16 bit memorv and thumb code use 16 bit memorv and thumb code
In tvpical embedded svstem In tvpical embedded svstem
--Use ARM code in 32 bit on Use ARM code in 32 bit on--chip memorv íor small speed chip memorv íor small speed--
critical routines critical routines
--Use 1humb code in 16 bit oíí Use 1humb code in 16 bit oíí--chip memorv íor large non chip memorv íor large non--
critical routines critical routines
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ARM state ARM state
All instructions are 32 bit in length All instructions are 32 bit in length
All instructions must be word aligned All instructions must be word aligned
!( ·alue stored in bits|31:2| and bits |1:0| equal !( ·alue stored in bits|31:2| and bits |1:0| equal
to zero to zero
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1HUMB state 1HUMB state
Instructions 16 bit in length Instructions 16 bit in length
Instructions halí Instructions halí--word aligned word aligned
!( ·alue stored in bits|31:1| and bit |0| equal to !( ·alue stored in bits|31:1| and bit |0| equal to
zero zero
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Introduction to RISC And CISC Introduction to RISC And CISC
\hat is (IS(· \hat is (IS(·
C Complex omplex IInstruction nstruction S Set et C Computers. omputers.
Aimed at reducing the gap between instruction set Aimed at reducing the gap between instruction set
and high le·el language. and high le·el language.
1hese instructions períorm complex sequence oí 1hese instructions períorm complex sequence oí
operations o·er manv cvcles. operations o·er manv cvcles.
Large and poweríul range oí instruction Large and poweríul range oí instruction
Less ílexible to implement Less ílexible to implement
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RISC RISC
RIS( stands íor Reduced Instruction Set RIS( stands íor Reduced Instruction Set
(omputer. (omputer.
Optimizing the instruction set and impro·ing Optimizing the instruction set and impro·ing
the speed oí the processor. the speed oí the processor.
1he memorv access instructions are those which 1he memorv access instructions are those which
make a computer slow. Arithmetic instructions make a computer slow. Arithmetic instructions
ha·e less eííect on speed oí processor. ha·e less eííect on speed oí processor.
Around 5° oí (!U usage is íor Data transíer. Around 5° oí (!U usage is íor Data transíer.
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RISC Architecture RISC Architecture
lixed instruction size with íew íormats. lixed instruction size with íew íormats.
Memorv access instructions are separated írom Memorv access instructions are separated írom
instructions that process data. instructions that process data.
A large register bank oí 32 registers each oí size A large register bank oí 32 registers each oí size
32 bits. 32 bits.
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RISC Ieatures RISC Ieatures
lard wired instruction decode logic. lard wired instruction decode logic.
!ipelined instruction execution !ipelined instruction execution
Large number oí registers Large number oí registers
Register independence Register independence
Smaller die size Smaller die size
Low power Low power
Simpler to program Simpler to program
(omparati·elv less expensi·e (omparati·elv less expensi·e
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Advantages Of RISC Advantages Of RISC
Reduction in the size oí processor. Reduction in the size oí processor.
ligh instruction throughput. ligh instruction throughput.
Lxcellent response íor interrupt. Lxcellent response íor interrupt.
Lííicient usage oí (!U time. Lííicient usage oí (!U time.
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!ipelines !ipelines
Usuallv instructions are executed in three stages. Usuallv instructions are executed in three stages.
letch letch
Decode Decode
Lxecute Lxecute
(an we concurrentlv use the processor to (an we concurrentlv use the processor to
períorm se·eral operations· períorm se·eral operations·
\es. this is what is known as !I!LLINING. \es. this is what is known as !I!LLINING.
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!ipelines !ipelines
(learlv. portion oí the hardware which does (learlv. portion oí the hardware which does
íetching job will be idle during decode and íetching job will be idle during decode and
execute phase. execute phase.
1his led to idea that next instruction can be 1his led to idea that next instruction can be
started beíore the current one has íinished. started beíore the current one has íinished.
letch the II instruction during decoding oí II letch the II instruction during decoding oí II
instruction. decode the II instruction during instruction. decode the II instruction during
execution oí I instruction and so on. execution oí I instruction and so on.
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!ipelining !ipelining
!ipe lining !ipe lining
lL1(l
DL(ODL
LXL(U1L
III INS1RU(1ION lL1(lLD
II INS1RU(1ION DL(ODLD
I INS1RU(1ION LXL(U1LD
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!ipeline Stages !ipeline Stages
letch letch
o o instruction is íetched írom memorv and placed in instruction instruction is íetched írom memorv and placed in instruction
pipeline pipeline
Decode Decode
o o instruction is decoded instruction is decoded
o o data data--path control signals prepared íor next cvcle path control signals prepared íor next cvcle
o o in data transíer instructions .ALU holds address in data transíer instructions .ALU holds address
components to compute auto indexing modiíication ií components to compute auto indexing modiíication ií
required required
Lxecute Lxecute
o o register bank is read register bank is read
o o ALU result generated ALU result generated
o o result written back into destination register result written back into destination register
o o in control ílow instructions .pipeline reíilling is done in control ílow instructions .pipeline reíilling is done
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!rocessor Modes !rocessor Modes
ARM has ¯ operating modes ARM has ¯ operating modes
User User
unpri·ileged mode under which most tasks run, unpri·ileged mode under which most tasks run,
Iast Interrupt Request Mode IIQ Iast Interrupt Request Mode IIQ
to handle high prioritv interrupt , to handle high prioritv interrupt ,
Interrupt Mode IRQ Interrupt Mode IRQ
entered when a low prioritv interrupt is raised , entered when a low prioritv interrupt is raised ,
Supervisor Mode SVC Supervisor Mode SVC
entered on reset or a soítware interrupt , entered on reset or a soítware interrupt ,
Abort Mode AB1 Abort Mode AB1
used to handle memorv access ·iolation, used to handle memorv access ·iolation,
Undefined Mode UND Undefined Mode UND
used to handle undeíined instruction, used to handle undeíined instruction,
System Mode SYS System Mode SYS
uses same registers as user mode .added at ·ersion , uses same registers as user mode .added at ·ersion ,
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MODLS MODLS
Most application program run in User Mode Most application program run in User Mode
A program in user mode is unable to access some A program in user mode is unable to access some
protected svstem resources or to change mode . other protected svstem resources or to change mode . other
than bv causing exception than bv causing exception
Mode change can be bv Mode change can be bv
--Soítware control Soítware control
--Lxternal interrupts Lxternal interrupts
--Lxception processing Lxception processing
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MODLS MODLS
Modes other than user mode are called Modes other than user mode are called 5riritegea voae. 5riritegea voae.
!ri·ileged modes has íull access to the svstem !ri·ileged modes has íull access to the svstem
resources resources
li·e oí them are called exception modes li·e oí them are called exception modes
IIQ IIQ
IRQ IRQ
SVC SVC
AB1 AB1
UND UND
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MODLS MODLS
!rocessor enters into !ri·ileged modes under !rocessor enters into !ri·ileged modes under
speciíic exception condition speciíic exception condition
All the exception Modes uses some additional All the exception Modes uses some additional
registers .to a·oid corrupting the user state registers .to a·oid corrupting the user state
when exception occurs when exception occurs
S\S uses the same no: oí registers as the User S\S uses the same no: oí registers as the User
Mode Mode
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DA1A 1Y!LS DA1A 1Y!LS
Bvte 8 bit , : placed on anv bvte boundarv Bvte 8 bit , : placed on anv bvte boundarv
lalí lalí--\ord 16 bit, : aligned to 2 bvte boundaries \ord 16 bit, : aligned to 2 bvte boundaries
\ord 32 bit , : aligned to bvte boundaries \ord 32 bit , : aligned to bvte boundaries
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Data 1ypes Data 1ypes
\hen anv oí the tvpe is deíined as \hen anv oí the tvpe is deíined as :3.ig3ea :3.ig3ea .the N bit .the N bit
·alue represents a non ·alue represents a non--negati·e integer in the range negati·e integer in the range 00 to to
2`^ 2`^· ·]]
when deíined as when deíined as .ig3ea .ig3ea the N bit ·alue represents an the N bit ·alue represents an
integer in the range integer in the range · ·2`t^ 2`t^ · ·])to 2`t^ ])to 2`t^· ·]) ])· ·]]
All data operations a períormed on word quantities All data operations a períormed on word quantities
Load and store operations can transíer all the data tvpes Load and store operations can transíer all the data tvpes
írom and to the memorv .automaticallv zero extending írom and to the memorv .automaticallv zero extending
or sign extending bvtes or halí or sign extending bvtes or halí--words as thev are loaded words as thev are loaded
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RLGIS1LRS RLGIS1LRS
ARM has ARM has 32 bit long registers 32 bit long registers
· · 30 general purpose registers 30 general purpose registers
· · 5 dedicated 5 dedicated $$a·ed a·ed ! !rogram rogram $$tatus tatus ##egisters egisters
· · 1 dedicated 1 dedicated urrent urrent ! !rogram rogram $$tatus tatus ##egister egister
· · 1 dedicated program counter 1 dedicated program counter
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General !urpose Registers General !urpose Registers
0 0 32 bit registers 32 bit registers
15 general purpose registers are ·isible at one 15 general purpose registers are ·isible at one
time . depending on the current processor mode time . depending on the current processor mode
.as .as r0.r].r2 .r].r]1 r0.r].r2 .r].r]1
r] r]· ·con·entionallv used as stack pointer con·entionallv used as stack pointer
r]1 r]1 --con·entionallv used as link register to store con·entionallv used as link register to store
the return address íor exception´ sub the return address íor exception´ sub--routine routine
call call
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!rogram Counter !rogram Counter
!( is accessed as r15 !( is accessed as r15
Incremented bv bvtes íor ARM state and 2 Incremented bv bvtes íor ARM state and 2
bvtes íor 1lUMB state bvtes íor 1lUMB state
Branch instruction loads destination address into Branch instruction loads destination address into
the !( the !(
(an also be loaded using data operation (an also be loaded using data operation
instruction instruction
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!rogram Counter !rogram Counter
Due to pipelining . address oí currentlv Due to pipelining . address oí currentlv
executing instruction is tvpicallv !( executing instruction is tvpicallv !(--8 íor ARM 8 íor ARM
and !( and !(-- íor 1lUMB íor 1lUMB
lor ARM state bits 1 & 0 are alwavs zero or lor ARM state bits 1 & 0 are alwavs zero or
ignored ignored
lor 1lUMB state bit 0 is alwavs zero or lor 1lUMB state bit 0 is alwavs zero or
ignored ignored
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C!SR C!SR urrent urrent ! !rogram rogram $$tatus tatus ##egister egister
(!SR holds (!SR holds
· · (opies oí ALU status ílags (opies oí ALU status ílags
· · 1he current processor mode 1he current processor mode
· · Interrupt disable ílag Interrupt disable ílag
ALU status ílags are used to determine whether ALU status ílags are used to determine whether
conditional instructions are executed or not conditional instructions are executed or not
On 1lUMB capable processors .the (!SR On 1lUMB capable processors .the (!SR
holds the current processor state holds the current processor state
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ILAGS ILAGS
Condition code flags Condition code flags
N(3J) N(3J) ÷÷ set to bit 31 oí the result oí the instruction set to bit 31 oí the result oí the instruction
N~0 ií positi·e N~0 ií positi·e
N~1 ií negati·e N~1 ií negati·e
(30) (30) ÷÷ ~1 ií result is zero ~1 ií result is zero
~0 ií not zero ~0 ií not zero
C(29) C(29) ÷÷ íor addition .set to 1 ií carrv occurs & 0 otherwise íor addition .set to 1 ií carrv occurs & 0 otherwise
íor subtraction .set to 0 ií borrow occurs & 1 íor subtraction .set to 0 ií borrow occurs & 1
otherwise otherwise
íor shiít operations . ( contains the last bit shiíted íor shiít operations . ( contains the last bit shiíted
VV (28) (28) ÷÷ íor addition and subtraction V set to 1 ií signed o·erílow íor addition and subtraction V set to 1 ií signed o·erílow
occurs occurs
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ILAGS ILAGS
Control bits Control bits
I(7) I(7) -- when set disables IRO interrupt when set disables IRO interrupt
I(6) I(6) - - when set disables lIO interrupt when set disables lIO interrupt
1(5) 1(5) - - on 1 ·ariants oí ·5 on 1 ·ariants oí ·5
1~0 .indicates ARM execution 1~0 .indicates ARM execution
1~1 .indicates 1lUMB execution 1~1 .indicates 1lUMB execution
on non on non--1 ·ariants 1 ·ariants
1~0.indicates ARM execution 1~0.indicates ARM execution
1~1.causes the next instruction executed 1~1.causes the next instruction executed
to cause UND to cause UND
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ILAGS ILAGS
MODL BI1S :0, MODL BI1S :0,
M(4:0) M(4:0) Mode Mode
10000 10000 User User
10001 10001 lIO lIO
10010 10010 IRO IRO
10011 10011 Super·isor Super·isor
10111 10111 Abort Abort
11011 11011 UND UND
11111 11111 S\S S\S
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S!SR S!SR $$aved aved ! !rogram rogram $$tatus tatus ##egister egister
Used to store (!SR when an exception is taken Used to store (!SR when an exception is taken
One S!RS is accessible in each oí the exception One S!RS is accessible in each oí the exception
handling mode handling mode
User Mode and Svstem Mode doesn`t ha·e User Mode and Svstem Mode doesn`t ha·e
S!RS as thev don`t handle exceptions S!RS as thev don`t handle exceptions
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General !urpose Registers General !urpose Registers
(an be di·ided into three groups (an be di·ided into three groups
Un Un--banked r0 banked r0--r¯ r¯
Banked r8 Banked r8--r1 r1
!( r15 !( r15
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Un Un banked Registers banked Registers
Registers Registers r0 r0 to to r r
Lach oí these registers address the same phvsical Lach oí these registers address the same phvsical
registers íor all the modes registers íor all the modes
(ompletelv general purpose registers . with no (ompletelv general purpose registers . with no
uses implied bv the architecture uses implied bv the architecture
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Banked Registers Banked Registers
Registers Registers rº rº to to r]1 r]1
phvsical registers reíerred to bv each oí them phvsical registers reíerred to bv each oí them
depends on the mode oí operation depends on the mode oí operation
Banked register contents are preser·ed across Banked register contents are preser·ed across
operating mode changes operating mode changes
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Banked Registers Banked Registers
r8 to r12 r8 to r12
two banked phvsical registers each two banked phvsical registers each
one íor lIO and other íor all other modes one íor lIO and other íor all other modes
reíerred to as r8_usr to r12_usr & r8_íiq to r12_íiq reíerred to as r8_usr to r12_usr & r8_íiq to r12_íiq
r13 & r1 r13 & r1
has six banked registers each has six banked registers each
one in USLR & S\S and rest íi·e in each exception modes one in USLR & S\S and rest íi·e in each exception modes
reíerred to as r13_·mode·´r1_·mode· reíerred to as r13_·mode·´r1_·mode·íor exception modes, íor exception modes,
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ARM RLGIS1LRS ARM RLGIS1LRS
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ARM RLGIS1LRS ARM RLGIS1LRS
r0
r1
r2
r3
r
r5
r6

r8
r9
r10
r11
r12
r13
r1
r15!(,
(!SR
r0
r1
r2
r3
r
r5
r6

r8_íiq
r9_íiq
r10_íiq
r11_íiq
r12_íiq
r13_íiq
r1_íiq
r15!(,
(!SR
S!SR_íiq
r0
r1
r2
r3
r
r5
r6

r8
r9
r10
r11
r12
r13_s·c
r1_s·c
r15!(,
(!SR
S!SR_s·c
r0
r1
r2
r3
r
r5
r6

r8
r9
r10
r11
r12
r13_abt
r1_abt
r15!(,
(!SR
S!SR_abt
r0
r1
r2
r3
r
r5
r6

r8
r9
r10
r11
r12
r13_irq
r1_irq
r15!(,
(!SR
S!SR_irq
r0
r1
r2
r3
r
r5
r6

r8
r9
r10
r11
r12
r13_und
r1_und
r15!(,
(!SR
S!SR_und
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1humb State Register Set 1humb State Register Set
Is a subset oí ARM set Is a subset oí ARM set
1he programmer has access to 1he programmer has access to
8 general register r0 to r¯ 8 general register r0 to r¯
!( !(
S! S!
LR LR
(!SR (!SR
S!SR íor exception modes, S!SR íor exception modes,
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Mapping of 1humb State registers to Mapping of 1humb State registers to
ARM State registers ARM State registers
r0
r1
r2
r3
r
r5
r6

r8
r9
r10
r11
r12
r13
r1
r15
(!SR
S!SR
r0
r1
r2
r3
r
r5
r6

S!
!(
(!SR
S!SR
LR
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Lxceptions & Interrupts Lxceptions & Interrupts
Bv deíault the svstem is in User Mode Bv deíault the svstem is in User Mode
Lnters exceptions modes when unexpected e·ents occur Lnters exceptions modes when unexpected e·ents occur
1here are 3 diíí tvpes oí exceptions some are called interrupts, 1here are 3 diíí tvpes oí exceptions some are called interrupts,
11·as a direct result oí executing an instruction ·as a direct result oí executing an instruction
software interrupt request (SWI) software interrupt request (SWI)
undefined illegal instruction undefined illegal instruction
memory error during fetching an instruction memory error during fetching an instruction
22·side ·side--eííects oí an instruction eííects oí an instruction
memory error during read/write from memory memory error during read/write from memory
arithmetic error arithmetic error
33·result oí external hardware signals ·result oí external hardware signals
reset reset
fast interrupt fast interrupt
normal interrupt normal interrupt
contd contd
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Lxceptions & Interrupt Lxceptions & Interrupt
As the processor enters an exception mode As the processor enters an exception mode
.some new registers are automaticallv switched .some new registers are automaticallv switched
in depending on the tvpe oí mode in depending on the tvpe oí mode
1his ensures that task state is not corrupted bv 1his ensures that task state is not corrupted bv
occurrence oí an exception occurrence oí an exception
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What happens when exception occurs What happens when exception occurs
ARM completes the current instruction as best ARM completes the current instruction as best
as it can as it can
Departs írom current instruction to handle the Departs írom current instruction to handle the
exception through íollowing steps exception through íollowing steps
]) ]) .are. tbe c:rre3t ! i3 r]1 .are. tbe c:rre3t ! i3 r]1 corresponding to the new corresponding to the new
mode mode
2) 2) .are. !$# .are. !$# i3 i3 corresponding corresponding $!#$ $!#$ oí new mode oí new mode
) ) cba3ge. tbe o5erati3g voae cba3ge. tbe o5erati3g voae corresponding to an corresponding to an
exception exception
contd contd--
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, , ai.abte. e·ce5tio3. ot torer 5riority ai.abte. e·ce5tio3. ot torer 5riority
5, 5, torce. ! to a 3er rat:e torce. ! to a 3er rat:e corresponding to exception. corresponding to exception.
Lííecti·elv íorce jumps the instruction stream to Lííecti·elv íorce jumps the instruction stream to
í·ce5tio3 ía3ater í·ce5tio3 ía3ater or or í3terr:5t $errice #o:ti3e.. í3terr:5t $errice #o:ti3e..
· · a a :3iq:e aaare.. :3iq:e aaare.. is predeíined íor each is predeíined íor each
exception handler exception handler
· · address to which the processor is íorced to address to which the processor is íorced to
branch is called branch is called e·ce5tio3´i3terr:5t rector e·ce5tio3´i3terr:5t rector
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Lxception/Interrupt Vector Lxception/Interrupt Vector
Lach ·ector except lIO, is bvtes long Lach ·ector except lIO, is bvtes long
Branch instruction is put at this address Branch instruction is put at this address
Undeíined Instruction Undeíined 0x0000000 0xllll000
Soítware Interrupt Super·isor 0x00000008 0xllll0008
!re-íetch Abort Abort 0x0000000( 0xllll000(
Data Abort Abort 0x00000010 0xllll0010
IRO interrupt, IRO 0x00000018 0xllll0018
lIO íast interrupt, lIO 0x0000001( 0xllll001(
Reset Super·isor 0x00000000 0xllll0000
Lxception tvpe Mode Vector add: ligh Vector add:
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Lxception Return Lxception Return
Once the exception has been handled bv the exception handler,
.the user task is resumed.
1he handler program or Interrupt Ser·ice Routine, must
restore the user state exactlv as it was beíore the exception
occurred:
1. Anv modiíied user registers must be restored írom the handler
stack
2. 1he (!SR must be restored írom the appropriate S!SR
3. !( must be changed back to the instruction address in the user
instruction stream
Steps 1 and 3 are done bv user. step 2 bv the processor
Restoring registers írom the stack would be the same as in the
case oí subroutines
Restoring !( ·alue is more complicated. 1he exact wav to do it
depends on which exception vou are returning írom.
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Lxception Return Lxception Return
\e assume that the return address was sa·ed in r1 beíore
entering the exception handler.
1,1o return írom a S\I or undeíined instruction trap. use:
MOVS pc. r1
2,1o return írom an IRO. lIO or pre-íetch abort. use.
SUBS pc. r1. 4
3,1o return írom a data abort to retrv the data access. use:
SUBS pc. r1. 48
1hree methods are because !( ·alue can be 1 or 2 instructions
ahead due to pipelining
11/2/2011 50
Interrupt !riority Interrupt !riority
Since exceptions can arise at the same time. a prioritv
order has to be clearlv deíined. lor the ARM processor
this is:
1, Reset highest prioritv,
2, Data abort i.e. Memorv íault in read´write data,
3, last Interrupt Request lIO,
, Normal Interrupt Request IRO,
5, !re-íetch abort
6, Soítware Interrupt S\I,. undeíined instruction
11/2/2011 51
ARM71DMI Core ARM71DMI Core
11/2/2011 52
Internal organization of ARM Internal organization of ARM
1wo main blocks: data-path and decoder
Register bank r0 to r15,
1wo read ports to A-bus´B-bus
One write port írom ALU-bus
Additional read´write ports íor program counter r15
Barrel shiíter - shiít´rotate 2
nd
operand bv anv number oí bits
ALU períorms arithmetic´logic íunctions
Address registers´incrementer holds either !( address with
increment, or operand address
11/2/2011 53
Internal organization of ARM Internal organization of ARM
Data register holds read´write data írom´to memorv
Instruction decoder decodes machine code instructions
to produce control signals to data-path
In single-cvcle data processing instructions. data ·alues
are read on the A-bus & B-bus. the results írom ALU is
written back into register bank
!( ·alue in address register is incremented and copied
back to r15 and the address register - this allows
íetching new instructions ahead oí time instruction
pre-íetch,
In case oí branching .next pre-íetch address is taken
írom ALU rather than the address incrementer .1he
instruction pipeline is íilled beíore anv íurther
execution takes place.
11/2/2011 54
Datapath activity during data processing
instruction
Subtract instruction - one
operand is a constant
(onstant 128 encoded in
instruction passes through
barrel shiíter to produce 1288
ALU operates on the operands
and writes
the result back to register r0
!( ·alue in address register is
incremented and coped back to
r15 and the address register
SUB r0. r1. 4128 LSL 43 : r0 :~ r1 - 1288
11/2/2011 55
Memory Memory Address Space Address Space
ARM uses single ílat address space oí 2`32 ARM uses single ílat address space oí 2`32 bvtes bvtes
Bvte address are treated as unsigned .running írom 0 Bvte address are treated as unsigned .running írom 0
to 2`31 to 2`31--11
1he address space is regarded as consisting oí 2`30 1he address space is regarded as consisting oí 2`30
32 bit words.each oí whose addresses is word aligned 32 bit words.each oí whose addresses is word aligned
\ord .whose word aligned address is A` .consists oí \ord .whose word aligned address is A` .consists oí
íour bvtes with address A . A-1 . A-2 . A-3 íour bvtes with address A . A-1 . A-2 . A-3
lrom · and abo·e address space is also considered lrom · and abo·e address space is also considered
as 2`31 16 as 2`31 16--bit halíwords bit halíwords
11/2/2011 56
Lndianness Lndianness
Memorv svstem uses one oí the 2 mapping schemes to Memorv svstem uses one oí the 2 mapping schemes to
map between word .halí map between word .halí--word & bvte word & bvte
1, 1, tittte tittte· ·e3aia3 .y.tev: e3aia3 .y.tev:
==a bvte or halíword at a word a bvte or halíword at a word--aligned address is the least aligned address is the least
signiíicant bvte or halíword within the word at that address signiíicant bvte or halíword within the word at that address
==a bvte at a halíword a bvte at a halíword--aligned address is least signiíicant bvte aligned address is least signiíicant bvte within within
the halí word at that address the halí word at that address
\ord at address A \ord at address A
lalíword at add: lalíword at add: A-1 A-1 lalíword at add: lalíword at add: A A
Bvte at A-3 Bvte at A-3 Bvte at A-2 Bvte at A-2 Bvte at A-1 Bvte at A-1 Bvte at A Bvte at A
11/2/2011 57
2, 2, big big· ·e3aia3 .y.tev: e3aia3 .y.tev:
==a bvte or halíword at a word aligned address is the most a bvte or halíword at a word aligned address is the most
signiíicant bvte or halíword within the word at that address signiíicant bvte or halíword within the word at that address
==a bvte at a halíword aligned address is most signiíicant a bvte at a halíword aligned address is most signiíicant bvte bvte
within the halí word at that address within the halí word at that address
ARM instruction set doesn`t contain anv instruction that can ARM instruction set doesn`t contain anv instruction that can
directlv select the endianness .Instead a hardware input is used to directlv select the endianness .Instead a hardware input is used to
coníigure an ARM implementation to the memorv svstem coníigure an ARM implementation to the memorv svstem
\ord at address A \ord at address A
lalíword at add: lalíword at add: A A lalíword at add: lalíword at add: A-1 A-1
Bvte at A Bvte at A Bvte at A-1 Bvte at A-1 Bvte at A-2 Bvte at A-2 Bvte at A-3 Bvte at A-3
11/2/2011 58
Memory mapped I/O Memory mapped I/O
Standard wav to períorm I´O íunctions on Standard wav to períorm I´O íunctions on
ARM svstems is bv the use oí memorv mapped ARM svstems is bv the use oí memorv mapped
I´O I´O
1his uses special memorv addresses which 1his uses special memorv addresses which
supplv I´O íunctions when thev are loaded supplv I´O íunctions when thev are loaded
írom or stored to írom or stored to
Loading írom memorv mapped I´O address is Loading írom memorv mapped I´O address is
used íor input .and storing to memorv mapped used íor input .and storing to memorv mapped
I´O address is íor output I´O address is íor output
11/2/2011 59
Instruction fetches from memory mapped I/O Instruction fetches from memory mapped I/O
Beha·ior oí memorv mapped I´O usuallv ·arv Beha·ior oí memorv mapped I´O usuallv ·arv
írom that expected oí a normal memorv írom that expected oí a normal memorv
location location
lro eg: .two successi·e loads írom same location lro eg: .two successi·e loads írom same location
mav not vield the same result .as expected írom mav not vield the same result .as expected írom
a normal memorv. a normal memorv.
As a result .it is recommended that memorv As a result .it is recommended that memorv
mapped I´O not be used íor instruction íetch mapped I´O not be used íor instruction íetch
11/2/2011 60
Data access to memory mapped I/O Data access to memory mapped I/O
Ií memorv words .halíwords or bvtes accessed bv the Ií memorv words .halíwords or bvtes accessed bv the
code sequence are memorv mapped I´O locations. one code sequence are memorv mapped I´O locations. one
access can generate a side eííect which changes the access can generate a side eííect which changes the
results oí a subsequent access to a diííerent location results oí a subsequent access to a diííerent location
Ií this happens the time order oí indi·idual accesses Ií this happens the time order oí indi·idual accesses
makes a diííerence to the íinal result oí the code makes a diííerence to the íinal result oí the code
sequence sequence
It is also important that data size oí the memorv access It is also important that data size oí the memorv access
be maintained .when accessing memorv mapped I´O be maintained .when accessing memorv mapped I´O
lor eg: a code sequence that speciíies íour bvte reads lor eg: a code sequence that speciíies íour bvte reads
írom íour subsequent address must not be merged into írom íour subsequent address must not be merged into
a single word read a single word read
11/2/2011 61
Data access to memory mapped I/O Data access to memory mapped I/O
1vpical requirements includes 1vpical requirements includes
· · (onstraints on memorv attributes oí the memorv mapped (onstraints on memorv attributes oí the memorv mapped
I´O .lor eg: .in the standard memorv svstem architecture I´O .lor eg: .in the standard memorv svstem architecture
.memorv locations must be uncachable and unbuííerable .memorv locations must be uncachable and unbuííerable
· · (onstraints on the sizes or alignments oí the access to the (onstraints on the sizes or alignments oí the access to the
memorv mapped I´O locations. lor eg: ií an ARM memorv mapped I´O locations. lor eg: ií an ARM
implementation has a 16 implementation has a 16--bit external bus .it might the use oí bit external bus .it might the use oí
32 32--bit access to the memorv mapped I´O locations since thev bit access to the memorv mapped I´O locations since thev
cant be períormed in a single bus cvcle cant be períormed in a single bus cvcle
· · A requirement íor additional hardware .lor eg: .an A requirement íor additional hardware .lor eg: .an
alternati·e possibilitv íor an ARM implementation with a 16 alternati·e possibilitv íor an ARM implementation with a 16
bit external bus is to allow 32 bit external bus is to allow 32--bit access to memorv .but bit access to memorv .but
require external hardware to reassemble the two 16 require external hardware to reassemble the two 16- -bit bit
accesses into a single 32 accesses into a single 32--bit access to the I´O de·ice. bit access to the I´O de·ice.
11/2/2011 62
ARM 7 ARM9 ARM 7 ARM9
(ore has Von Neumann (ore has Von Neumann
architecture .with single 32bit architecture .with single 32bit
data bus carrving both data bus carrving both
instruction and data instruction and data
(!I ~1.9 (!I ~1.9
Uses 3 stage pipeline Uses 3 stage pipeline
letch letch
Decode Decode
Lxecute Lxecute
Implements Implements BASL U!DA1LD BASL U!DA1LD
DA1A ABOR1 MODLL DA1A ABOR1 MODLL
Doesn`t implement extension Doesn`t implement extension
spaces as spaces as UNDLIINLD UNDLIINLD
(ore has lar·ard (ore has lar·ard
architecture. with separate architecture. with separate
buses íor data and instruction buses íor data and instruction
(!I~1.5 (!I~1.5
Uses 5 stage pipeline Uses 5 stage pipeline
Instruction íetch Instruction íetch
Instruction decode Instruction decode
Lxecute Lxecute
Data memorv access Data memorv access
Register write Register write
Implements Implements BASL RLS1ORLD BASL RLS1ORLD
DA1A ABOR1 MODLL DA1A ABOR1 MODLL
Implements all the Implements all the
instruction set extension instruction set extension
spaces as spaces as UNDLIINLD UNDLIINLD
11/2/2011 SHANKAR NARAYAN P.S 63
ARM ASSLMBLY LANGUAGL ARM ASSLMBLY LANGUAGL
!ROGRAMING !ROGRAMING
An Introduction to Instruction Set. An Introduction to Instruction Set.
11/2/2011 64
ARM Instruction 1ypes ARM Instruction 1ypes
32 bit ARM Instruction set. 32 bit ARM Instruction set.
16 bit 1humb instruction set. 16 bit 1humb instruction set.
(an be íurther di·ided in to íollowing tvpes. (an be íurther di·ided in to íollowing tvpes.
Data processing instructions. Data processing instructions.
Data transíer instructions. Data transíer instructions.
(ontrol ílow instructions. (ontrol ílow instructions.
(oprocessor instructions. (oprocessor instructions.
Breakpoint instructions. Breakpoint instructions.
11/2/2011 65
ARM Instruction format ARM Instruction format
U U -- Up the stack. Up the stack.
S S -- Set condition code bit. 1his savs whether the Set condition code bit. 1his savs whether the
data processing instruction should aííect the data processing instruction should aííect the
ílags or not. ílags or not.
\ \ -- write back. write back.
L L -- Load´Store. Load´Store.
N N -- Data size. Data size.
11/2/2011 66
11/2/2011 67
ARM Instruction format ARM Instruction format
Rn. Rs. Rm Rn. Rs. Rm - - Used íor sourse registers. Used íor sourse registers.
Rd Rd -- Destination registers. Destination registers.
Rdli Rdli -- Most signiíicant 32 bits oí destination Most signiíicant 32 bits oí destination
register. register.
RdLo RdLo -- Least signiíicant 32 bits oí destination Least signiíicant 32 bits oí destination
register. register.
11/2/2011 68
About the condition field. About the condition field.
Ordinarv instruction set allow branches to be Ordinarv instruction set allow branches to be
executed conditionallv. executed conditionallv.
Arm instructions contain a condition íield Arm instructions contain a condition íield
within itselí which determines whether the cpu within itselí which determines whether the cpu
is going to execute them or not. is going to execute them or not.
1he time penaltv oí not executing se·eral 1he time penaltv oí not executing se·eral
conditional instructions is usuallv less than the conditional instructions is usuallv less than the
o·erhead oí branch that would be otherwise o·erhead oí branch that would be otherwise
needed. 1he branch instructions usuallv stall the needed. 1he branch instructions usuallv stall the
pipeline which is remo·ed 3 cvcles to reíill,. pipeline which is remo·ed 3 cvcles to reíill,.
11/2/2011 69
Condition Iield Condition Iield
1he Last bits oí the opcode constitute the 1he Last bits oí the opcode constitute the
condition íield. 1hev represent the íollowing. condition íield. 1hev represent the íollowing.
11/2/2011 70
Condition Iield Condition Iield
11/2/2011 71
Data !rocessing Instructions Data !rocessing Instructions
(ontains (ontains
Arithmetic operations Arithmetic operations
(omparisons (omparisons
Logical operations Logical operations
Data Mo·ement between Registers. Data Mo·ement between Registers.
Important thing to note is that these instructions Important thing to note is that these instructions
ca33ot ror/ o3 vevory ca33ot ror/ o3 vevory thev thev ror/ o3ty o3 #egi.ter. ror/ o3ty o3 #egi.ter.
since ARM incorporates LOAD´S1ORL since ARM incorporates LOAD´S1ORL
Architecture. Architecture.
11/2/2011 72
Arithmetic Operations Arithmetic Operations
Svntax Svntax
·operation·¦·cond·}¦·S·} Rd. Rn. operand2 ·operation·¦·cond·}¦·S·} Rd. Rn. operand2
Operations are Operations are
ADD ADD -- operand1 - operand2 operand1 - operand2
AD( AD( -- operand1 - operand2 - carrv operand1 - operand2 - carrv
SUB SUB -- operand1 operand1 -- operand2 operand2
SB( SB( -- operand1 operand1 -- operand2 - carrv operand2 - carrv -- 11
RSB RSB -- operand2 operand2 -- operand1 operand1
RS( RS( -- operand2 operand2 -- operand1 - carrv operand1 - carrv -- 1 1
Re·erse subtraction is required because operand1 Re·erse subtraction is required because operand1
is alwavs a register is alwavs a register
11/2/2011 73
With Immediate Operands With Immediate Operands
Svntax Svntax
·operation·¦·cond·}¦S} Rd. Rn. 4immediate ·al ·operation·¦·cond·}¦S} Rd. Rn. 4immediate ·al
Operations are Operations are
ADD ADD -- operand1 - immediate ·alue operand1 - immediate ·alue
AD( AD( -- operand1 - immediate ·alue - carrv operand1 - immediate ·alue - carrv
SUB SUB -- operand1 operand1 -- immediate ·alue immediate ·alue
SB( SB( -- operand1 operand1 -- immediate ·alue - carrv immediate ·alue - carrv -- 11
Note : Onlv 12 bits are a·ailable to store the Note : Onlv 12 bits are a·ailable to store the
immediate operand. immediate operand.
11/2/2011 74
Immediate Operands Immediate Operands
1hen how do we put a 32 bit immediate operand · 1hen how do we put a 32 bit immediate operand ·
1he most important thing to be taken care while 1he most important thing to be taken care while
writing the 32 bit immediate operand is that it writing the 32 bit immediate operand is that it
should be a Legitimate one. should be a Legitimate one.
\hat are these legitimate immediate ·alues· \hat are these legitimate immediate ·alues·
Anv 32 bit or lesser ·alue which can be expressed as an Anv 32 bit or lesser ·alue which can be expressed as an
8 bit ·alue and a íour bit shiít. 8 bit ·alue and a íour bit shiít.
1his shiít ·alue is multiplied bv 2 beíore actuallv 1his shiít ·alue is multiplied bv 2 beíore actuallv
períorming the shiít. períorming the shiít.
11/2/2011 75
Immediate Operands Immediate Operands
Lxample MOV r0. 4096 Lxample MOV r0. 4096
Uses 0x0 as 8 bit operand and shiíts RIGl1 bv 26. Uses 0x0 as 8 bit operand and shiíts RIGl1 bv 26.
Beíore storing this 26 is stored as 26´2 ~ 13 ~ 0xD. Beíore storing this 26 is stored as 26´2 ~ 13 ~ 0xD.
1he instruction as MOV r0. 4096 is stored as. 1he instruction as MOV r0. 4096 is stored as.
So the operand speciíied must ha·e a propertv that So the operand speciíied must ha·e a propertv that
it can be expressed as it can be expressed as
·8 bit ·al· rotated right bv an LVLN amount. ·8 bit ·al· rotated right bv an LVLN amount.
20 bits for opcode and Register 20 bits for opcode and Register 0x40D 0x40D
11/2/2011 76
Immediate Operands Immediate Operands
So the ·alues that cannot be generated this wav So the ·alues that cannot be generated this wav
will cause an error will cause an error
Let us see this example Let us see this example
ADD r1. r2. 40xíí0000 Note that the ·alue is lex,. ADD r1. r2. 40xíí0000 Note that the ·alue is lex,.
Uses 0xíí ROR 16 Uses 0xíí ROR 16
So processor stores it as. So processor stores it as.
20 bits for opcode and Register 20 bits for opcode and Register 0xff8 0xff8
11/2/2011 77
Logical Operations Logical Operations
Svntax Svntax
·operation·¦·cond·}¦·S·} Rd. Rn. operand2 ·operation·¦·cond·}¦·S·} Rd. Rn. operand2
Operations are Operations are
AND AND -- operand1 AND operand2 operand1 AND operand2
LOR LOR -- operand1 LOR operand2 operand1 LOR operand2
ORR ORR -- operand1 OR operand2 operand1 OR operand2
BI( BI( -- operand1 AND NO1 operand2 | can be Bit clear| operand1 AND NO1 operand2 | can be Bit clear|
11/2/2011 78
Comparisons Comparisons
Onlv eííect is to update the condition ílags thus Onlv eííect is to update the condition ílags thus
no need to set S bit. 1hev don`t write the result. no need to set S bit. 1hev don`t write the result.
Svntax Svntax
·operation·¦·cond·}Rn. operand2 ·operation·¦·cond·}Rn. operand2
Operations are Operations are
(M! (M! -- operand1 operand1 -- operand2 operand2
(MN (MN -- operand1 - operand2 operand1 - operand2
1S1 1S1 -- operand1 AND operand2 operand1 AND operand2
1LO 1LO -- operand1 LOR operand2 operand1 LOR operand2
11/2/2011 79
Branch Instructions Branch Instructions
1vpe1 1vpe1 -- Branch to a label Branch to a label
Svntax Svntax -- B¦·cond·} Label B¦·cond·} Label
Oííset íor the branch is calculated bv the Oííset íor the branch is calculated bv the
assembler in íollowing wav once a branch assembler in íollowing wav once a branch
instruction is encountered. instruction is encountered.
Oííset ~ addr oí branch inst Oííset ~ addr oí branch inst -- |target addr |target addr -- 8| 8|
--8 is to account íor the pipeline which !( handles. 8 is to account íor the pipeline which !( handles.
1he oííset can be up to 26 bits. 1his oííset is alwavs 1he oííset can be up to 26 bits. 1his oííset is alwavs
obtained with bottom 2 bits 0. 1hus 26 bit oííset is obtained with bottom 2 bits 0. 1hus 26 bit oííset is
right shiíted bv 2 and stored in instruction encoding. right shiíted bv 2 and stored in instruction encoding.
1he Range is 1he Range is ii 32 MB. 32 MB.
11/2/2011 80
Branch Instructions Branch Instructions
1vpe2 1vpe2 -- Branch to a subroutine (alled Branch Branch to a subroutine (alled Branch
with Link, with Link,
Svntax Svntax -- BL¦·cond·} Sub_routine_label. BL¦·cond·} Sub_routine_label.
BL is identiíied using the link bit in the opcode. BL is identiíied using the link bit in the opcode.
Implements a subroutine call bv writing !( Implements a subroutine call bv writing !( --
to Link Register lr, oí the current bank. to Link Register lr, oí the current bank.
Note that this will put the address oí the next Note that this will put the address oí the next
instruction íollowing the branch. since !( is ahead instruction íollowing the branch. since !( is ahead
bv 3 instructions bv 3 instructions..
1o return írom the subroutine we simplv need 1o return írom the subroutine we simplv need
to restore !( írom LR. Mo· pc. lr, to restore !( írom LR. Mo· pc. lr,
11/2/2011 81
1he Barrel Shifter 1he Barrel Shifter
ARM does not support independent shiít ARM does not support independent shiít
instructions. Instead it supports a Barrel Shiíter instructions. Instead it supports a Barrel Shiíter
which can pro·ide shiíts as a part oí other which can pro·ide shiíts as a part oí other
instructions. instructions.
Barrel Shiíter supports se·eral actions like Barrel Shiíter supports se·eral actions like
Leít shiít Leít shiít
Right shiíts Right shiíts
Rotations Rotations
11/2/2011 82
Barrel Shifter Barrel Shifter ÷÷ Left Shift Left Shift
Shiíts the II operand in the instruction to its leít. Shiíts the II operand in the instruction to its leít.
bv speciíied amount. bv speciíied amount.
Svntax Svntax
·data processing instruction·. LSL ·immediate No.· ·data processing instruction·. LSL ·immediate No.·
·data processing instruction·. LSL ·register· ·data processing instruction·. LSL ·register·
Lxample Lxample
ADD r0. r1. r1. LSL 42 ADD r0. r1. r1. LSL 42
Means r0 ~ r1 - r1 Means r0 ~ r1 - r1
11/2/2011 83
Barrel Shifter Right Shifts Barrel Shifter Right Shifts
Logical shiít right LSR, Logical shiít right LSR,
Di·ides bv power oí two Di·ides bv power oí two
Used with other instructions as in case oí LSL Used with other instructions as in case oí LSL
Di·ides bv power oí two Di·ides bv power oí two
Lxample Lxample
LSR 45 is di·iding bv 32 LSR 45 is di·iding bv 32
Svntax similar to leít shiít. Svntax similar to leít shiít.
11/2/2011 84
Barrel Shifter Right Shifts Barrel Shifter Right Shifts
Arithmetic shiít right ASR,. Arithmetic shiít right ASR,.
Shiíts right. and preser·es the sign bit íor 2`s Shiíts right. and preser·es the sign bit íor 2`s
complement operations. complement operations.
i.e. it copies the last bit to the remaining bits. i.e. it copies the last bit to the remaining bits.
Used with other instructions as in case oí LSR Used with other instructions as in case oí LSR
11/2/2011 85
Barrel Shifter Barrel Shifter Rotations Rotations
Rotate Right ROR,. Rotate Right ROR,.
Similar to LSR but the bits which lea·es the LSB oí Similar to LSR but the bits which lea·es the LSB oí
the register appear as the MSB oí the register. the register appear as the MSB oí the register.
1he bit which lea·es the LSB is also copied to the 1he bit which lea·es the LSB is also copied to the
(l (l
Used with other instructions similar to the shiít Used with other instructions similar to the shiít
instructions. instructions.
Rotate Right Lxtended RRX,. Rotate Right Lxtended RRX,.
Similar to rotate right but uses the carrv as the 33 Similar to rotate right but uses the carrv as the 33
rd rd
bit. bit.
11/2/2011 86
Barrel Shifter Barrel Shifter
LSL LSL
LSR LSR
RLGIS1LR
(l
0
RLGIS1LR
0
(l
11/2/2011 87
Barrel Shifter Barrel Shifter
ASR ASR
ROR ROR
RLGIS1LR (l
RLGIS1LR (l
11/2/2011 88
Barrel Shifter Barrel Shifter
RRX RRX
Rotate Right through (arrv, Rotate Right through (arrv,
RLGIS1LR (l
11/2/2011 89
Multiplication Instructions Multiplication Instructions
1here are two multiplication instructions. 1here are two multiplication instructions.
Multiplv Multiplv
Svntax : MUL ¦·cond·}¦S} Rd. Rm. Rs Svntax : MUL ¦·cond·}¦S} Rd. Rm. Rs
Rd ~ Rm Rs Rd ~ Rm Rs
Multiplv and accumulate Multiplv and accumulate
Does addition along with multiplication with the third Does addition along with multiplication with the third
register operand speciíied. and stores the end result in the register operand speciíied. and stores the end result in the
destination. destination.
Svntax : MLA¦·cond·}¦S} Rd. Rm. Rs. Rn Svntax : MLA¦·cond·}¦S} Rd. Rm. Rs. Rn
Rd ~ Rm Rs, - Rn Rd ~ Rm Rs, - Rn
11/2/2011 90
Limitations of MUL Limitations of MUL
Rd and Rm cannot be the same register. Rd and Rm cannot be the same register.
(annot use program counter. (annot use program counter.
Operands can be considered signed or unsigned. Operands can be considered signed or unsigned.
the user should interpret correctlv the user should interpret correctlv
11/2/2011 91
Data Movement Data Movement
1he MOV instruction 1he MOV instruction
Svntax : MOV¦·cond·}¦S} Rd. operand2 Svntax : MOV¦·cond·}¦S} Rd. operand2
Mo·es operand 2 into destination register. Mo·es operand 2 into destination register.
Note that there is no use oí operand1 which means Note that there is no use oí operand1 which means
that there can be an immediate data. that there can be an immediate data.
1he MVN instruction 1he MVN instruction
Svntax same as the MOV instruction Svntax same as the MOV instruction
Mo·es NO1 operand2 into destination register. Mo·es NO1 operand2 into destination register.
11/2/2011 92
Load Store Instructions Load Store Instructions
1he ARM is a load store architecture 1he ARM is a load store architecture
Does not support memorv to memorv data processing Does not support memorv to memorv data processing
Must mo·e to registers beíore using them. Must mo·e to registers beíore using them.
!rocess becomes much íaster due to register access to !rocess becomes much íaster due to register access to
process data. process data.
1here are three sets oí instructions which can 1here are three sets oí instructions which can
interact with main memorv. thev are interact with main memorv. thev are
Single register data transíer Single register data transíer
Block data transíer Block data transíer
Single data swap Single data swap
11/2/2011 93
Single Register Data 1ransfer Single Register Data 1ransfer
Load or store a word LDR´S1R, Load or store a word LDR´S1R,
Svntax : ·LDR´S1R·¦·cond·} Rd´Rs. ·address· Svntax : ·LDR´S1R·¦·cond·} Rd´Rs. ·address·
lor LDR Rd and íor S1R Rs as a case mav be lor LDR Rd and íor S1R Rs as a case mav be
·address· oí the memorv can be expressed in manv ·address· oí the memorv can be expressed in manv
addressing modes which will be discussed shortlv. addressing modes which will be discussed shortlv.
Load or store a bvte Load or store a bvte
Svntax : ·LDR´S1R·¦·cond·}¦B} Rd´Rs.·address· Svntax : ·LDR´S1R·¦·cond·}¦B} Rd´Rs.·address·
Note that B is to be attached aíter condition ií anv. Note that B is to be attached aíter condition ií anv.
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Single Register Data 1ransfer Single Register Data 1ransfer
ARM architecture ·ersion also adds support íor ARM architecture ·ersion also adds support íor
halí words. halí words.
Svntax : ·LDR´S1R·¦·cond·}¦l} Rd´Rs.·address· Svntax : ·LDR´S1R·¦·cond·}¦l} Rd´Rs.·address·
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Addressing Modes Addressing Modes
Register Indirect addressing mode Register Indirect addressing mode
Address oí the source Memorv location íor Load, Address oí the source Memorv location íor Load,
or the destination memorv location íor Store, as a or the destination memorv location íor Store, as a
case mav be. is gi·en bv the contents oí an internal case mav be. is gi·en bv the contents oí an internal
register. register.
Lxamples: Lxamples:
S1R ro. |r1| S1R ro. |r1|
LDR r2. |r1| LDR r2. |r1|
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Addressing Modes Addressing Modes
S1R r0. |r1| works this wav. S1R r0. |r1| works this wav.
..
..
..
0x5 0x5
..
..
..
..
..
0xJ00
0x5
0xJ00
Ro
RJ
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Indexed Addressing Indexed Addressing
Instructions in ARM are capable oí accessing a Instructions in ARM are capable oí accessing a
location oííset írom the base address speciíied. location oííset írom the base address speciíied.
1his oííset can be 1his oííset can be
An unsigned 12 bit immediate ·alue. An unsigned 12 bit immediate ·alue.
A register. optionallv shiíted using barrel shiít. A register. optionallv shiíted using barrel shiít.
Added or subtracted írom the base register. Added or subtracted írom the base register.
Applied beíore transíer : !re Applied beíore transíer : !re -- indexed Addressing. indexed Addressing.
Applied aíter transíer : !ost Applied aíter transíer : !ost -- indexed Addressing. indexed Addressing.
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!re !re ÷÷ Indexed Addressing Indexed Addressing
Lxample : LDR r0.|r1. 412| Lxample : LDR r0.|r1. 412|
Oííset addition |r1| - 12 is done beíore transíer Oííset addition |r1| - 12 is done beíore transíer
1ransíer to r0 is made írom the 1ransíer to r0 is made írom the newly available newly available address. address.
y aeta:tt tbe ba.e regi.ter r] i. 3ot :5aatea. y aeta:tt tbe ba.e regi.ter r] i. 3ot :5aatea.
1o update the base register. use LDR r0. |r1.412|! 1o update the base register. use LDR r0. |r1.412|!
LDR r0. |r1.r3| can be used ií r3 contains 12. LDR r0. |r1.r3| can be used ií r3 contains 12.
LDR r0. |r1.r3.LSL 42| can be used ií r3 contains 3. LDR r0. |r1.r3.LSL 42| can be used ií r3 contains 3.
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!re !re ÷÷ Indexed Addressing Indexed Addressing
low LDR r0.|r1. 412| works · low LDR r0.|r1. 412| works ·
..
..
..
0x5 0x5
..
..
..
..
..
0xJ00
0x5
0xJ0C
Ro
RJ
J2
offset
+
RJ
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!ost !ost ÷÷ Indexed Addressing Indexed Addressing
Lxample : LDR r0.|r1|. 412 Lxample : LDR r0.|r1|. 412
Oííset addition |r1| - 12 is done aíter transíer Oííset addition |r1| - 12 is done aíter transíer
1ransíer to r0 is made írom the 1ransíer to r0 is made írom the current current address. address.
y aeta:tt tbe ba.e regi.ter r] i. :5aatea. y aeta:tt tbe ba.e regi.ter r] i. :5aatea.
Makes sense onlv when there is updating. Makes sense onlv when there is updating.
LDR r0. |r1|. 4 LDR r0. |r1|. 4--12 can be used to go to 0xí. 12 can be used to go to 0xí.
LDR r0. |r1.r3.LSL 42| can be used ií r3 contains 3. LDR r0. |r1.r3.LSL 42| can be used ií r3 contains 3.
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!ost !ost ÷÷ Indexed Addressing Indexed Addressing
low LDR r0.|r1|. 412 works· low LDR r0.|r1|. 412 works·
..
..
..
0x5 0x5
..
..
..
..
..
0xJ00
0x5
0xJ00 Ro
RJ
J2
offset
+
0xJ0C
RJ
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Block Data 1ransfer Block Data 1ransfer
1he Load or Store Multiple instructions allow us to 1he Load or Store Multiple instructions allow us to
transíer data írom or into registers b´w 1 and 16. transíer data írom or into registers b´w 1 and 16.
1ransíerred registers can be either 1ransíerred registers can be either
Subset oí current bank Subset oí current bank
Anv subset oí user mode registers when in a pri·ileged Anv subset oí user mode registers when in a pri·ileged
mode. mode.
1hev are ·erv eííicient íor sa·ing and restoring context. 1hev are ·erv eííicient íor sa·ing and restoring context.
Mo·ing large blocks oí data around memorv Mo·ing large blocks oí data around memorv
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Block Data 1ransfer Block Data 1ransfer
1hese are íew instructions used. 1hese are íew instructions used.
LDMIA´S1MIA : LDMultiple´S1Multiple, LDMIA´S1MIA : LDMultiple´S1Multiple,
Increment Aíter Load´Store,. Increment Aíter Load´Store,.
Lxamples: Lxamples:
LDMIA r0.¦r2 LDMIA r0.¦r2 --r9} r9}
Means Means
Load registers r2 to r9 with data present in 8 Load registers r2 to r9 with data present in 8
successi·e locations whose I address Base successi·e locations whose I address Base
address, is in r0. Increment r0 aíter load. ro is not address, is in r0. Increment r0 aíter load. ro is not
updated updated
Arm supports manv oí these kind which will Arm supports manv oí these kind which will
be listed out shortlv. be listed out shortlv.
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Stacks Stacks
Stack is an area oí the memorv which works on Stack is an area oí the memorv which works on
the LIlO algorithm. the LIlO algorithm.
1wo pointers deíine the current limits oí the 1wo pointers deíine the current limits oí the
stack. stack.
1he base pointer which points to the bottom oí the 1he base pointer which points to the bottom oí the
stack stack
1he stack pointer which points to current 1O! oí 1he stack pointer which points to current 1O! oí
the stack. the stack.
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Stacks Stacks
!USl ~ I Decrement and then push. !USl ~ I Decrement and then push.
!O! ~ I !O! and then Increment. !O! ~ I !O! and then Increment.
33
22
11
S!
S!
INI1IAL After !USH {J,2,3]
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Stacks Stacks
1he !O! operation 1he !O! operation
33
22
11
S!
INI1IAL
22
11
S!
After !O! 3
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Stacks Stacks
Usual procedure is that the stack grows in size as Usual procedure is that the stack grows in size as
what is alreadv seen. ARM readilv supports this. what is alreadv seen. ARM readilv supports this.
In addition to this ARM supports the íollowing In addition to this ARM supports the íollowing
tvpes oí stack. tvpes oí stack.
lull Descending stack lull Descending stack
lull Ascending stack lull Ascending stack
Lmptv Descending stack Lmptv Descending stack
Lmptv Ascending stack Lmptv Ascending stack
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Stack Lxamples Stack Lxamples
33
22
11
33
22
11
0xJ06
0xJ05
0xJ00
.
.
.
.
.
.
.
.
Initial S!
S!
Initial S!
S!
IULL DLSCLNDING
LM!1Y DLSCNDING
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Stack Lxamples Stack Lxamples
11
22
33
11
22
33
0xJ06
0xJ05
0xJ00
.
.
.
.
.
.
.
.
S!
Initial S!
S!
Initial S!
LM!1Y DLSCLNDING
IULL ASCLNDING
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Stacks Stacks
1he multiple Load´Store instructions can also 1he multiple Load´Store instructions can also
be used to transíer the data írom or to the stack. be used to transíer the data írom or to the stack.
Depending on the tvpe oí stack we ha·e the Depending on the tvpe oí stack we ha·e the
íollowing íorms. íollowing íorms.
S1MlD´LDMlD S1MlD´LDMlD
S1MlA´LDMlA S1MlA´LDMlA
S1MLD´LDMLD S1MLD´LDMLD
S1MLA´LDMLA S1MLA´LDMLA
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Block Data 1ransfer Block Data 1ransfer
!utting it all together we ha·e. !utting it all together we ha·e.
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Block Data 1ransfer Block Data 1ransfer
lew tips while using block data transíer. lew tips while using block data transíer.
1he base register in the instruction can be updated 1he base register in the instruction can be updated
each time using ! Svmbol each time using ! Svmbol
Lxample : S1MlD sp!. ¦r0 Lxample : S1MlD sp!. ¦r0 -- r12} r12}
1he destination register set need not be continuous 1he destination register set need not be continuous
one. \e can speciív diííerent registers using . one. \e can speciív diííerent registers using .
Lxample : LDMIA r0. ¦r1.r.r6} Lxample : LDMIA r0. ¦r1.r.r6}
Lxample : LDMA r0. ¦r1. r3 Lxample : LDMA r0. ¦r1. r3 -- r5} r5}
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Control Ilow Instructions Control Ilow Instructions
1he íollowing are to be discussed. 1he íollowing are to be discussed.
Branch Instructions Branch Instructions
(onditional branch instructions. (onditional branch instructions.
Branch and link instructions Branch and link instructions
Subroutines. Subroutines.
Super·isor calls Super·isor calls
Jump calls. Jump calls.
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Control Ilow Instructions Control Ilow Instructions
1he unconditional branch 1he unconditional branch
B Label : Branch unconditionallv to the speciíied B Label : Branch unconditionallv to the speciíied
label. label.
1he conditional branch instruction. 1he conditional branch instruction.
B·condition· Label. B·condition· Label.
Branches to speciíied label depending on the Branches to speciíied label depending on the
condition speciíied. condition speciíied.
(onditions are same as listed in íirst 1able. (onditions are same as listed in íirst 1able.
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Control Ilow Instructions Control Ilow Instructions
1he BL instruction. 1he BL instruction.
Stores the current return address in r1 Link register, Stores the current return address in r1 Link register,
and then shiíts the control to the subroutine as alreadv and then shiíts the control to the subroutine as alreadv
seen. seen.
Ií there is a call to a subroutine within another Ií there is a call to a subroutine within another
subroutine then the original address is pushed on to subroutine then the original address is pushed on to
the stack and current return address is stored in r1. the stack and current return address is stored in r1.
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Supervisor calls Supervisor calls
\hene·er there is a need íor input and an \hene·er there is a need íor input and an
output then it has to be done using super·isor output then it has to be done using super·isor
calls. which calls special subroutines using a calls. which calls special subroutines using a
special interrupt called S\I which stands íor special interrupt called S\I which stands íor
the Soítware Interrupt. the Soítware Interrupt.
Some useíul S\I. Some useíul S\I.
S\I S\I_write( S\I S\I_write(
S\I S\I_Lxit S\I S\I_Lxit
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ump 1ables ump 1ables
1he Idea oí a jump table is that a programmer 1he Idea oí a jump table is that a programmer
sometime wants to call one among a set oí sometime wants to call one among a set oí
subroutines depending on a ·alue computed. subroutines depending on a ·alue computed.
Lxample Lxample
BL jumptable BL jumptable
...... ......
Jumptable Jumptable
(M! r0.40 (M! r0.40
BLO íun1 BLO íun1
(M! r0.41 (M! r0.41
BLO íun2 BLO íun2
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Swap Swap
1he ARM instruction set has two swap 1he ARM instruction set has two swap
instructions. instructions.
Swap S\!, Swap S\!,
Swap Bvte S\!B, Swap Bvte S\!B,
Svntax : S\!¦·cond·}¦B} Rd. Rm. |Rn| Svntax : S\!¦·cond·}¦B} Rd. Rm. |Rn|
Lxample : Lxample :
S\! r12. r10. |r9| means S\! r12. r10. |r9| means
Load r12 írom address r9 and store r10 to address r9 Load r12 írom address r9 and store r10 to address r9
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Swap Swap
Ií we use the same instruction on a single Ií we use the same instruction on a single
register as shown then swap is achie·ed register as shown then swap is achie·ed
S\! r1. r1. |r2| S\! r1. r1. |r2|
Lxchanges ·alue in r1 and memorv whose address is Lxchanges ·alue in r1 and memorv whose address is
in r2 in r2
Bvte exchange works on similar lines. Bvte exchange works on similar lines.
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1he 1humb Instruction Set 1he 1humb Instruction Set
1he 16 bit instruction set 1he 16 bit instruction set
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1humb Instruction Set 1humb Instruction Set
It is a re It is a re--encoded subset oí ARM instruction set. encoded subset oí ARM instruction set.
Designed to increase the períormance oí the Designed to increase the períormance oí the
ARM implementations. which use a 16 bit or ARM implementations. which use a 16 bit or
narrower memorv data bus and allow better narrower memorv data bus and allow better
code densitv than ARM. code densitv than ARM.
1humb execution is ílagged bv 1 Bit bit|5|, in 1humb execution is ílagged bv 1 Bit bit|5|, in
the (!SR. the (!SR.
1~~0 ARM mode. 1~~0 ARM mode.
1~~1 1humb Mode. 1~~1 1humb Mode.
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A Glance at C!SR A Glance at C!SR
1he (!SR holds 1he (!SR holds
(opies oí ALU status ílags. (opies oí ALU status ílags.
(urrent processor state. (urrent processor state.
Interrupt disable ílags Interrupt disable ílags..
NN ( ( V V Unused Unused I I ll 11 Mode Mode
3J 30 29 28 27 8 7 6 5 4 0
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Lntering 1humb State Lntering 1humb State
1humb execution is entered bv executing an 1humb execution is entered bv executing an
ARM BX instruction Branch and Lxchange, ARM BX instruction Branch and Lxchange,
1his instruction branches to the address held in a 1his instruction branches to the address held in a
general purpose register and ií the bit|0| oí that general purpose register and ií the bit|0| oí that
register is a 1 1humb execution begins at the register is a 1 1humb execution begins at the
branch target address. branch target address.
Ií bit|0| is a 0 ARM execution continues írom a Ií bit|0| is a 0 ARM execution continues írom a
branch target address. branch target address.
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1humb Model 1humb Model
1humb instruction set gi·es íull access to the 1humb instruction set gi·es íull access to the
eight Lo` general purpose registers r0 to r¯ and eight Lo` general purpose registers r0 to r¯ and
makes use oí the rest as íollows. makes use oí the rest as íollows.
r13 is used as stack pointer. r13 is used as stack pointer.
r1 is the link register. r1 is the link register.
r15 is used as !(. r15 is used as !(.
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1humb ARM Differences 1humb ARM Differences
Most 1humb instructions are executed un Most 1humb instructions are executed un--
conditionallv where as condition can be íixed to conditionallv where as condition can be íixed to
all the arm instructions. all the arm instructions.
Manv data processing instructions are in the two Manv data processing instructions are in the two
address íormat. i.e. one oí the source register address íormat. i.e. one oí the source register
also acts as the destination register. also acts as the destination register.
Better code densitv than arm. Better code densitv than arm.
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Data !rocessing Instructions Data !rocessing Instructions
Data processing instructions on the Lo registers. Data processing instructions on the Lo registers.
i.e. registers r0 to r¯. i.e. registers r0 to r¯.
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1he Data !rocessing Instruction 1he Data !rocessing Instruction
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1he Compares 1he Compares
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Logical Instructions Logical Instructions
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Load Instructions Load Instructions
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Store Instructions. Store Instructions.
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Store Instructions Store Instructions

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