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**1999. 10 Jun Dong Cho Sungkyunkwan Univ. Dept. ECE Mail : Jdcho@skku.ac.kr Homepage : vada.skku.ac.kr
**

1

Agenda

The Issues of Clock Tree Synthesis The Basic Consideration of Clock Tree Synthesis Traditional Clock Routing Algorithm Recent Approaches in Clock Tree Synthesis

2

**The Issues of Clock Tree Synthesis
**

Global Distribution of Clocks and Power Consideration of Timing/Density/Clock/Power Clock Management Scheme Clock Power Reduction Clocking Techniques in Deep Submicron Design Multiple Clock Design Need of PLL

3

Global Distribution of Clocks and Power (1)

When ASICs are built on a deep submicron process with over tens of million gates and a clock frequency below 1GHz, the designer must consider many details in the clock and power circuitry. Normally these circuit elements are not given much thought; power is drawn from the rails drawn across the top and bottom of the page, and the clock has ideal characteristics: a square wave running at the specified frequency. In reality, many other effects need to be evaluated in the clocking and power distribution areas of the design when the total chip power consumption will be in the range of tens to over 100 W and the clock power can be as much as half of the total power consumption. The clocking scheme cannot be assumed to be a clean, uniform signal network. It might be a complicated distribution structure with architectures ranging from a large distributed clock buffer for the high-performance chips to a complex system with multiple derived sub-clocks to help manage power consumption.

4

Global Distribution of Clocks and Power (2)

The interaction between clocks and power consumption may require the ability to generate clock signals which can be stopped in the inactive sections to minimize power consumption. The power and ground system will take up about half of the available package pins to be able to handle the tens of amperes of average current consumed by the IC. Many side effects of the basic IC process will have to be addressed to make the chip meet all the requirements of speed, power, and silicon area. If the supply voltage is reduced to take advantage of the power savings available at a lower supply voltage, noise margins and leakage currents may become significant problems. The various secondary effects within the system, like voltage drops on the supply lines, ground bounce, crosstalk, and glitches, may exacerbate the problems by adding enough noise to the system to decrease the clock slew rates and the clock rise and fall times.

5

Consideration of Timing/Density/Clock/Power (1) This further exacerbates the power consumption problems by making the big clock buffers stay in the high current linear portions of their transfer curves for greater amounts of each clock cycle. and getting operating power to all active circuit elements. supplying sufficient clock drive to operate all of the clocked elements in the system. power consumption. adding large power surges and a very large potential for crosstalk and interference to the clock and power distribution subsystems. 6 . In addition. the clock network has many signals switching simultaneously. The problems with skew and the process of balancing the delays across the chip occur in parallel with the increases in density and complexity. For single-frequency clock systems. The most basic problems facing designers are managing the skew in the clock system (which entails getting the clock everywhere at the same time). and area. the tradeoffs are speed.

Clock creation after placement adds area and affect density. marketing director of the IC design group of Cadence Design Systems (San Jose. Clock generation before placement yields high skew. CA). density. notes that the timing. Post placement ECOs may require clock redesign. 7 . and power are intricately related in the following ways: Downsizing cells to reduce power may degrade timing. Timing-driven placement may increase wire length and power. Large load count yields high clock delay and affects timing. Upsizing cells to improve timing degrades power and area. clock. Clock creation without wire delays affects power and delay.Consideration of Timing/Density/Clock/Power (2) Tom Katsioulas.

The amount of time available after accounting for clock skew and set-up and hold times leaves very little time for buffer and propagation delays. as well as noise problems due to the large current spikes generated when the buffers switch. 8 . An alternative approach is to distribute the buffers into the clock tree. This reduces the power consumption by requiring buffers of smaller size and also helps the reliability aspects by reducing the size of the current spike. The large clock buffers lead to high power consumption. high speed circuits are associated with the physics of the devices and interconnections. the clock period is only 4ns.Clock Management Scheme (1) Some of the clocking problems of complex. At 250 MHz. often as large as 30 to 50 percent of the total chip power consumption.

which generates glitches and power surges at the end of each clock cycle. "the software tries to make all paths the same length. a senior architect at Epic Design Technology (Santa Clara. The careful analysis of the signal paths relative to the clocks is critical to making a working integrated circuit. This makes all data paths complete at the same time. CA).Clock Management Scheme (2) The clock system and the wide word datapaths all switching at the same time increase the possibility for glitches and higher peak switching currents. This effect gets worse at higher speeds. They put additional loads on the power delivery systems. "In synthesized circuits." 9 . The resulting datapath skews will require close scrutiny of the datapath localization and grouping." says Charlie Xiaoli Huang. as well as careful analysis of pipeline lengths.

If the gate is used in place of a buffer in the clock tree section. For example. Obviously. the clock tree does not require an additional level of buffers to match the delays due to the extra gate levels. area. The areas for compromise are power. this keeps the clocks from toggling the inputs of sections with no data changes. with the understanding that the gate delay will exacerbate the clock skew and clock edge uncertainty for those sections. The tradeoff would be in a clock system which draws up to half of the total system current. Why have a 250 MHz clock for a serial I/O channel controller? This could save some more power since the frequency term in the power equation has now been reduced for much of the on-chip circuitry. The sections will get clocks appropriate for their functions. An intermediate solution might be a multiply driven clock spine If all of the circuitry did not need to run at same speed. a single point clock with sufficient buffers to drive all the circuitry would be the best choice.Clock Management Scheme (3) Clocking schemes and power distribution are going to be affected by the system requirements. 10 . If one of the areas is defined as much more critical than the others. and performance. derived multiple clocks could be generated from the master reference clock. it will drive the design. if the designer gates the clock signals to unused sections of the chip. if performance is the key parameter.

Analyzing the intricacies of multiple clock interactions requires more detail and different techniques than is available in the standard ASIC flow. This additional on-chip capacitance reduces the effects of the synchronous power surges and the associated noise on the power and ground lines. 11 . If power consumption is minimized in the design through whatever techniques are available. it ameliorates the power distribution problems. The additional metal to the distributed local decoupling devices helps to reduce total supply and ground resistance. Other areas would have lower-speed clocks and gated clocks and power-down circuitry to minimize the capacitive charging currents. The use of the "unused" gates as local decoupling capacitors mitigates the package isolation problems and minimizes the local IR drops. with multiple frequencies so only those circuits requiring extremely high performance would get the highest-speed clocks. which reduces the potential for electromigration and improves overall manufacturability. then the complicated scheme described in the introduction should be considered. This could be multiple clocks.Clock Power Reduction If power consumption and/or management is the most important concern.

Its benefit is that it can reduce both skew and latency. latency is reduced because fewer layers of buffer trees are needed to drive the clock net from multiple ends. small latency and power usage. minimizing the skew. thereby reducing the effective distance between drivers and clock signal receivers (otherwise known as flip-flops). also known as a multiply-driven clock spine network. the clock signal arrival time difference between the first flip-flop and the last flip-flop is much smaller. One innovative approach is a clock network driven from multiple clock driver pads. Additionally. In multiply-driven clock networks. 12 .Clocking Techniques in Deep Submicron Design (1) Physical implementation of a clock network requires novel approaches to balance the tradeoffs between minimization of skew. One reason this technique produces low skew is because the clock signal is driven from multiple points on the chip.

then let the software move the virtual flip-flops to optimal locations based on the actual logic use. When people try to get the logic interconnections first.Clocking Techniques in Deep Submicron Design (2) Physical design manager Herman Lam of Fujitsu (San Jose. For high performance functions. a large clock buffer driving a minimum size clock tree is the best way to accomplish the clocking. They place virtual flip-flops at the ends of the clock lines for loads. then try to balance the clock trees for matched delays. 13 . After place and route of the design the RC values for the clock network are extracted and measured. CA). then the rest of the signals. says that they are encouraging place and route of the clock system first. the resulting circuit has a much larger clock tree and its associated parasitics which increase power consumption. This may be done with a clock tree place and route tool or manually inserted in physical layout of the design. Clock networks for deep submicron designs are typically inserted during physical layout.

14 . Multiply-driven clock networks can be designed with very small skew and latency. but special tools beyond RC extraction and analysis are required to ensure that such networks meet the requirements of high-performance deep submicron designs.Multiple Clock Design Multiply-driven clock spine network delays are very difficult to model because analytical RC algorithms only work for a net with a single driver. This method totally breaks down for more than a few drivers which drive a single clock net. but the Spice results must be manually analyzed and backannotated to timing analysis tools. Circuit (Spice) simulation has been used as an alternative to analyze multiple driven clock nets. For accurate skew and latency analysis. special EDA tools are needed to model multiply-driven clock networks automatically and the extracted data needs to be back-annotated to timing analysis tools. One alternative is a manual solution that breaks the multiply driven net into multiple subnets and extracts the subnet segments for RC analysis.

The jitter errors add to the total clock skew. However. According to John Harrington. PLLs consume a lot of power making them less attractive for low power applications. ASIC product manager at Hitachi America (Brisbane. manager of ASIC products at AT&T Microelectronics (Reading. One caveat is that one must monitor the phase jitter and noise associated with the PLL and clock regeneration circuitry. This can help by reducing external clock frequencies and allow lower cost crystals which can normally go up to 40 MHz. Three-fourths of their designs have a PLL to synchronize and or align clock edges." 15 . For multiple clocks. "PLLs are useful for clock doublers and triplers [and other multiples]. noting."We try to add PLLs to compensate and resync the clocks where possible. The jitter and synchronization can create repeatable phase relationships within the clock network for continuous signals. PA). The PLL can develop a clock with zero or even negative effective skew by adjusting the phase comparator response. The designer needs to be careful of PLL latency and lock times for those situations where the clock is not continuous." Jim Smith. CA).Need of PLL A phase-locked loop (PLL) is useful to resynchronize clocks and to generate multiples of the base system clock. agrees. the problem is the latency and lock times for the clocks as well as the added jitter errors.

The Basic Consideration of Clock Tree Synthesis Basic Feature of Clock Skew Consideration of Synchronous Design Design Style Specific Problems 16 .

TGATE(min) + TRC(min) . t. and t = time for one period of the clock The clock. 17 .Basic Feature of Clock Skew Circuit operation speed is increasingly limited by clock skew which is the maximum difference in arrival times of the clocking signal at the logic gates.THOLD(max) > TSKEW TGATE(max) + TRC(max) + TSETUP(max) + TSKEW < t where: TGATE = signal propagation delay from clock input to data output of a logic gate TRC = signal propagation delay because of metalinterconnect RC effects between for a logic gate THOLD = data-valid hold time requirement for for a logic gate TSETUP = data-valid setup time requirement for for a logic gate TSKEW = maximum amount of skew between clock signals. Figure shows the definition of clock skew. TSKEW. The goal of balance clock tree distribution is to make the clock skew. in most VLSI ASIC design is getting faster and tolerance of THOLD and TSETUP is getting smaller. as small as possible. This is seen from the below inequality governing the clock period of a clock signal net. In deep submicron and submicron technologies. the effect of TRC becomes important.

in submicron and deep submicron technologies. Y3. 18 . this circuit will produce correct output. logic gate delay is no longer the sole cause of delay. Figure illustrates that the unequal length distance of wires from the clock source to the D-flip flops will not contribute much unbalance wire delay in nonsubmicron technology. A and B. This is because in nonsubmicron technology the main delay and cause of skew is due to propagation delay of logic gates. arrive at both identical D flip-flops simultaneously.Consideration of Synchronous Design Assuming signals. The wire delay can be neglected compared to logic gate delay. The wire distance between logic gates can cause substantial delay. clock skew will occur. However. as well as the clock signal reaches the D flip flops within t seconds. Since the distance from the clock source to the clock input of the D flip-flop D1 is longer than the distance from the clock source to the clock input of D flip. Y3 may generate incorrect results due to the clock skew. if the circuit is built on non-submicron technology. The wire load delay also contributes a large proportion of delay.flop D2.

The algorithms for clock routing in such symmetric structures have been well studied and well analyzed. If a dedicated layer is available for routing with free of obstacles. Gate Array : Gate arrays are symmetrically arranged in a plane and allow the clock to be routed in a symmetric manner as well. Conventional methods do not work in standard cell design since terminals are neither uniformly distributed (as in full-custom). 19 . we refer to that problem as the BBCRP(Building Block Clock Routing problem) : minimizing both total delay and skew and constraint(wires does not intersect with any rectangles) exists. Standard Cell : The clock routing problem in standard cell designs is somewhat easier than full-custom in some aspects. But. clock lines have to be routed in channels and feedthroughs.Design Style Specific Problems Full Custom : The clock routing problem in full custom style depends on the availability of a routing layer for clocks. the clock routing problem in full custom design is exactly the same as CRP(Clock Routing Problem) : minimizing total delay and minimizing skew between buffer. Since. nor are they symmetric in nature(as in gate array). if obstacles are present.

If the period of time for passing signals down a level is identical for all children nodes. 20 . then all children nodes will receive the signal from the root (parent) node at the same instant. It can minimize the clock skew and ensure that the clock signals arriving at any logic gates are within the clock skew specification.Balanced Clock Tree A balanced clock tree distribution is the fundamental requirement for synchronous systems. A typical balanced clock tree is like a binary tree where all children nodes at the same level have the same distance from the root (parent) node.

It shortens the length of clock feed line for more clock needed component.Load Balancing Load balancing method is the method which balances the clock delay by the number of clock needed component. It can equalize the delay of clock by the method that If one node has more clock needed component than the other side. And assign long clock feed line for less clock needed component. 21 . Then.

Load Balancing using Elmore Delay 22 .

Load Balanced Clustering 23 .

Balanced Tree + Mesh 24 .

Distributed 25 .Single vs.

Then all signal paths will experience the same delay. The delay time can be equalized for all logic gates by adding logic gate delay and interconnect delay to the faster signal paths. This approach not only has a near zero clock skew. However. 26 . Logic gates are usually being placed by cell placement program at the early stage of layout. Two general clock tree distribution algorithms are discussed here. The positions of the buffers and the clock source. this approach is not feasible because the drive strength of the clock source is limited. and there is not enough room to route wires around the clock source. Assuming that there is no buffer between any logic gate and the clock source. however. and the wire width is constant. the furthest logic gate will experience the largest delay. It should be noted that a few major assumptions are made for the following discussion: the wire resistance and wire capacitance have linear relationship with the clock signal delay. but also has the fastest speed.Clock Tree Distribution Algorithms An optimal balance clock tree distribution is to connect all logic gates directly to the clock source. are determined by the clock tree distribution algorithm. all buffers are identical and they contribute the same delay.

the clock trees generated by these algorithms may look similar. clock trees built by different algorithms may have noticeable difference in clock skew. If the placement pattern of the logic gates is unique. It is difficult. Each algorithm has its own distinct characteristics. There are other clock tree distribution algorithms proposed. wire length and design flexibility. if not impossible. such as buffer distribution algorithm [3]. clock signal speed. to determine which algorithm is the best. If logic gates are evenly distributed. general zero-skew clock net [4] and process-variation-tolerant zero skew-clock routing [5]. 27 .

Buffer Pre-Placement 28 .

Iso-Radius Buffer Insertion (a) (b) (a) (b) 29 .

Width Control 30 .

Width Tapering 31 .

Buffer/Load Distribution 32 .

it is undesirable since they may cause crosstalk due to close proximity of wires. hence the skew in each terminals is zero. the shape of H-Tree can be changeable with X shape. 33 . But. The H-Tree algorithms connects two terminals in a particular order. as is the case in the gate arrays. Then.H-Tree H-Tree is a special case of CRP. it connects the two middle points of vertical segments. where all the clock terminals are arranged in a symmetric fashion. X-Tree : If the routing is not restricted to being rectilinear. The H-Tree makes all terminals have the same unit length. The connected middle points are called the tapping points.

Hierarchical Matching Tree : MMM & GMA MMM(Method of Means and Medians) : The MMM algorithm recursively partitions a circuit into two equal parts. GMA works bottom up. ¢ ¢ ¡ ut Black Blue - ut 2 ut 3 MMM GMA £¢ ed - Green 34 . and then connects the center of the mass of the whole circuit to the centers of mass of the two sub-circuits. GMA(Geometric Matching Algorithm) : Unlikely MMM algorithm which is a top down algorithm.

So we call this ³snaking´. we must elongate one path length to make zero skew to both path. This algorithm Assumes that pairing of points has been done Concerns itself with finding the tapping point very accurately.Zero Skew Algorithm Zero Skew Algorithm has recursive. based on capacitive loading of the clock terminals as well as the delay in the sub-trees C t - ¦ ¦ § ¥ § c c ¦¨ ¦¨ ¤ T ¦ If we can¶t achieve the zero skew in Ta pping o int above method. bottom-up characteristics in nature. ¥ C ¥ c © ¦¨ c ¥ t © ¦¨ c1 c2 r1 ( c1 ) t1 ! r2 ( c2 ) t 2 2 2 T 35 .

A Worst Case Tree 36 .

RHMT 37 .

Importance metric: total wire length.diameter (for multi-source nets) Optimal tree construction algorithms BRBC(Bounded-radius bounded-cost) algorithm A-tree algorithm: start with a forest of n single-node A-trees. 38 . interconnect topology optimization is importance. radius (longest source-sink path-length). repeatedly combining two A-trees into a new one.Interconnect Topology Resistance ratio = driver resistance / unit wire resistance when resistance ratio is small.

Recent Approaches in Clock Tree Synthesis Research in Clock Tree Synthesis Algorithm Wire-sizing & Parallel Algorithm for zero skew Reducing Clock Power using Multiple Voltage Clock Tree Scheduling with Storage Retiming Research in System Level Design Feature GALS Clock Scheme Considering System Level Clock Tree 39 .

the size of a wire is locally o timized.Wire-sizing & Parallel Algorithm for zero skew (1) Using an iterative a roach. When. 40 . Assum tion : The sibling wire uses the same wire size. we have to re-merge the sub-tree rooted at the current wire with its sibling. To make the skew of the tree zero. the effect of the wire size change is agation ath ro agated by zero skew merging to the root of the clock tree. ro W The length of all the wires along the ro agation ath and their siblings may change but their wire-sizes remain unchanged. One wire segment is selected and an alternate wire-size is tried. This ro agation continues until all the wire segments on the ath from the current wire to the root wire are re-merged.

Only the nodes in the bottom part are distributed among the processors The nodes in the top part are shared among the processors First. The sub-tree assignment will not occur on nodes of depth 1 since it will make an assignment of 16 nodes and 2 nodes. then synchronized the result. .(Except root) Each process can do the wire-sizing for all the wires in the bottom part of the tree in a distributed manner. 16 2 p1 p1 6 p0 8 p1 The tree is partitioned into the top part and the bottom part. let each processor do the wire-sizing for the top part. 41 Iteration Method.Wire-sizing & Parallel Algorithm for zero skew (2) Sub-tree Partition : Assume there are two processors. But in depth of 2. we have 4 sub-trees.

Only use reduced-swing clock scheme. LL Converter : regenerate the signal and maintain a sharp slew rate as the signal passes through the network. Instead of using multiple voltage. 42 .Reducing Clock Power using Multiple Voltage P ! f CLVddVs ! f CLVdd 2 HL Converter : converts the incoming clock signal to the chip from high voltage swing to a lower voltage swing. LH Converter : convert the higher voltage swing used by logic network at the sink FF.

Clock scheduling achieves the same effect as retiming by introducing skew between the clock signals that control the timing of the storage elements within a circuit. When nonzero clock skew is introduced. the circuit can successfully operate at a clock period which equals the largest difference in the delays of the slowest path and the fastest path between any pair of registers. When the clock skew is zero. the minimum clock period is the longest delay of all the combinational paths in the circuit. So the goal is to balance the longest delay of all the data paths by relocation the registers.Clock Tree Scheduling with Storage Retiming Retiming improves the speed of a digital circuit bye relocating its storage elements while preserving the functionality of the original design. Left : Original circuit Middle : Fastest retimed circuit with zero skew Right : Fastest retimed circuit with nonzero skew 43 .

GALS approach is skew tolerant at global level because it does not depend on a global clock reference for communication. In the view of system design. we eliminate a major source of power consumption and a design bottleneck. Locally Synchronous) design style. Power consumption in clock of large high performance VLSIs can be reduced by adopting GALS(Globally Asynchronous. Power consumption in Clock tree is about 50% percent of total power consumption. we must reduce the power consumption of clock. By eliminating the global clock. 44 . but. GALS architecture is composed of large synchronous block(SBs) which communicate with each other on an asynchronous basis. gated clock will occurs clock skew when clock frequencies go beyond GHz.GALS Clock Scheme(1) By now.

The basic ring oscillator consists of an odd number of inverters in a circular chain. a delay line of controllable capacitor is used.GALS Clock Scheme(2) In GALS architecture. The signal is distributed at a much lower frequency compared to the highest frequency. local clocks are required for the SBs. No effort is made to carefully design the geometry of the signal to minimize skew. Using global reference and PLL The signal swing can be a fraction of Vdd. The frequency of the ring oscillator will be determined by the propagation time through the chain of inverters. To change the oscillation. Local clock generators based on ring oscillators. 45 . Restriction : analog PLL in a noisy digital environment is difficult. and PLL is sensitive to process variations.

Conclusion . optimized to meet all of your constraints.Low Power Issues (1) Power optimization allows logic optimization to simultaneously optimize for timing. technology library. What you get out of power optimization is a gate-level netlist.the same switching activity used with power analysis. and parasitic information (initially in the form of estimated wireloads. 46 . In a similar way gate-level power optimization will pave the way for RTL and Behavioral synthesis for low power. optional constraints for timing and area. A natural question to ask is: "If optimization at the RTL and Behavioral levels can have a great impact on final power dissipation. A power-optimizing logic optimization system takes as input a gate-level netlist or database. area and power. So all the inputs to optimization are the same with the addition of two new power constraints: max dynamic power and max leakage power. All that's needed in addition for power optimization is to set a power constraint and supply switching activity . but if backannotation has been done that information will be used). The first commercially successful synthesis products were gate-level timing optimizers and these paved the way for RTL and Behavioral synthesis systems. why offer a gate-level power optimization capability first?" Over a decade of experience in synthesis and optimization it has proven that RTL level suffers the impact of optimization at the gate level.

Or to put it another way: Successful synthesis at higher levels requires successful optimization at lower levels.Low Power Issues (1) Earlier we made the point that analysis precedes optimization. 47 .Conclusion . Here we make another general point: We might say that just as analysis precedes optimization. optimization precedes synthesis.

IR drop: the voltage drop caused by the current I through the resistor R. 48 . Jitter: the change in period to period timing in a clock signal. Latency: the time for a clock to become available in the circuit. Clock tree: design technique to achieve balanced delays and loads in the clock buffers. Ground loop: the noise caused in the ground line(s) due to unbalanced IR drops in the ground line. Multiphase clock: clocking system with more than one phase may be overlapping or nonoverlapping.The Key Terms in Clock Tree Synthesis Clock buffer: circuit element to isolate and amplify incoming clock signal. Slew rate: also called rise time or fall time. Skew: the maximum difference in clock arrival time between any two flip-flops. Quadrature-clocks separated by a phase angle of 90 degree PLL: Phase-Locked Loop. Gated clock: clock line that can control clock transmission to the operating circuits. Ground bounce: the change in ground (vss) reference levels due to current in the ground line. Insertion delay: the time from clock pad to individual flop-flops. Biphase-clock and complement. a variable frequency generator locked to a source signal. The time for a signal to go from one level to the other level.

49 . Schweber. IEEE 93 Custom Integrated Circuits Conference. In IEEE 1992 Custom Integrated Circuits Conference. T.In Proc. D. Cheng. Hansen and R. and Packaging for VLSI. [10] K. In Proc. ASIC Design Techniques Synchronize Dual Clocks In High-Speed Designs. 1992 [11] A. In Proc. T. P. Interconnections. 1995 [7] Menezes. Nisson. Lundqvist. No. In Proc. Khan and N. Hemani. 1999. Vol 3. K. Skew Reduction in Clock trees Using Wire Width Optimization.Lowering power consumption in clock by using Globally Asynchronous Locally Synchronous design style. A. T. On General Zero-Skew Clock Net Construction. Pillage. K. B. Boese and A. Kumar. 1995 [2] H. EDN. S. D. Lin and C. Ellervee. February 16. Deep submicron ASIC Design Requires Design Planning. July 6. Delivering The High-Speed Clock: Not Easy To Be On Time. Wong. In Proc. March 1993. A Buffer Distribution Algorithm for High-Performance Clock Net Optimization. 1993 [8] R. Oberg. In Proc. March 1995 [5] S. 1990 [3] J. Process-Variation-Tolerant Zero Skew Clock Routing. J. Zero Skew Clock Routing Algorithm For High Performance ASIC Systems. B. [4] N. EDN. Balivada. Postula. Bakoglu. No. IEEE Transactions On Very Large Scale Integration (VLSI) Systems. Deming. Meinchke. A. Chou and C. Addison-Wesley Publishing Company.1. In Proc. Wiederhold. In IEEE 1993 Custom Integrated Circuits Conference.1. IEEE Transactions On Very Large Scale Integration (VLSI) Systems. Pullela and L. Sherwani. Zero-Skew Clock Routing Trees With Minimum Wirelength.References & Suggested Readings(1) [1] B. New York. July 1993 [9] W. EDN. DAC `99. Vol 3. Olsson. Kahng. C. Cho and M. Sarrafzadeh. S. 1993 [6] B. P. Circuits. D.

1998. Clock Distribution Using Multiple Voltages. Vol. 50 . Papaefthymiou. O. No. E.References & Suggested Readings(2) [12] J. CAD-2. P. 1999 [15] Z. Horowitz. Xing. A. Pangjun. S. In Proc. In Proc. Yim. July 1983 [13] X. DAC`99. A Floorplan-based Planning Methodology for Power and Clock Distribution in ASICs. Penfield. G. Maximizing Performance by Retiming and Clock Skew Scheduling. Kyung. C.3. [16] J. A PARALLEL ALGORITHM FOR ZERO SKEW CLOCK TREE ROUTING. C. P. Bae. Rubinstein. IEEE Transactions On Computer-Aided Design. International Symposium on Physical Design. In Proc. DAC`99 1999. S. Banerjee. S. Liu. S. M. [14] J. and M. ISLPED`99. Friedman. 1999. Signal Delay in RC Tree Networks. Sapatnekar. M.

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