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The INTEL 8279 is specially developed for interfacing keyboard and display

devices to 8085/8086/8088 microprocessor based system. The important

features of 8279 are,

˜ Simultaneous keyboard and display operations.

˜ It is designed to interface and control keyboard and display

peripherals. It relives CPU from scanning keyboards, refreshing
displays, debouncing key closures, blanking display etc.

˜ it provides two 4 bit display output ports, hence two separate

banks of 8/16 digit numeric displays can be interfaced. Two 4 bit
ports can also be used together as a single 8 bit port. Hence a
single bank of 16 characters alphanumeric display can be
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3ins of 8259 can be divided into

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Interface 3ins
3ins Functions

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ëeyboard 3ins
3ins Functions
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*&!2$&)2'8" %5%"&'(0*&!2$&)%$&'2'80$((
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keyboard mode only6+%&)+5%"&'%($w 96 
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)$*&$control input !$%6+$&'2!!"*&$$%*%(&control
key &)+%" %,'%'5%"&'(6wignored in sensor matrix mode6
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Display 3ins
3ins Functions
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    &''%$(3(!!" '&4'22!%0-./& *&$%$&)%!%*%(
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 lank Display:
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SCÔN 3ins
3ins Functions
  SCÔN Lines:
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!$%*$%& %'%($%+%'encoded &'decoded mode6
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lock diagram of 8279: C3 ëeyboard

The four major sections of 8279 are keyboard, scan, display
and CPU interface.

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ëeyboard section:
˜ The keyboard section consists of eight return lines RL0 - RL7
that can be used to form the columns of a keyboard matrix.
˜ It has two additional input : shift and control/strobe. The
keys are automatically debounced.
˜ The two operating modes of keyboard section are 2-key
lockout and N-key rollover.
˜ In the 2-key lockout mode, if two keys are pressed
simultaneously, only the first key is recognized.
˜ In the N-key rollover mode simultaneous keys are recognized
and their codes are stored in FIFO.
˜ The keyboard section also have an 8 x 8 FIFO (First In First
Out) RAM.
˜ The FIFO can store eight key codes in the scan keyboard mode. The
status of the shift key and control key are also stored along with key
code. The 8279 generate an interrupt signal when there is an entry in
FIFO. The format of key code entry in FIFO for scan keyboard mode is,

˜ In sensor matrix mode the condition (i.e., open/close status)

of 64 switches is stored in FIFO RAM. If the condition of any of
the switches changes then the 8279 asserts IRQ as high to
interrupt the processor.
Display section
˜ The display section has eight output lines divided into two groups A0-

A3 and 0-3.

˜ The output lines can be used either as a single group of eight lines or as

two groups of four lines, in conjunction with the scan lines for a

multiplexed display.

˜ The output lines are connected to the anodes through driver transistor

in case of common cathode 7-segment LEDs.

˜ The cathodes are connected to scan lines through driver transistors.

˜ The display can be blanked by D (low) line.

˜ The display section consists of 16 x 8 display RAM. The CPU can read

from or write into any location of the display RAM.

Scan section:
˜The scan section has a scan counter and four scan lines, SL0 to SL3.

˜In decoded scan mode, the output of scan lines will be similar to a 2-

to-4 decoder.

˜In encoded scan mode, the output of scan lines will be binary count,

and so an external decoder should be used to convert the binary

count to decoded output.

˜The scan lines are common for keyboard and display.

˜The scan lines are used to form the rows of a matrix keyboard and

also connected to digit drivers of a multiplexed display, to turn

C3 interface section
˜The CPU interface section takes care of data transfer between 8279 and
the processor.
˜This section has eight bidirectional data lines D0 to D7 for data
transfer between 8279 and CPU.
˜It requires two internal address A =0 for selecting data buffer and A = 1
for selecting control register of8279.
˜The control signals WR (low), RD (low), CS (low) and A0 are used for
read/write to 8279.
˜It has an interrupt request line IRQ, for interrupt driven data transfer
with processor.
˜The 8279 require an internal clock frequency of 100 kHz. This can be
obtained by dividing the input clock by an internal pre scaler.
˜The RESET signal sets the 8279 in 16-character display with two -key
lockout keyboard modes.
Programming the 8279:
˜The 8279 can be programmed to perform various functions through eight
command words.

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3rogram Clock

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In general 3rescalar value = (external Clock / 100 ëz) ; for proper operation.
Read FIFO/Sensor RÔ

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(('%= >'%''%!%3$6

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Read Display RÔ

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The C3 sets up the 8279 for a read of the Display RÔ by first writing this command.
The address bits ÔÔÔÔ select one of the 16 rows of the Display RÔ .

If the ÔI flag is set (ÔI=1), this row address will be incremented after each following
read or write to the Display RÔ .

Since the same counter is used for both reading and writing, this command sets the
next read or write address and the sense of the Ôuto-Increment mode for both
Write Display RÔ

* The C3 sets up the 8279 for a write to the Display RÔ by first writing this
command. Ôfter writing the command with Ô0=1, all subsequent writes with Ô0 = 0
will be to the Display RÔ .

* The address and Ôuto-Increment functions are identical to those for the Read
Display RÔ .

* owever, this command does not affect the source of subsequent Data Reads; the
C3 will read from whichever RÔ (Display of FIFO/Sensor) which was last
specified. If, indeed, the Display RÔ was last specified, the Write Display RÔ
will, nevertheless, change the Next Read location.
Display Write Inhibit/lanking

w$+ !%
BC &'2! %'&$
7BCw$+&''%%@% !% ( !"
w$+ !%
BC &'2! %'&$
7BCw$+&''%%@% !% ( !"

!$5 !%
BC &'2! %'&$
7BC !$5 !% ( !"

!$5 !%
BC &'2! %'&$
7BC !$5 !% ( !"

This code defaults to all zeros after a reset. Note that both L flags must be set to blank a
display formatted with a single 8-bit port.

The CD bits are available in this command to clear all rows of the Display RÔ to a
selectable blanking code as follows :

During the time the Display RÔ is being cleared (~160 ʅs), it may not be written to. The
most significant bit of the FIFO status word is set during this time. When the Display RÔ
becomes available again, it automatically Resets.

If the CF bit is asserted (CF = 1), the FIFO status is cleared and the interrupt output line is
Ôlso, the Sensor RÔ pointer is set to row 0.
CÔ, the Clear Ôll bit, has the combined effect of CD and CF; it uses the CD clearing code on
the Display RÔ and also clears FIFO status. Furthermore, if resynchronizes the internal
timing chain.
End Interrupt/Error ode Set

For the sensor matrix modes this command lowers the IRQ line and enables further
writing into RÔ . (The IRQ line would have been raised upon the detection of a
change in a sensor value.

This would have also inhibited further writing into the RÔ until reset).
For the N-key rollover mode - if the E bit is programmed to ͞1͟ the chip will operate in
the special Error mode.
In a microprocessor based system, when
keyboard and 7-segment LED display is interfaced
using ports or latches then the processor has to
carry the following task.

˜ ëeyboard scanning
˜ ëey debouncing
˜ ëey code generation
˜ Sending display code to LED
˜ Display refreshing
Interfacing 8279 with 8085 processor:

˜A typical Hexa keyboard and 7-segment LED display interfacing circuit using 8279 is shown.
Interfacing 8279 with 8 X 4 matrix keyboard

Source program:
MVI A, 00H : Initialize keyboard/display in
OUT 81H : scan keyboard 2 key lockout
MVI A, 34H
OUT 81H : Initialize prescaler count
MVI A, 0BH : Load mask pattern to enable
RST 7.5
SIM : mask other interrupts
EI : Enable Interrupt
HERE: JMP HERE : Wait for the interrupt

Interrupt Subroutine:
MVI A, 40H : Initialize 8279 in read FIFO
OUT 81H : RAM mode
IN 80H : Read FIFO RAM (keycode)
EI : Enable Interrupt
RET : Return to main program
Interfacing 8279 with 8 X 8 matrix keyboard (decoded mode)



Interfacing 8279 with seven segment display
Interfacing 8279 with 8 seven segment display (decoded
Source program:
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9w 0<
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w9 D25&+%'$%'' 
w D$!%w$%'' 
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Interrupt service routine

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9 09 DF%+%%42%$*&(%
- D
'%%42%$*&(%$( !" 9
w D$!%$%'' 
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