Lecture-11

POWER ANALYSIS AT CIRCUIT-LEVEL

Dr. Arti Noor M. Tech (VLSI) Division, CDAC Noida UP.

29-3-2011

LPVD Lecture-11

Topics
‡ Network Restructuring and Reorganization.
± Transistor network restructuring. ± Transistor network partitioning and reorganization.

‡ Special Latches and FFs. ‡ Low Power Digital Cell Library.

LPVD Lecture-11

Network restructuring and Reorganization
‡ If signal probabilities are known, then restructuring of transistors may result in low power.

Various transistor reordering techniques : Transistor Network Restructuring:
Boolean functions are composed of AND and OR gates. To realize any Boolean function, one can map it on complex logic gates directly. ‡ The mapping steps are : -- Each variable corresponds to N and P transistor pair, -- For N-Network : serial connection corresponds to AND while parallel OR operator. -- P-network is just reverse of N-network. -- Inverter optionally can be added. Example : Y= AB+C ‡
LPVD Lecture-11

LPVD Lecture-11 .

LPVD Lecture-11 .

‡ To do the analysis of timing and power. one has to calculate transition probability at each input node to evaluate the circuit. ‡ As a general rule : put transition involving transistors near to output node because often these have less delay and consume less power. ‡ A switching level simulation is used to select best implementation. This results in different timing and power consumption. ‡ Therefore. LPVD Lecture-11 .Network restructuring summary ‡ Same function can be implemented in different ways.

supply voltage. In place of CMOS gate now consider transistor network. The exact limit of transistors depends upon technology. system speed.Transistor Network Partitioning and Reorganization ‡ ‡ ‡ ‡ ‡ Restructuring operation is applied on single complex logic gate. Partitioning and reorganization concept can be applied to trade-off between power and delay. Large Boolean function can not be implemented in single complex gate because of series and parallel connection limit of transistors. LPVD Lecture-11 ‡ . Network reorganization is composing different transistors network that can implement same functionality.

‡ Example: LPVD Lecture-11 .Network Reorganization ‡ With a given technology and serial connection constrains. the aim is to partition and reorganize circuit for better performance.

‡ Sizing each transistor of gate needs a tool for automatic layout simulation. ‡ CMOS complex gate generated by reorganization can not be predesigned. ‡ For large network hand calculation is not possible. LPVD Lecture-11 .Network Reorganization ‡ The choice of network structure increases exponentially with circuit size for best result. ‡ Sophisticated CAD tools are required at physical level. ‡ Power and timing analysis to be performed at transistor level which is computation intensive.

In addition to voltage reduction. FFs are clocked at the system and thus consumes large amount of power. LPVD Lecture-11 . capacitance reduction and change in transistor count to minimize switching techniques are used to reduce the power. Data Energy : addition to clock energy due to different data writing in FF.Special Latches and FFs ‡ ‡ ‡ ‡ ‡ ‡ Latches and FFs are basic elements used in synchronous circuits and decide the maximum speed of the system. FFs energy dissipation has two parts : Clock energy : dissipated when FF is clocked and data is unchanged. Normally Data rate is much lower than clock rate and thus power saving techniques concentrate on clock energy reduction.

Similarly single phase FF is suitable for low power implementation as compared to two phase clock. ‡ ‡ ‡ LPVD Lecture-11 . The NMOS transistor in place of TG eliminates two phase non overlapping clock. One has to do SPICE level simulation after including transistor sizing techniques to select the best implementation of Latches and FFs. delay and power consumption. reduces load capacitance at the cost of speed and threshold voltage loss.Flip-Flop and Latch Circuits ‡ Flip-flop and latch can be implemented in different ways and each design varies in terms of area.

‡ The RS latch retains data when clock is low during precharge. LPVD Lecture-11 . ‡ T provides a path to GND and prevents latch to have intermediate values. ‡ RS inputs are precharged and selectively discharged at rising edge of clock. Four transistors form cross-coupled feedback inverters.Flip-Flop and Latch Circuits ‡ FF contains differential feedback circuit to drive RS latch. Only three transistors are connected to clock and no static Current when clk stopped.

Power is saved by holding the internal clock signal while external clock of FF switches. LPVD Lecture-11 . ‡ ‡ If there is no change in data then power can be saved by suppressing the clock switching.‡ ‡ Flip-Flop and Latch Circuits Self Gating FF Some part of clock energy is consumed by internal clock buffer to control TGs.

‡ When D and Q are different XOR output is one to pass clk. ‡ TG at Clk is used to gate the external clock so that internal clock J and Jbar do not switch if not required. When J is high TG is off to stop unnecessary switching unless D and Q are different. LPVD Lecture-11 .Flip-Flop and Latch Circuits ‡ Self Gating FF The below figure shows this idea.

The power dissipation depends on transition frequency of Td and Tclk. When it is less than one. ‡ LPVD Lecture-11 . but if input switching probability is very low as compared to clock rate then probability of clock disabling is very high. when it is zero. power saving is more. no dynamic power consumption by this circuit.Flip-Flop and Latch Circuits ‡ Self Gating FF ‡ This circuit uses more area and delay.

Flip-Flop and Latch Circuits ‡ Double edge triggered FF ‡ Data can be latched on both rising and falling edge of clock. ‡ fc: clock frequency and fd is FF output frequency. Clock frequency can be halved to achieved same throughput compared to single edge triggered FF. More area is required but FF retains data when clock is not toggling. Comparison of both FFs SETFF ‡ ‡ ‡ Ps ! E sc f c  E sd f d ‡ Esc: energy consumed due to clock ‡ Esd: energy consumed due to data. LPVD Lecture-11 .

84 Ps ‡ ‡ DETFF is working at half frequency. fd=0. Edc = 1.17 Esc f c ! 0. so over all 2X time power saving in clock distribution network.4 Esc f c Pd ! 1. so energies are also larger in this case. Edd=1. 5 E dc f c  E dd f d ‡ ‡ Normally fd is very small as compared to fc. LPVD Lecture-11 . DETFF area is more as SETFF. If Esc=Esd.3Esd.4fc then Ps ! 1.3Esc. Esc/Edc ratio is important at the time of circuit design.Flip-Flop and Latch Circuits ‡ DETFF Pd ! 0 .

At gate±level the basic building blocks are gates or cells. Quality of gate level synthesis depends upon quality of cell library. low power cells are added in library to meet the power specification.Low Power Digital Cell Library ‡ Most circuits are synthesized at gate level to meet the various specifications. LPVD Lecture-11 ‡ ‡ ‡ . Therefore.

Spacing of cell sizes should be chosen carefully. thus more cell sizes should be available to drive this range. LPVD Lecture-11 . delay and power by selecting the appropriate sizes of cells. 8X. Capacitance distribution profile is considered for spacing. Example : normally net capacitance is within 0. The number of gates of different sizes is approximately four times of traditional cell library for low power. one should have cells of wide range sizes. Because of low range of capacitance. Therefore for good low power cell library.5pF. one has to do trade-off among area.5X.Low Power Digital Cell Library Cell Sizes and Spacing ‡ ‡ ‡ ‡ ‡ ‡ ‡ In top-down cell based design.2X. lower drive cells should be spaced closer than higher drive cells like :1X.1-0. 12X. 3X.

Typically OR. AND. thus for n>3 small number of M Boolean functions are available in cell library. AOI. and OAI are available. M=28. For n-input.Low Power Digital Cell Library Varieties of Boolean Functions ‡ ‡ ‡ After size and spacing the next consideration is on how many Boolean functions of given inputs (n-inputs) exist. XOR. For n=3. LPVD Lecture-11 . Each combination is unique Boolean function thus one can write M !2 ‡ 2n M is very large for small values of n. one has 2n entries at output side with different 0 and 1 combinations.

Compare which cell will take less area and power. M functions can not be implemented but how many function should be sufficient for a rich library? Among M some are degenerated : output dose not depend on all input variables. Y ! AB ‡ Implement Y without having inverted input cells and with inverted input cells. Among non-degenerated some are identical like ‡ ‡ Y ! AB Y ! A B LPVD Lecture-11 .Low Power Digital Cell Library Varieties of Boolean Functions ‡ Lack of variety of functions results in inferior circuits.

‡ Negation of input variables. ‡ Negation of output LPVD Lecture-11 .Low Power Digital Cell Library Varieties of Boolean Functions Equivalence of Functions : ‡ Permutation of input variables.

Low Power Digital Cell Library Varieties of Boolean Functions P-Equivalence ‡ Some Boolean function are P equivalent (one function can be obtained from other by permuting the inputs) Let f (X) and g (X) be two functions and . x2 .«. xn} ‡ Then  g (X) = f (V (X) )  where V is a permutation of X  LPVD Lecture-11 X = { x1 .

x3 p x 4 . g ! x 2 x 4  x1 x3 V maps x1 p x2 . x 2 p x1 . x 4 p x3   g ( x ) ! f ( Vx ) ‡ This can be used to reduce the number of function by having P equivalence classes.Low Power Digital Cell Library Varieties of Boolean Functions P-Equivalence (Permutation of input variables) ‡ Example f ! x1 x3  x 2 x 4 . Y ! AB  C . Y ! AC  B LPVD Lecture-11 .

x2 . x3 p x3 .Low Power Digital Cell Library Varieties of Boolean Functions N-Equivalence (Negation of input variables)  Let f (X) and g (X) be two functions and X = { x1 . x 2 p x 2 . xn} ‡ Then  g (X) = f (N (X) )  where N maps each xi to itself or its complement ‡ Example : f ! x1  x 2  x3 .   g ( x ) ! f (Jx ) LPVD Lecture-11 .«. g ! x1  x 2  x3 J maps x1 p x1 .

Low Power Digital Cell Library Varieties of Boolean Functions N-Equivalence (Negation of output) g ( X ) ! f ( X ) or g(X) ! f ( X ) f ! x1  x2 and g ! x1.x2   g( X ) ! f ( X ) Y ! AB } Y ! A B and Y ! A B Y ! AB } Y ! AB LPVD Lecture-11 .

produces circuits with better quality.equivalent : ± equivalent under input Permutation The cell library which covers the more classes .Low Power Digital Cell Library Varieties of Boolean Functions    NPN-equivalent : ± equivalent under input Negation. LPVD Lecture-11 ‡ . input Permutation. input Permutation P. output Negation NP-equivalent : ± equivalent under input Negation.

Low Power Digital Cell Library Varieties of Boolean Functions Input (n) Fn.7 X 107 1.904 LPVD Lecture-11 . NP equipv NPN equipv 2 1 2 3 4 5 4 16 256 2 n 2 10 218 64594 2 8 68 3904 1 3 16 380 1 2 10 208 65536 4. n variables P-equipv.227.756 615.3 X 109 4. No.3 X 109 3.

performance decreases rapidly and becomes limiting factor. LPVD Lecture-11 .Adjustable Device Threshold Voltage ‡ When one reduces the supply voltage how it affects delay and performance. V dd td w 2 (V dd  V t ) f max ‡ ‡ Vt 1 w w (1  )(V dd  V t ) td V dd When Vdd is closer to Vt. Because of reduction in subthreshold current and process variation. But proportionally one can not scale Vt. Thus one has to scale Vt also.

Another method is control Vt by Body bias voltage. ‡ ‡ LPVD Lecture-11 . Speed critical devices operate at low Vt while others at high Vt.Adjustable Device Threshold Voltage ‡ ‡ One solution is use different Vt devices on the same chip. Additional mask is not needed but the Vt stability is poor and bias voltage generation circuit need additional power. For this additional mask is needed to identify the low Vt devices.

Assignment y=a+bc Use Shannon Decomposition theorem to find probability and transition density function. Submission date 4-4-2011 LPVD Lecture-11 .

LPVD Lecture-11 . NP and NPN equivalence. ‡ Date of submission 11-4-2011.Assignment ‡ Draw the 2 input function under P.

Next Topic ‡ Power optimization techniques at Logic Level (chapter-5 Yeap) LPVD Lecture-11 .

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