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 BJTs amplifier requires a knowledge of both the DC analysis
(3 signal) and AC analysis ( 33 signal).
 ^or a DC analysis a transistor is controlled by a number of
factors including the range of possible operating points.
 Once the desired DC current and voltage levels have been
defined, a network must be constructed that will establish the
desired operating point.
 BJT need to be operate in active region used as amplifier.
 The cutoff and saturation region used as a switches.
 ^or the BJTs to be biased in its linear or active operating
region the following must be true:
a) BE junction forward biased, 0.6 or 0.7V
b) BC junction reverse biased
á   
 DC bias analysis assume all capacitors are open cct.
 AC bias analysis :
1) Neglecting all of DC sources
2) Assume coupling capacitors are short cct. The effect of
these capacitors is to set a lower cut-off frequency for
the cct.
3) Inspect the cct (replace BJTs with its small signal model).
4) Solve for voltage and current transfer function and i/o and
o/p impedances.
 ^or transistor amplifiers the resulting DC current and voltage
establish an operating point that define the region that can be
employed for amplification process.
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á   

##  Important basic relationships for a transistor:

VBE=0.7V

IE=(ȕ+1)IB§IC

IE= IC +IB

IC = ȕIB
u    
 ^or transistor amplifiers the resulting dc current and voltage
establish an operating point on the characteristics that define the
region that will be employed for amplification of the applied
signal.

##  The biasing circuit can be designed to set the device operation at

any of these points or others within the active region.

##  The BJT device could be biased to operate outside the max

limits, but the result of such operation would be shortening of the
lifetime of the device or destruction of the device.

##  The chosen Q-point often depends on the intended use of the

circuit.
D               
 

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 ^or the dc analysis the network can be isolated from the
indicated ac levels by replacing the capacitors with an open-
circuit equivalent because the reactance of a capacitor for dc is

 The dc supply Vcc can be separated into two supplies
^   
^    
 ]rite KVL equation in
 the clockwise direction
 
 of the loop :



 j YY   
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##  Solving the equation for

 
the current results :
  (  ?
?
?
 
   
 The magnitude of the IC is related
directly to IB through
Y  
 Apply KVL in the clockwise direction
around the indicated close loop results:
Y

## Yj YY YY

Y

Y YY YY
YY
Y
 `ecall that :
Y  Y   YY

##  In this case, VE = 0V, so

Y
Y
Y
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## IBQ ICQ ! VCEQ VB VC VBC

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 ·    
 The term saturation is applied to any system where levels have
reached their max values.
 ^or a transistor operating in the saturation region, the current is
maximum value for a particular design.
 Saturation region are normally avoided because the B-C junction
is no longer reverse-biased and the output amplified signal will
be distorted.


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 By refering to example 1 and the figure, determine the saturation
level.
Solution
- YY 3

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 )
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##  ^ind the saturation current for the fixed-bias configuration of

figure example 2.

Solution

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 )
 
 
 ]e investigate how the network parameters define the possible
range of Q-points and how the actual Q-point is determined.
 `efer to figure below (output loop) one straight line can be draw at
output characteristics. This line is called load line.
 This line connecting each separate of Q-point.
 At any point along the load line, values of IB, IC and VCE can be
picked off the graph.
 The process to plot the load line as follows:
 
 
 Step 1:
`efer to circuit, VCE=VCC ± IC`C (1)
Choose IC=0 mA. Subtitute into (1), we get
VCE=VCC (2) located at X axis
 Step 2:
Choose VCE=0V and subtitute into (1), we get
IC=VCC/`C (3) located at Y-axis
 Step 3:
Joining two points defined by (2) + (3), we get straight line that
can be drawn as ^ig. 5.6.
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 !
!iven the load line of ^ig. 5.10 and defined Q-point, determine the
required values of VCE, `C and `B for a fixed bias configuration.

  ,) .

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  ) + 3 \$
 ?  # 
3#
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233  : )
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Determine the value of Q-point for this figure. Also find the new
value of Q-point if ^ change to 150.

ë 3
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3
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 #3 -   ; (   ,
#3  - 387#)%.
  #·
áá|á·
 The DC bias network below contains an emitter resistor to
improve the stability level of fixed-bias configuration.
 The analysis consists of two scope:
- Examining the base-emitter loop (input loop)
- Use the result to investigate the collector-emitter loop (output
loop) D

`
`

D

D 

^   `

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Y 92  @Y*5

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  Y   01 )2334
 ?

## )& &  & ,  ))& &

) )  .

`   
Y 

    
|  
   !"#\$
%
·  | 
  


,2
)%

)%. 3)%
%Y , Y !#. 3
,2  2
  . 3 

' %Y9 AY

!)%
 AY , Y !#. 3 \$
`   

|  

#  % Y 

    
  !"#\$
%
· & `
   
2
* )& & 

01 )23
4


 M3

 01 )23
4

 ù3

`   
Y 

    
|  
   !"#\$
%
·     
`
    

 ? 01 )23"4

01 )23#4
 , M3.?

`   
Y 

    
|  
   !"#\$
%
 \$
^or the emitter-bias network for ^ig.5.14 determine:
a)IB b)IC c)VCE d)VC e)VE f)VB g)VBC
D D

` /
` /

 

^   `
/
·   
  (  ?
ù  !
.   ?  "  3 
 ? M ü M 3  "2 : M ü# M 3 3 :

.     ? ü# ü" 3
 3 )

.      (   ü  M 

ù ü
 3 ) ü
: M 3:
ù 8  2
32  7! 

 .    ù   
ù ü
 3 ) ü
:

ù " 
3#  7\$ 

.  ù   3#  7\$ ù 32  7!
 3 

      ü
 3 ) ü3 :
 3 

 . ?  ? M   ! M
 3
 !3 

 . ?  ? ù  
 !3 ù 3#  7\$ ù 32 
! 
,      >.
·    
     !      

 ù   ù    2

`  ù  ü M 2

  
^    
D
D
 M 2

`

 %
|    
/   &

·   
- YY
 Y ë
Y M 

ë ë ë 8  8! )%

: M 3: 2:
è   !     Y\$ . è " 
  &     !
  & !  ' ! 
/
 
      


Step 1:
    "
 Y YY Y.Yj .
Y  Y·! .
 

## Y YY . è   0 

Step 2:
Y  Y ! . 

- YY
Y ë -Y ë -  ,2.       B  +
Y M 
 
Step 3:
a  
  !'. j.

      
!
 ) "&


,
 .



 ,.
 


## #3!'<  )(   

 &
^or the emitter-bias network for ^ig.5.14 determine:
a) Draw a load line in the graph on the characteristic.
b)IB c)IC d)VCE e)VC f)VE g)VB h)VBC
i) Choose the operating point between cut off and saturation, determine
the resulting values ICQ and VCEQ

j) ȕ k)Į l) ICsat



 "

"
D  | 
^ . Y. Y. 
"   
#&




#

 ICQ and VCEQ from the table is changing dependently the changing of ^.
 The voltage-divider bias configuration is designed to have a less
dependent or independent of the ^.
 If the circuit parameter are properly chosen, the resulting levels of ICQ
and VCEQ can be almost totally independent of ^.
D  | 
 Two method for analyzed the voltage-divider bias configuration:
- Exact method ( applied anywhere)
- Approximate method (only if specified conditions are
satisfied)
 
 ·
The input side of the network can be redrawn for DC analysis.
 ·
Analysis of Thevenin equivalent network to the left of base
terminal
 

 · . 
`eplaced the voltage sources with short-circuit equivalent and
gives the value of `TH

   3 

 

 · .!
Determining the ETH by replaced back the voltage sources and
open circuit Thevenin voltage. Then apply the voltage-divider
rule.

- YY
 ë -
ë
3M

 

 ·

The Thevenin network is then redrawn and IBQ can be
determined by KVL  ù ? ù ? ù  
   üC M 3  ?   

 ù ?
?
  M ü M 3 
 
Determine the DC bias voltage VCE and current IC for the
voltage-divider configuration of network below:
YY

 Y/ 
 
# /  

ë 3"

 
# /       " /  
  3 
·    27 : ü2  7 :

2##  : )
27 : M 2  7 :

- YY 2  7 : ü

 
-
3M 
27 : M 2  7 :
  ù - ?
?
  M ü M 3  

ù !
8  # 
2  ## : M ü3" M 3 3  # :

Y  ? 3" ü8  #   \$# )

- Y - YY ù  Y ü Y M  

ù  \$# ) ü3 : M 3  # :
3


-
 

##  ^or the voltage-divider bias configuration, determine: IBQ, ICQ,

VCEQ, VC, VE and VB.
·   
  3 
    ù   ü  M 
8
: ü7  3 : 38 ù 3  !3
) ü2  7 : M  8\$ :
!72  : )
8
: M 7  3 : \$  38 


 73: ü38    ù    

 #
3 M 
8
: M 73: 38 ù 3  !3
) ü2  7 : 7  2


ù ?
  
?
  M ü M 3  ü M  8\$ :
? 

 # ù ! ü
3 " M 3!3
) 8\$ :

3 "
!72 : M ü\$ M 3 8\$ : 3 3\$ 

  ? \$ ü
3 " 3!3
) ?  M ?
3  3\$ M  !
3  \$\$ 
 
·

 ' (á )  
^`E 10`2 * ')    
#
*  
 ·
The input section can be represented by the network of figure below and
`2 can be considered in series by assuming
I1I2 and IB= 0A .

 `



 
 ü 3  

 ` 
`
 ü M 3  2

 
     
 
  
 
`
Step 3: 


      ) '  ` 
`


  
? 

3 M 

##         '  

     
 
  
 ? ë  ? (  
  ë  ? (  ?
Y  &
  )    ) '  +)  '
   3

    
   ë , ^ M 3.  ë ^ 
rr
 ·  
 

##  `epeat the analysis of example 9 using the approximate

technique and compare solution for ICQ and VCEQ.
3 '
 3 

## Solution: ü3" ü3#: 3 ü27:

3 : ) 27: )  ë


'
 ù    
·   
2 '

-YY 27: ü

-* ë ë ë
-
3 M
27: M 27:
Y\$. Y\$. 

  "  
- ë -* ù -*
 '
ë
ù ! ë 32-    &  

 '
- 32
Y;   ë ë ë \$8!)% Y\$  Y\$   ' 
3#:

-Y ; ë -YY ù YüY M
ë

ë 3
 2-
 

##  `epeat the exact analysis of example 9 if ^ is reduced to 70.

Compare the solution for ICQ and VCEQ.

Solution:   2## : )


 *

*
  M ü M 3 

 !
33  \$3  %
2  ## : M ü! M 3 3  # :

Y * ! ü33 \$3   \$2 )%
·   #  
- Y ë - YY   Y ü Y M  
ë

  \$2 ) ü3 : M 3  # :
ë 3
 "8 -

Y\$. Y\$. 

 "  
& 
 
Y         '    Y\$
 Y\$  ' 
 
|    Y\$  Y\$   
             '
Y    
YY 1

Y  
1  Y\$

\$

    
·   
+ % '
 ë  3

\$
: ü

:
ë ë 3 !  2#  : )
\$
: M

:

-YY

:ü3\$
 ë ë ë 2\$3-
3 M
\$
: M

:
 ù -?
? ë 
 M ü M 3  
2\$3 ù !
ë ë 27 8%
3! 2# : M ü# M 3 3
:

## Y ë  ? ë # ü27 8 ë 37\$ )%

- Y ë - YY ù  Y ü Y M  
ë 3\$ ù 3  7\$ ) ü#  8 : M 3 
:
ë "  #" -
·   #  
 +)  '
 3 

ü# ü3
: 3 ü

:
8 : )

: ),  .

-YY

: ü3\$
-* ë  ë ë ë 2\$3-
 3 M 
\$
: M

:
- ë -*  -*
ë 2\$3  ! ë 233-
- 233
Y;   ë ë ë
#7)
 3
:

-Y ; ë -YY  YüY M 
ë 3\$ 
#7)ü#8: M 3
:
ë 2\$\$-
·   #  

## Y\$.   Y\$.  


  # "
 '
" &
   "#

 '
        
           ! 
      
!


 

 M 
 
 
  ! 
            
       

##         



 
         +
 M 

##     )       D +

|  D  ^'+

 
'   ! '  !     ! /
      !  ! \$   '   '
      
  

 ' 2 3  
 YY Y
Y    

*   Y
 Y j  ! ' 44 Y è   Y
 Y

2
  Y     Y  YY Y     

## ·  '       - YY  - *

* ë
* M ^ , Y M   .
 
   

 2  ù , M2 .

##  ' 2 3  

  j Yj Y
Y YY 

· Y
 Y  Y   Y.Y jj Y YY 

## ·    Y  Y  YY Y.Yj

 ·    

-YY
Y ë Y)+ ë
Y M  

 

##    '    ! 

! 
·   rr    
    

ó     
|u    
 ]e are able to design the transistor circuit using the ideas that
we have learnt before during analyzing dc biasing circuit.
 How?
- Understand the Kirchoff¶s Law and other electric circuit
law such as Ohms Law, Thevenin Laws etc
- Identify the parameters given
- Analyze into the input/output for the system and build a
loop using electric circuit¶s law.
|u    
 If the transistor and supplies are specified,
the design process will simply determine the
required resistor for a particular design.
 Once the theoretical values of the resistors
are determined, the nearest standard
commercial values are normally chosen and
any variations due to not using the exact
resistance values are accepted as part of the
design.
`unknown=V`/I`
| '     
'+ 

 5 
6  '  
| '   
  '+ 

##  `E and `C cannot proceed directly from the

information just specified.
 `E ± to provide dc bias stabilization so that the
change of collector current due to leakage currents
in the transistor and the transistor beta would not
cause a large shift in the operating point.
 The `E cannot be unreasonably large because the
voltage across it limits the range of swing of the
voltage from collector to emitter.
 VE ± typically ¼ -1/10 from supply voltage
 
Determine the resistor values for the network,
for
the indicated operating point and supply
voltage.
|   
|     ',  
#'  

##  5 6

 '  
   
 7

  
  +
>  
/   
> +   
         
    
>    
  
Y Y+
Y  
> +       
   ' !  ! 
  
 
/

    +

 
       
^
        

 
 ë ë 

o

  ë  ë  

   
    ë ë o o!
^ 

  

  #  

' 
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