A presentation on VLSI / VHDL JNIT

Submitted to:Submitted by:Mr. Devendra Somwanshi Ashish Khandelwal Seminar coordinator Final Year (VII Sem) E.I.C. E.I.C.

About Institute

ST Microsystems is a software and VLSI design training center located in the IT-zone at Sitapura industrial area, Jaipur. It was established in 2001 and is the first VLSI design center in Rajasthan in private sector. The company has registered its presence in training sector through its high quality and expert training in emerging technologies. Keeping in view the importance that IT has gained in recent years and small number of institutes providing the industry level training in the area, ST Microsystems provides training in major key areas like VLSI, software design & development, embedded systems, PLC/SCADA etc.

Integrated circuits(ICs) .

Classification of ICs • • • • • SSI MSI LSI VLSI ULSI .

000 to 1.000.VLSI • Very Large Scale Integrated Circuits • 100.000 electronic components per chip • Language used • VHDL • Verilog HDL  .

VHDL • • • • V – Very high speed integrated circuit(VHSIC) H – Hardware D – Description L – Language • •  .

Overview of VHDL • • • • • VHDL has IEEE standard Used to model a digital system Not case sensitive (entity is similar to ENTity) Described & Verified the model .

Requirements • • • • • Library support Sequential statement Type declarations and usage Timing control Support for design hierarchy .

VHDL model .

Elements of VHDL • Entity • Architecture .

Entity declaration • Each component or subsystem is identified by its entity name • Specifies name of entity • Define ports of entity • A design can be used one or more entity .

 .Syntax of Entity        Entity NAME_OF_ENTITY is. End [NAME_OF_ENTITY] . Port (signal_names: mode type. signal_names: mode type. : : signal_names: mode type).

b : in bit . c : out bit).Example            a c b OR Gate Entity or_ gate is Port(a . . End or_ gate.

Architecture • Describes the implementation of the port behavior • Specifies the circuit operation • Includes process of implementation • Describes the behavior of the entity .

procedure.Syntax of Architecture Architecture ARCH_NAME of ENTITY_NAME is <signal.  . function and component declaration> Begin <Concurrent statements> <Processes> <Component instantiations> End ARCH_NAME.

Example           a b c OR Gate Architecture dataflow of or_ gate is Begin c <= a or b . End dataflow . .

Library & Packages • Where compiler stores information about a design project • Contains set of utility packages • Package contains declarations of commonly used objects .

Use LIBRARY_NAME.Library & Packages • Syntax   Library LIBRARY_NAME. Use IEEE.ALL.PACKAGE_NAME.STD_LOGIC_1164. •    .<List of definitions>  • Example   Library IEEE.

use ieee.std_logic_1164. use ieee.all.all.all.std_logic_arith.  . use ieee.std_logic_unsigned.Library & Packages • Package types • std_logic_1164 package • std_logic_arith package • std_logic_unsigned package • std_logic_misc package  • Implementation     library ieee.

Modeling of VHDL • Dataflow modeling • Behavioral modeling • Structural modeling .

end alu.std_logic_1164.all. . s:in std_logic_vector(3 downto 0). Entity alu is Port ( a. f: out std_logic_vector(3 downto 0)).Example of VHDL          --Example of ALU Library ieee. Use ieee.std_logic_unsigned.all. Use ieee.b:in std_logic_vector(3 downto 0).

Example of VHDL(cont. elsif s="0010" then f<=a-b.)  architecture alu_arch of alu is begin process(s. a. elsif s="0001" then f <= a + b.          . b) begin if s="0000" then f<="0000".

end process. elsif s="1001" then f<= not a. elsif s="0111" then f<= a nand b. elsif s="0110" then f<= a or b. elsif s="1000" then f<= a nor b.)              elsif s="0101" then f<= a and b.Example of VHDL(cont. . elsif s ="1010" then end if.

New York. Perry. McGraw-Hill. • [3] http://en. 2002.org/wiki/VHDL • • • .html#_Toc526061341 • [2] Douglas L.edu/~ese201/vhdl/vh dl_primer. Fourth Edition.wikipedia.wikipedia.seas.upenn.org/wiki/Very-largescale_integration • [4] http://en.References • [1] http://www. VHDL: “programming by example”.

Queries ??? .

!! Thank You !! .