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Static Timing Analysis & Synthesis

Maharshi Bhattacharya

© Advanced VLSI Design Laboratory

Dynamic Vs. Static Timing Analysis

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Dynamic timing analysis is not exhaustive and do not cover all critical paths . Static timing analysis is highly exhaustive and fast. STA may include false paths into consideration as critical path. In DTA there is no chance of false path being interpreted. Main Objective in STA is meeting setup and hold requirements.

Typical Chip Component Leaf cells Custom Block Memory Cells Interconnects Control Logic Optimized core .

Interconnects are wires and delay of wires are calculated from wire-load models.STA Tool Requirements     Every block must have a timing model. . Custom blocks are instantiated in the design and they don’t have any netlist representation. NOR etc ) and delay information is in the tech-library. Stamp Modeling is used for these blocks. Synthesized logic is represented in terms of basic cells ( NAND .

Latches D Delay = It1 -q clock q Delay = It2 When Clock = 1 When Clock = 0 Clock to Q delay when enabled = It1 + It2 So this explains why latch is transparent .

Setup and Hold of Flops D -QM -Q Q clock Clock = 0 Clock = 1 Setup Time = 1st stage inverter delay ( only one ) Hold = 2nd stage inverter delay Clock –2-q = Switch delay + 2nd stage inverter delay .

 Period and Waveform: These are mentioned by create_clock command. 6 } clk 0 2 6 10 12 16 20 . Example : create_clock clk –period 10 –waveform ( 2.Understanding clocks  Clock Sources: Sources can be input ports or internal pins .

1 clk .Clock Network  Clock Uncertainty: Also called the skew. clk Flop Flop clka Flop clkb Flop Clock reaches At time T Clock reaches at Time T + δt Uncertainty between two Clocks : set_clock_uncertainty <value> -from clka –to clkb set_clock_uncertainty 0.

set_clock_latency –source 2. Clock latency is specified by set_clock_latency command.Clock Network ( cont …)  • • • Clock Latency: Source Latency: Propagation time from original waveform to the clock definition point in circuit.0 clk . Network Latency: Propagation time from clock definition point to the register clock pin.

Input and Output delays Clk-to-q delay Input delay A B Output delay Output delay = clock latency+ clk-to-q delay + combo delay A + port delay Input delay = port delay + combo delay B Input setup time = input delay – intrinsic setup Total path delay : Output delay + input delay = Td .

.Input and Output delays ( cont…) Intrinsic setup Launch edge Capture edge Max. Time for logic propagation = Tp Td <= Tp Slack = Data Required time – Data arrival time = Tp – Td >= 0 Note: For the capture edge clock skew will be considered. Not shown here for simplicity.

Summary of clock definitions  Commands       used for clock definitions create_clock set_dont_touch_network set_clock_latency set_clock_uncertainty set_input_delay set_output_delay .

Slope Delay = resistance* capacitance Different Plot for Wire length 6 8 fan-out . Parameters cap 1 Unit Resistance 2.Wire-load Models  These are statistical data for calculating interconnect net delays.Unit Cap 3.

Wire-load models ( cont …) Wire Load mode selection Top Top level enclosed wire-load = w1 segmented Lower Modules Wire load = w2 .

425). 680). fanout_length(4. fanout_length(5. 935).000140 . fanout_length(3. 255). capacitance : 0.Wire-Load Models ( Example ) wire_load("R1_3M_AVERAGE") { resistance : 1. 102). fanout_length(2. fanout_length(1. } . slope : 212 .

If there are both constraints defined design compiler tries to meet the more restrictive one. In design this value can be defined using set_max_transition command. In tech-lib this is defined as max_transition.Design Rule Constraints     Maximum Transition: This is the longest time for a net required for its driving pin to change logic values. .

deg) The input pin of each component max_fanout:10 Fanout_load:4 Total fanout_load on pin Z >= 2+3+4+3 = 1 .Design Rule Constraints ( cont …)  Max Fanout: This is a DRC placed on every driving pin of cell . This constraint may be on the entire library or may be specific to cells. fanout_load is set on Fanout_load :2 Z Fanout_load:3 Set_fanout_load:3 Out1 set_max_fanout 8 find ( design .

Max transition and max load control the cap values indirectly and has higher priorities than max_capacitance . . To set the capacitance use set_max_capacitance command.Design Rule Constraints ( cont …)    Maximum Capacitance: This is also DRC and allows to control the capacitance of the nets directly.

set_false_path –from –to SEL .Timing Exceptions  False 1 0 1 0 Path: These are valid paths which are not simulated or executed.

Case Study: Timing Loop module test ( b . wire out2 . assign out1 = ~ (out | b ) . input b . c . output out2 . out2 ). wire out1. c . wire out . (OPT-150) S_4/B S_4/Z Warning: Disabling timing arc between pins 'B' and 'Z‘ on cell 'S_4' to break a timing loop (OPT-314) . assign out2 = out1 & c & out2 . endmodule Loading design 'test' Information: Timing loop detected. assign out = (b & c ).

Timing Exceptions D • Multicyle Paths Huge Combinational Logic Clock set_multicylcle_path -2 –from ff1 –to ff2 .


Back Annotation Standard Delay Format ( SDF ) : This is the file containing delay information on any circuit after successful timing.  SDF file contains two types of delay information: 1. ) Every Delay information has pattern like {min:typ:max}  . Hold etc. Timing Check Delays ( Setup . Combinational Delays ( Point to Point ) 2.

112:1.112)) (0.074:2.Back Annotation ( Cont …) (CELL (CELLTYPE "INT_FDPC") (CELLTYPE "INT_NOT") (INSTANCE out_reg} (DELAY (INSTANCE U168) (ABSOLUTE (DELAY (IOPATH (posedge CP) Q (1.074:2.954:1.568:0.612:1.512:0.568)) (IOPATH (negedge PRE) Q ) (2.612:1.112:1.6 (ABSOLUTE 12)) (IOPATH A Z (0.954:1.954) (1.512) (IOPATH (negedge CLR) Q () (1.568:0.512:0.074) ()) ) ) ) ) ) (CELL Example : SDF File .

Write sdf file from primetime. ( report_annotated_delay and report_annotated_check ) Note: Only internal nets are annotated. Nets connected to ports are not annotated. Method: – – – – • • Open Primetime Read in the design netlist setting proper paths Read in the sdf. .Back Annotation ( Cont …)    What is Back Annotation ? This is the process of verification of the delays those have been extracted in the sdf. Report Annotated delays.

• Data File:This file describes timing data with respect to the mentioned timing arcs.Stamp Models Why Required ? • Modeling timing of custom blocks Components: • Model File: This file describes the ports. . and interface timing arcs. modes.

Timing Check arcs: Setup/Hold .Stamp Models   1. 2. Every arc has a label and this label is referenced in the data file. . clock latency etc. • New Terms ? Timing Arcs: Min/Max arcs: Specifies combinational path directly. Clock period .

Example MODE: read ( COND : rw =1 ) activate the read timing path and associated models. . Please See the Primetime Modeling User Guide for example.Stamp Models ( Cont…)  Timing Mode: Modes are labels that may activate some set of timing arcs.

 Clock is a global constraint.  Back-Annotation is a must looking into postlayout simulation.  Must mention wire-load and operating conditions.Concluding …  Do not synthesize any circuit without constraints. THANKS .