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Contents:
Introduction Block Diagram and Pin Description of the 8051 Registers Memory mapping in 8051 Stack in the 8051 I/O Port Programming Timer Interrupt

Why do we need to learn Microprocessors/controllers?
 The microprocessor is the core of computer systems.  Nowadays many communication, digital entertainment, portable devices, are controlled by them.  A designer should know what types of components he needs, ways to reduce production costs and product reliable.

Different aspects of a microprocessor/controller
 Hardware :Interface to the real world

 Software :order how to deal with inputs

The necessary tools for a microprocessor/controller         CPU: Central Processing Unit I/O: Input /Output Bus: Address bus & Data bus Memory: RAM & ROM Timer Interrupt Serial Port Parallel Port .

ROM. I/O on CPU chip itself  Example : Intel’s x86. Motorola’s 680x0 Many chips on mother’s board CPU GeneralPurpose Microprocessor Data Bus RAM ROM I/O Port Timer Serial COM Port Address Bus General-Purpose Microprocessor System .Microprocessors: General-purpose microprocessor  CPU for Computers  No RAM.

Intel’s 8051. ROM.Microcontroller :  A smaller computer  On-chip RAM.. Zilog’s Z8 and PIC 16X CPU I/O Port RAM ROM Serial Timer COM Port A single chip Microcontroller ..  Example : Motorola’s 6811. I/O ports.

I/O and timer are all on a single chip • fix amount of on-chip ROM. Microcontroller Microprocessor  CPU is stand-alone. power and space are critical • single-purpose . timer are separate  designer can decide on the amount of ROM. RAM.  expansive  versatility  general-purpose Microcontroller • CPU. RAM. ROM. RAM and I/O ports. ROM. I/O. I/O ports • for applications in which cost. RAM.Microprocessor vs.

 An embedded product uses a microprocessor or microcontroller to do one task only.  In an embedded system. there is only one application software that is typically burned into ROM. video game player .  Example : printer. keyboard.Embedded System  Embedded system means the processor is embedded into that application.

availability of software development tools • assemblers. wide availability and reliable sources of the microcontrollers. . emulator. simulator. the number of I/O ports and timers. the amount of ROM and RAM. packaging. C compilers. meeting the computing needs of the task efficiently and cost effectively • speed. debuggers.Three criteria in Choosing a Microcontroller 1. power consumption • easy to upgrade • cost per unit 1. size. technical support 1.

Block Diagram External interrupts Interrupt Control On-chip ROM for program code Timer/Counter On-chip RAM Timer 1 Timer 0 Counter Inputs CPU Serial Port OSC Bus Control 4 I/O Ports P0 P1 P2 P3 TxD RxD Address/Data .

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6(AD6) P0.1 P1.4 (T1)P3.1 (INT0)P3.6 P1.2(AD2 P0.5 (WR)P3.7 RST (RXD)P3.4(A12 ) P ) 2.2 P1.7 XTAL2 XTAL1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Vcc P0.3 P1.Pin Description of the 8051 P1.4(AD4) P0.2(A10) ) P2.1(A9) P2.5(A13 P2.2 (INT1)P3.0 (TXD)P3.6 (RD)P3.3 (T0)P3.7(A15) P2.5 P1.3(AD3) ) P0.4 P1.1(AD1) ) P0.0(AD0 P0.0(A8) 8051 (8031)  .0 P1.3(A11 P2.6(A14 P ) 2.7(AD7) EA/VPP ALE/PROG PSEN P2.5(AD5) P0.

– The voltage source is +5V.Pins of 8051 ( 1/4 )  Vcc ( pin 40 ): – Vcc provides supply voltage to the chip.  GND ( pin 20 ): ground  XTAL1 and XTAL2 ( pins 19.18 ) .

Figure (a). XTAL Connection to 8051  Using a quartz crystal oscillator  We can observe the frequency on the XTAL2 pin. C2 XTAL2 30pF C1 XTAL1 30pF GND  .

– It is a power-on reset.Pins of 8051 ( 2/4 )  RST ( pin 9 ): reset – It is an input pin and is active high ( normally low ) . the microcontroller will reset and all values in registers will be lost.  The high pulse must be high at least 2 machine cycles.  Reset values of some 8051 registers  .  Upon applying a high pulse to RST.

Power-On RESET Circuit Vcc + 10 uF 30 pF 8.Figure (b).2 K 30 pF 11.0592 MHz 31 19 18 EA/VPP X1 X2 9 RST  .

/EA pin is connected to Vcc. – The /EA pin is connected to GND to indicate the code is stored externally.Pins of 8051 ( 3/4 )  /EA ( pin 31 ): external access – There is no on-chip ROM in 8031 and 8032 . – “/” means active low. – For 8051.  /PSEN ( pin 29 ): program store enable – This is an output pin and is connected to the OE pin of the ROM. . – /PSEN & ALE are used for external ROM.

P2. – 8051 port 0 provides both address and data. – The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch.  I/O port pins – The four ports P0.Pins of 8051 ( 4/4 )  ALE ( pin 30 ): address latch enable – It is an output pin and is active high. . P1. and P3. – Each port uses 8 pins. – All I/O pins are bi-directional.

1.7 is the bit 7 ( MSB ) of P0  These 8 bits form a byte.7 ) – Port 2 ( pins 21-28 ): P2 ( P2.7 ) – Each port has 8 pins.Pins of I/O Port  The 8051 has four I/O ports – Port 0 ( pins 32-39 ): P0 ( P0. P3... P2.0 ~ P3.0 ~ P0.X. P1.  Named P0.X..7 ) – Port 3 ( pins 10-17 ): P3 ( P3.7 ) .0 ~ P2.0 ~ P1.  Each port can be used as input or output (bi-direction).X ( X=0..0 is the bit 0 ( LSB ) of P0  Ex : P0.  .7 ) – Port 1 ( pins 1-8 ) : P1 ( P1.X  Ex : P0.

Hardware Structure of I/O Pin  Each pin of I/O ports – Internal CPU bus : communicate with CPU – A D latch store the value of this pin  D latch is controlled by “Write to latch” – Write to latch = 1 : write data into the D latch – 2 Tri-state buffer :  TB1: controlled by “Read pin” – Read pin = 1 : really read the data present at the pin  TB2: controlled by “Read latch” – Read latch = 1 : read value from internal latch – A transistor M1 gate  Gate=0: open  Gate=1: close .

D Latch: .

x 8051 IC .A Pin of Port 1 Read latch TB2 Vcc Load(L1) Internal CPU bus Write to latch D Q P1.X Clk Q P1.X pin M1 TB1 Read pin P0.

X Clk Q P1.X Read latch TB2 Vcc Load(L1) 2.Writing “1” to Output Pin P1. output pin is 1.X pin output 1 TB1 Read pin 8051 IC . write a 1 to the pin Internal CPU bus Write to latch D Q Vcc 1 0 M1 P1.

output pin is 1.X Clk Q output 0 TB1 Read pin 8051 IC . write a 0 to the pin Internal CPU bus Write to latch D Q ground P1.X Read latch TB2 Vcc Load(L1) 2.Writing “0” to Output Pin P1.X pin 0 1 M1 P1.

P1 external pin=High D Q P1.#0FFH Internal CPU bus TB2 Load(L1) 1 1 P1. write a 1 to the pin MOV P1.Reading “High” at Input Pin Read latch 1.X Write to latch Clk Q 0 M1 TB1 Read pin 3. MOV A. Read pin=1 Read latch=0 Write to latch=1 8051 IC .X pin Vcc 2.

X P1. write a 1 to the pin MOV P1.Reading “Low” at Input Pin Read latch 1.#0FFH Internal CPU bus TB2 Load(L1) 1 0 Vcc 2.X pin Write to latch Clk Q 0 M1 TB1 Read pin 3. MOV A.P1 external pin=Low D Q P1. Read pin=1 Read latch=0 Write to latch=1 8051 IC .

and P3 have internal pull-up resisters. P1. P2. it is the same to program P0.X. .  P0 has no internal pull-up resistors and does not connects to Vcc inside the 8051. P2. P2 and P3. – Compare the figures of P1.   However. – P0 is open drain. for a programmer.Other Pins  P1.  All the ports upon RESET are configured as output. and P3 are not open drain.X and P0. – P1.

A Pin of Port 0 Read latch TB2 Internal CPU bus Write to latch D Q P1.x 8051 IC .X Clk Q P0.X pin M1 TB1 Read pin P1.

5 P0.1 P0.4 8951 P0.6 P0.7 Port 0 .2 8751 P0.Port 0 with Pull-Up Resistors Vcc 10 K P0.3 P0.0 DS5000 P0.

1 P3.6 P3.3 P3.5 P3.4 P3.Port 3 Alternate Functions P3 Bit P3.2 P3.7 Function RxD TxD INT0 INT1 T0 T1 WR RD Pin 10 11 12 13 14 15 16 17  .0 P3.

RESET Value of Some 8051 Registers: Register PC ACC B PSW SP DPTR RAM are all zero. Reset Value 0000 0000 0000 0000 0007 0000  .

Registers A B R0 R1 R2 R3 R4 R5 R6 R7 Some 8-bitt Registers of the 8051 Some 8051 16-bit Register PC PC DPTR DPH DPL .

Memory mapping in 8051  ROM memory map in 8051 family 4k 0000H 0000H 8k 0000H 32k 0FFFH DS5000-32 8751 AT89C51 1FFFH 8752 AT89C52 7FFFH from Atmel Corporation from Dallas Semiconductor .

 RAM memory space allocation in the 8051 7FH Scratch pad RAM 30H 2FH Bit-Addressable RAM 20H 1FH 18H 17H 10H 0FH 08H 07H 00H Register Bank 3 Register Bank 2 Stack) Register Bank 1) Register Bank 0 .

Stack in the 8051  The register used to access the stack is called SP (stack pointer) register. When 8051 powered up. 7FH Scratch pad RAM 30H 2FH Bit-Addressable RAM 20H 1FH 18H 17H 10H 0FH 08H 07H 00H Register Bank 3 Register Bank 2 Stack) Register Bank 1) Register Bank 0 .  The stack pointer in the 8051 is only 8 bits wide. which means that it can take value 00 to FFH. the SP register contains value 07.

Timer : .

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TMOD Register:  Gate : When set.  M0 : Mode bit 0.1) is  C/T : Counter/Timer select bit.  M1 : Mode bit 1. only runs while INT(0. timer high. .

IE0: External interrupt 0 edge flag. IT0: External interrupt 0 type flag. IE1: External interrupt 1 edge flag. IT1: External interrupt 1 type flag. TR0: Timer 0 run control bit.TCON Register:         TF1: Timer 1 overflow flag. . TF0: Timer 0 overflag. TR1: Timer 1 run control bit.

Interrupt : .

      ET2 :Enable Timer 2 interrupt. ET1 :Enable Timer 1 interrupt. . ET0 : Enable Timer 0 interrupt. EX1 :Enable External 1 interrupt.Interrupt Enable Register :  EA : Global enable/disable.  --: Undefined. EX0 : Enable External 0 interrupt. ES :Enable Serial port interrupt.