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y Output of combinational circuit at any instant is dependent
upon the its inputs present at that time. y Output of sequential logic is dependent upon not only at its inputs but also upon the internal states that is memory. y Memory state is a function of input to the circuit and its present state.
Classification of Sequential circuits
y Sequential circuits can be classified as y Synchronous Sequential circuits
y Their behavior is defined by the input signals at discrete
intervals of time.
y Asynchronous Sequential circuits
y Their behavior is defined by the order in which the input signals
change and can be affected by any instant of time.
y Flip-Flops are the memory elements of the sequential circuit. y They are binary cells, capable of storing only one bit of
information. y A flip- flop circuit has two outputs, one for normal value and other complement value of bit stored in it. y A flip flop can maintain its state indefinitely until directed by input signal to switch states. y They are various types of flip flops depending upon the variation of the manner in which inputs affect the binary state.
RS Flip Flop
y It is constructed with two NOR gates or two NAND gates. y The cross-coupled connection from the output of one gate to the
input of other gate constitutes the feedback path. That·s why known as asynchronous sequential circuit.
y Flip Flop has two useful states
y Set State when Q=1 and Q·=0 y Clear state when Q=0 and Q·=1
y SR = 11 is avoided y Outputs Q and Q· are not complementary
Clocked RS Flip Flop
y The clocked RS Flip Flop is synchronous circuit, which respond to
inputs levels during the occurrence of clock pulse y It consists basic NOR flip flop and two AND gates. y The outputs of two AND gates remains zero as long as the clock pulse is 0, regardless the R and S inputs. y R and S inputs are allowed to reach the basic flip flop circuit only when clock pulse is 1.
D Flip Flop
y The D Flip Flop receives its designation by its ability to transfer ´dataµ. y It consists of basic NAND flip flop and two NAND gates for clocked RS flip
flop y D input is directly goes to S input and its complement goes to R input. y When CP=0, the gates 3 and 4 produces 1 regardless of other inputs
JK flip flop
y A JK flip flop is the refinement of the RS flip flop in that the
indeterminate state of RS type is defined in JK type. y Inputs J and K behave like S and R to set and clear the flip flop. y When inputs are applied to both J and K simultaneously, the flip flop switches to its complement state, that is if Q=1, switches to Q=0 and vice versa.
T Flip Flop
y T flip flop is a single input version of JK flip flop. y The designation of T flip flop comes from the ability to ´toggleµ
state. y Regardless the present input of the flip flop it assumes the complement state when the clock pulse occurs while input T is logic 1
Master Slave Flip Flop
Analysis of Clocked Sequential Circuits
Step 1: State Table
Step 2: State Diagram
Step 3: State Equations
Finally we have«
Step 4: Implementation of circuit
Example: How to show implementation of sequential circuit from state equations