cmpe22203processppt.

ppt 1
VLSÌ Digital Systems Design
CMOS Processing
cmpe22203processppt.ppt 2
Si Purification
· Chemical purification of Si
· Zone refined
÷ Ìnduction furnace
÷ Si ingot melted in localized zone
÷ Molten zone moved from one end to the other
÷ Ìmpurities more soluble in melt than in solid
÷ Ìmpurities swept to one end of ingot
· Pure Si = intrinsic Si (impurities < 1:10
9
)
cmpe22203processppt.ppt 3
Czochralski Technique for
Single-Crystal Ìngot Growth, Melt
· Remelt pure Si
÷ Si melting point = 1412 C
÷ Quartz crucible with graphite liner
÷ RF induction heats graphite
· Dip small Si seed crystal into melt
÷ Seed determines crystal orientation
cmpe22203processppt.ppt 4
Czochralski Technique for
Single-Crystal Ìngot Growth,
Freeze
· Withdraw seed slowly while rotating
÷ Withdrawal and rotational rates determine ingot
diameter
÷ 30-180 mm/hour
÷ Largest current wafers = 300 mm
· Si crystal structure = diamond
cmpe22203processppt.ppt 5
Single-Crystal Ìngot to Wafer
· Diamond saw cuts grown crystal into slices =
wafers
÷ 0.25-1.00 mm thick
· Polish one side of wafer to mirror finish
cmpe22203processppt.ppt 6
idation Converts Si to Si
2
· Wet oidation
÷ idizing atmosphere contains water vapor
÷ 900-1000 C
÷ Rapid
· Dry oidation
÷ idizing atmosphere pure oygen
÷ 1200 C
· Volume of Si
2
= 2 volume of Si
÷ Si
2
layer grows above Si surface approimately
as far as it etends below Si surface
cmpe22203processppt.ppt 7
Dopants
· Si is semiconductor:
R
conductor
< R
intrinsicSi
< R
insulator
· Dopants = impurity atoms
÷ Can vary conductivity by orders of magnitude
· Dopant atom displaces
14
Si atom in crystal
· Each
14
Si atom shares 4 electrons
with its 4 neighbors in the crystal lattice,
to form chemical bond
÷ Group (column) ÌV-A of Periodic Table
cmpe22203processppt.ppt 8
Donor Atoms Provide Electrons
· Group V-A of Periodic Table
· Phosphorus,
15
P, and Arsenic,
33
As
· 5 electrons in outer shell, 1 more than needed
· Ecess electron not held in bond is free to
drift
· Ìf concentration of donors > acceptors,
n-type Si
cmpe22203processppt.ppt 9
Acceptor Atoms Remove Electrons
from Nearby Atoms
· Group ÌÌÌ-A of Periodic Table
· Boron,
5
B
· 3 electrons in outer shell, 1 less than needed
· Ìncomplete bond,
accepting electron from nearby atom
· Movement of electron is effective flow of
positive current in opposite direction
· Ìf concentration of acceptors > donors,
p-type Si
cmpe22203processppt.ppt 10
Epitay
· Greek for "arranged upon¨ or "upon-ordered¨
· Grow single-crystal layer
on single-crystal substrate
· Homoepitay
÷ Layer and substrate are same material
· Heteroepitay
÷ Layer and substrate differ
· Elevate temperature of Si wafer surface
· Subject surface to source of dopant
cmpe22203processppt.ppt 11
Deposition and Ìon Ìmplantation
· Deposition
÷ Evaporate dopant onto Si wafer surface
÷ Thermal cycle
· Drives dopant from Si wafer surface into the bulk
· Ìon Ìmplantation
÷ Energize dopant atoms
÷ When they hit Si wafer surface,
they travel below the surface
cmpe22203processppt.ppt 12
Diffusion
· At temperature > 800 C
· Dopant diffuses from area of high
concentration to area of low
· After applying dopant, keep temperature as
low as possible in subsequent process steps
cmpe22203processppt.ppt 13
Common Dopant Mask Materials
· Photoresist
· Polysilicon (gate conductor)
· Si
2
= Silicon dioide (gate insulator)
· SiN = Silicon nitride
cmpe22203processppt.ppt 14
Selective Diffusion Process
1.Apply dopant mask material
to Si wafer surface
÷ Dopant mask pattern includes windows
2.Apply dopant source
3.Remove dopant mask material
cmpe22203processppt.ppt 15
Positive Resist Eample
· Apply Si
2
· Apply photoresist
÷ PR = acid resistant coating
· Pass UV light through reticle
÷ Polymerizes PR
· Remove polymerized areas with organic
solvent
÷ Developer solution
· Etch eposed Si
2
areas
cmpe22203processppt.ppt 16
Lithography Pattern Storage,
Technique 1
· Mask
÷ Two methods for making
1.Electron beam eposure
2.Laser beam scanning
÷ Parallel processing
cmpe22203processppt.ppt 17
Lithography Pattern Storage,
Technique 2
· Direct Write
÷ Two writing schemes
1.Raster scan
2.Vector scan
÷ Pro
· No mask epense
· No mask delay
· Able to change pattern from die to die
÷ Con
· Slow
· Epensive
cmpe22203processppt.ppt 18
Lithography Pattern Transmission
· Four types of radiation to convey pattern to
resist
1.Light
· Visible
· Ultraviolet
2.Ìon
3.X-ray (does not apply to direct write)
4.Electron
cmpe22203processppt.ppt 19
Lithographic Printing
· Contact printing
· Proimity printing
· Projection printing
÷ Refraction projection printing
÷ Reflection projection printing
÷ Catadioptric projection printing
cmpe22203processppt.ppt 20
Contact and Proimity Printing
· Contact printing
÷ 0.05 atm < pressure < 0.30 atm
· Proimity printing
÷ 20 µm < mask-wafer separation < 50 µm
÷ Pro
· Low cost
· Mask lasts longer because no contact
÷ Con
· Ìnferior resolution
cmpe22203processppt.ppt 21
Projection Printing
· Projection printing
÷ Higher resolution than proimity printing
· Numerical Aperture
÷ Ìt was once believed that a high NA
is always better.
÷ Ìf NA too low, can't achieve resolution
÷ Ìf NA too high, can't achieve depth of field
· DF = lambda/(2 NA
2
)
cmpe22203processppt.ppt 22
Refraction Projection Printing
· High resolution
· To transmit deep UV, optical components are
÷ Fused silica
÷ Crystalline fluorides
· Lenses are fused silica
÷ Chromatic
÷ Source bandwidth must be narrow
· KrF laser
cmpe22203processppt.ppt 23
Reflection and Catadioptric
Projection Printing
· Reflection projection printing
÷ Polychromatic, larger spectral bandwidth
· Catadioptric projection printing
÷ Combines reflecting and refracting components
÷ Larger spectral bandwidth
÷ More than one optical ais
· Aligning optical elements can be very difficult
cmpe22203processppt.ppt 24
Minimum Channel Length
and Gate Ìnsulator Thickness
Ìmprove Performance
· Ì
ds
= Beta(V
gs
÷ V
t
)
2
/ 2
· Beta = MS transistor gain factor
= ( (mu)(epsilon) / t
o
)( W / L )
· mu = channel carrier mobility
· epsilon = gate insulator permittivity (Si
2
)
· t
o
= gate insulator thickness
· W / L = channel dimensions
cmpe22203processppt.ppt 25
Silicon Gate Process, Steps 1 & 2
· Ìnitial patterning Si
2
layer
÷ Called field oide
÷ Thick layer
÷ Ìsolates individual transistors
· Thin Si
2
layer
÷ Called gate oide
÷ Also called thino
÷ 10 nm < thin oide < 30 nm
cmpe22203processppt.ppt 26
Silicon Gate Process, Step 3
· Polysilicon layer
÷ Polycrystalline = not single crystal
÷ Formed when Si deposited
· Has high R when undoped
· Used as high-R resistor in static memory
÷ Used as
· Short interconnect
· Gate electrode
÷ Most important:
allows precise definition of source and drain electrodes
÷ Deposited undoped on gate insulator
÷ Then doped at same time as source and drain regions
cmpe22203processppt.ppt 27
Silicon Gate Process, Steps 4 & 5
· Eposed thin oide, not covered by poly,
etched away
· Wafer eposed to dopant source
by deposition or ion-implantation
1.Forms n-type region in p-type substrate
or ;.0;078,
· Source and drain created in shadow of gate
· Si gate process called self-aligned process
2.Polysilicon doped, reducing its R
cmpe22203processppt.ppt 28
Silicon Gate Process, Final Steps
· Si
2
layer
· Contact holes etched
· Metal (Al, Cu) evaporated
· Ìnterconnect etched
· Repeat for further interconnect layers
cmpe22203processppt.ppt 29
Parasitic MS transistors
· Formed from
÷ Diffusion regions of unrelated transistors
· Act as parasitic source and drain
÷ Thick (t
fo
) field oide between transistors
overrun by metal or poly interconnect
· Act as parasitic gate insulator and
· parasitic gate electrode
· Raise threshold voltage of parasitic transistor
÷ Make t
fo
thick enough
÷ Add "channel-stop¨ diffusion between transistors
cmpe22203processppt.ppt 30
Four Main CMS Processes
1. n-well process
2. p-well process
3. Twin-tub process
4. Silicon on insulator
cmpe22203processppt.ppt 31
n-well Process, n-Well Mask A
· Mask A defines n-well
· Also called n-tub
· Ìon implantation produces shallower wells than
deposition
÷ Deeper diffusion also spreads further laterally
÷ Shallower diffusion better for more closely-spaced
structures
cmpe22203processppt.ppt 32
n-well Process, Active Mask B, Page 1
· Mask B defines thin oide
· Called active mask, since includes
÷ Area of gate electrode
÷ Area of source and drain
· Also called thino
· thin-oide
· island
· mesa
cmpe22203processppt.ppt 33
n-well Process, Active Mask B, Page 2
· Thin layer of Si
2
grown
· Covered with SiN = Silicon Nitride
÷ Relative permittivity of Si
2
= 3.9
÷ Relative permittivity of Si
3
N
4
= 7.5
÷ Relative permittivity of comb. = 6.0
· Used as mask for steps for
channel-stop mask C and
field oide step D
cmpe22203processppt.ppt 34
n-well Process, Channel-Stop Mask C
· Channel-stop implant
· Raises threshold voltage of parasitic transistors
· Uses p-well mask
= complement of n-well Mask A
÷ Where no nMS, dope p-substrate to be p+
cmpe22203processppt.ppt 35
n-well Process, Field ide Step D
· Thick layer of Si
2
grown
· Grows where no SiN
· Grows where no mask B = no active mask
· Called LCS = LCal idation of Silicon
cmpe22203processppt.ppt 36
n-well Process, Bird's Beak
· Just as dopant diffuses laterally as well as
vertically:
· Field oide also grows laterally,
underneath SiN
· Tapering shape called bird's beak
· Causes active area to be smaller
÷ Reduces W
· Some techniques limit this effect
÷ SWAMÌ = SideWAll Masked Ìsolation
cmpe22203processppt.ppt 37
n-well Process, Planarity
· Field oide higher than gate oide
· Conductor thins or breaks
· Problem called step coverage
· To fi,
pre-etch field oide areas
by 0.5 field oide depth
cmpe22203processppt.ppt 38
n-well Process, V
t
Adjust,
After Field ide Step D
· Threshold voltage adjust
· ptional
· Uses n-well mask A
· 0.5 v < V
tn
< 0.7 v
· -2.0 v < V
tp
< -1.5 v
· Add a negatively charged layer at Si-Si
2
· Lowers channel
· Called "buried channel¨ device
cmpe22203processppt.ppt 39
n-well Process, Poly Mask E
· Mask E defines polysilicon
· Poly gate electrode
acts as mask for source & drain regions
· Called self-aligned
cmpe22203processppt.ppt 40
n-well Process, n+ Mask F
· n+ mask defines active areas to be doped n+
÷ Ìf in p-substrate,
n+ becomes nMS transistor
÷ Ìf in n-well,
n+ becomes ohmic contact to n-well
· Also called select mask
cmpe22203processppt.ppt 41
n-well Process, LDD Step G
· LDD = Lightly Doped Drain
1. Shallow n-LDD implant
2. Grow spacer oide over poly gate
3. Second, heavier n+ implant
÷ Spaced from edge of poly gate
4. Remove spacer oide from poly gate
· More resistant to hot-electron effects
cmpe22203processppt.ppt 42
n-well Process, p+ Mask H
· p+ diffusion
· Uses complement of n+ mask
· p+ mask defines active areas to be doped p+
÷ Ìf in n-well,
p+ becomes pMS transistor
÷ Ìf in p-substrate,
p+ becomes ohmic contact to p-substrate
cmpe22203processppt.ppt 43
n-well Process, Si
2
,
After p+ Mask H
· Entire chip covered with Si
2
· No need for LDD for pMS
÷ pMS less susceptible to to hot-electron effects
than nMS
· LDD = Lightly Doped Drain
cmpe22203processppt.ppt 44
n-well Process, Contact Mask Ì
· Defines contact cuts in Si
2
layer
· Allows metal to contact
÷ Diffusion regions
÷ Poly gates
cmpe22203processppt.ppt 45
n-well Process, Metal Mask J
· Wire it up!
· n-well Process, Passivation Step
÷ Protects chip from contaminants
· Which can modify circuit behavior
÷ Etch openings to bond pads for Ìs
cmpe22203processppt.ppt 46
p-Well Process
· Transistor in native substrate
has better characteristics
· p-well process has better pMS than
n-well process
· nMS have better gain (beta) than pMS
cmpe22203processppt.ppt 47
Twin-Tub Process
· Separately optimized wells
· Balanced performance nMS & pMS
1. Start with epitaial layer
· Protects against latchup
2. Form n-well and p-well tubs
cmpe22203processppt.ppt 48
Silicon-on-Ìnsulator Process
· Uses n-islands and p-islands of silicon
on an insulator
÷ Sapphire
÷ Si
2
· No n-wells, no p-wells
cmpe22203processppt.ppt 49
SÌ Process Advantages
· No n-wells, no p-wells
÷ Transistors can be closer together
÷ Higher density
· Lower parasitic substrate capacitance
÷ Faster operation
· No latchup
· No body effect
· Enhanced radiation tolerance

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