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Design of 4-bit ALU

Ashwini Nanjappa Sravani Sanapala Vanita Ramaswamy


Advisor: Dr.David Parent Fall 2004
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Agenda
Abstract Introduction Why Simple Theory Project Details Block Diagram Schematics Layout Verification: DRC, Extract, LVS Simulation Results Cost Analysis Conclusion

Abstract
Aim of the project is to design a 4-bit ALU to perform seven arithmetic operations and four logic operations. The circuit is designed so as to meet the following specifications:
Frequency: 200MHz Power : 23W/cm2 Area : 400x400m2

The results are verified with AMI06 technology, Spectre spice simulation tools.
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Introduction
ALU is a fundamental unit of several combinational circuits. Learning ALU design aids in designing complex circuits. All the arithmetic operations are performed by the Carry look ahead adder using a B-input logic.The Binput logic is based on the equation Y=BiS0+BiS1 The logic operations are performed using basic gates. Two select lines are used to perform the operations on two 4 bit inputs in both the units. The third select line is used to select either one of the units.
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Introduction Contd.
Function Table for ALU
M 1 1 1 1 1 1 1 1 0 0 0 0 S1 0 0 0 0 1 1 1 1 X X X X S0 0 0 1 1 0 0 1 1 0 0 1 1 CIN 0 1 0 1 0 1 0 1 0 1 0 1 Operation Out =A Out=A+1 Out =A+B Out=A+B+1 Out=A+B Out=A+B+1 Out=A-1 Out=A Out=A & B Out=A | B Out=A^B Out=A Function Transfer A Increment A Addition Add with Carry A plus 1s complement of B Subtraction Decrement A Transfer A AND OR XOR NOT(1sComplement) 5

Project Details
The B-input logic with CLA reduces the complexity of the circuit.The CLA consists of propagate/generate block, carry generator and sum block. The critical path for the circuit is from the input B2 to the output out3 for the subtraction operation. 4to1 Mux selects the logic operations based on the select lines in the logic unit. Finally a 2to1 Mux selects between arithmetic and logic unit. Mux based D-flipflops are used in the circuit with .7ns setup and hold time. The sizing and layout of the gates are cell based.
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Project Details Contd


Longest path has 17 logic levels including the input and output flipflops. A load of 20fF is assumed as the load for long path calculation from DFF.

Long Path Calculation(Arithmetic Unit)

PHL=5ns/(13+4)=0.29ns

for each logic level

4-Bit ALU Block Diagram

Logic Verified in NC-Verilog

B-Input Logic

Propagate/Generate Carry Generator


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4-bit Arithmetic Unit Schematic

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1-Bit Logic Unit Schematic

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ALU Test Bench Schematic

The inputs (A,B,CIN) and select lines (M,S0,S1)are set for worst case.
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Layout of 4-Bit ALU

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Verification
DRC Extracted

LVS Report

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Simulation Result : Subtraction

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Simulation Result: XOR

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Simulation Result: Power For 4-bit ALU

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Cost Analysis
Time is money ! Time spent on each phase is:
 Design and Implementation Phase:
 Logic design and NC Verilog check 1 Week.  Transitor level design and simulation 2 Week.  Timing check, Stick Diagram and Layout- 1 week.

 Verification and Testing Phase:


 Post extraction, Power simulation & Time check - 1day

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Conclusion
Designed and tested a 4 bit ALU that performs seven arithmetic and four logic operations at : 200 Mhz clock Power: 11.6W/cm2 Area: 333x412 m2 The project meets all the given specifications This design concept can be a building block for higher bit ALU ex. 16-bit, 32-bit
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Acknowledgement
Thanks to Professor David Parent for his guidance throughout the project. Thanks to Cadence Design Systems for the VLSI lab. Thanks to TA for helping us in the lab. Thanks to our classmates.

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