Combinational logic Reg .STATE MACHINE ENCODING y It is a computational model y Implemented using Boolean functions and Flip-Flops.

State Machine Synthesis Process: ‡ ‡ It generates a gate-level circuit based on machine·s specifications. 2. It allocates state register and assigns binary codes to represent symbolic states. State Transition Graph: ‡ Describes state machine in terms of its input and output at that particular state and its transition to the next state.this process is called ´Encodingµ. .y Two things have to be taken into account for designing State Machine :  State Transition Graph  State Machine Synthesis Process 1.

normally minimum number of bits that are enough to represent all states are used. etc. . power . ‡ To optimize the design.‡ Encoding of state machine determines the quality of the gate- level circuit in terms of area . speed .

.Transition Analysis of State Encoding y Here two parameters are taken into account :  Expected number of bit transitions. Consider the figures shown below which represent functionally identical state machines M1 and M2 with different encodings.  Expected number of transitions of output signals.

4 11  Binary codes within the bubbles represent state encoding . .3 0.1 11 0.4 00 0.  E[M] represents expected number of state bit transitions and is given by sum of products of edge probabilities and their associated number of bit flips as given by encoding.1 0.  Sum of all the probability must equal 1.1 0.1 0.3 01 0.1 01 00 0.  Labels at the transition edges represent the probabilities that transitions will occur.1 0.0.

4 + 1* 0.1 + 2 * 0.y Expected state transitions of the above figure are given as :  E[M1] = 2 * 0. 2. Fewer transitions lead to lower power dissipation.4 + 1* 0.1 = 1.1 = 1. .0 ‡ Machines with lower E[M] are more power efficient because : 1. Fewer transitions are propagated into combinational logic of machine.3 + 1* 0. ‡ A large state machine dissipates more power because more gates and nodes toggle in the circuit.3+ 2* 0.6  E[M2] = 1* 0.1 + 1* 0.

the area has to be increased.  Problem 3 : If states are encoded to minimize power dissipation .e encode the state incident to high probability edges to reduce E[M].Design trade offs in State Machine Encoding y State encoding affects power dissipation as well as area of the machine. .  Problem 1 : It is very difficult to find the encoding technique that minimizes the state-bit transition E[M].  Problem 2 : Logic synthesis system can perform automatic state encoding for area minimization but it may not be desirable for power dissipation because the expected transition is high.  One solution to above problems is to use a subset of states that spans high probability edges i.

y To measure the probabilities of state machine behavioral level simulation can be used.y For example. edges incident to states like ´resetµ and ´interruptµ states of a CPU have very low transition probability whereas states like ´instruction fetchµ and ´memory accessµ have very high probabilities. .

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