CENTRAL PROCESSING UNIT (CPU

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The solution algorithm consists of series of steps These steps are broken into smaller steps 1 steps = 1 machine instruction Each instruction is executed by carrying out a sequence of rudimentary/basic operations These operations anda how they are generated is one of the main topic of this course

1

FUNDAMENTAL CONCEPT

The instructions are loaded in the sequential locations in main memory Instructions are fetch from successive memory locations PC (program counter) keeps track address of the next memory location containing next instruction (PC= PC +1)

2

THREE STEPS OF EXECUTION 1 INSTRUCTION


1. Fetch the contents of memory location pointed by PC, then loaded into IR (instruction register) IR [[ PC ]] 2 . Increment PC : PC  PC +1 3 . Carry out the action by the instruction in the IR If the instruction more the 1 word, step 1 and 2 must be repeated as necessary
3

SINGLE BUS ORGANIZATION 4 .

OPERATION FUNCTIONS      Fetch content of memory location and load into a CPU register (M R) Store data from CPU register into memory location (R M) Transfer from 1 register to another register (R  R) Perform arithmetic & logic operation and store the result in CPU register How each function is implemented in detail ? 5 .

Fetching a word from Memory    Specify the address of memory location containing the instruction or operand. sent from CPU MAR memory CPU send Read control signal After completing the operation. memory send the WMFC (wait for Memory Function Completed) signal to CPU. it means instruction/operand (requested) is available in the MDR 6 .

MAR  [R1] 2. Wait for MFC signal 4. R2  [MDR] This type of data transfer is asynchronous transfer (combination of read request and MFC signal) 7 .Sequence of Read operation       Assumed memory address is in R1 and data from memory to be loaded into R2 1. Read 3.

Storing a Word in Memory     Address is loaded into MAR Data (to be written) is loaded into MDR Write signal is issued After completion of the operation. the memory will send the MFC signal 8 .

MAR  [R1] 2.Sequence of Write operation     Assumed data to be stored is in R2 and memory address is in R1 1. MDR  [R2]. Wait for MFC 9 . Write 3.

Register Transfer      To control the gate for input the data into Ri is used control signal Ri in To control the gate for output the data to the bus is used control signal Ri out To transfer contents of R1 to R4 : R1 out is set to 1  output to the bus R4 in is set to 1  load from the bus into R4 10 .

Arithmetic & Logic operation  To add two numbers :   First operand is hold on register Y Second operand is gated into the bus   The result is store temporarily in reg Z Example : Add the contents of R1 to R2 and store the result in R3 11 .

R3in The signal whose name are given.Signal control to ADD 2 numbers       Step Action 1. Yin 2. Add. R2out. Zout. is set to 1 All other signals are inactive 12 . Zin 3. R1out.

Add.) Store the result to register or memory 13 . Fetch the instruction 2. etc. Executions :    Fetch operand(s) Perform the operations (Move.Execution a Complete Instruction    The actions : 1.

5. Add.Sequence control for instruction ADD LOC. R1in. Pcout. 14 . 6. Read. 2. End. 7. R1 1. MARin. IRin Address_field_of_IRout. Zin Zout. Wait_for_MFC MDRout. Read R1out. Add. Set_carry_in_to ALU. 3. 4. PCin. Wait_for_MFC MDRout. Yin. MARin. Zin Zout. Clear Y.

DOUBLE BUS ORGANIZATION (1) 15 .

register input connect to bus B Two buses connected through bus tie G. normally open.DOUBLE BUS ORGANIZATION (2)     Register output connect to bus A. two buses disconnected Do not need register Z. to close use control signal Genable When bus tie G disable. because output from reg Z can be placed on bus B. no possible conflict with the data on bus A 16 .

Genable. R2in 17 .[R1] + [R2] can be perform as follows : 1. Add. Genable. R3in The operation R2 <.[R1] + [R2] can be perform as follows : 1. R1out. R2out. Yin 2. ALUout. ALUout. Yin 2. R2out.DOUBLE BUS ORGANIZATION (3)       Ex : the operation R3 <. Add. R1out.

Internal Register 18 .

data stored is locked. until Zin = 1 again 19 .Internal Register    Flip-flop : 1 bit of Register Z If Zin = 1 -> state = data on the bus If Zin chenge to 0.

Branching     Branching : replacing contents of PC by branch address Branch address = update PC + offset X Offset X is given in the address field of the branch instruction 2 type of branching :   Unconditional Conditional 20 .

Zin Zout. Clear Y. Zin Zout. 4. 3. 6. 21 . 5. ADD. MARin. Yin Address_field_of_IRout. Read. Wait_for_MFC MDRout. End. PCin. Set carry-in to ALU. IRin PCout. Add.Sequence control : Branch Unconditional 1. 2. PCin. Pcout.

to know the result of the last computing operation . otherwise is 0 Z (zero) : set to 1 if the result is 0.CONDITION CODE      Condition code flag is represent by a bit in the status register of the processor. otherwise is 0 V (overflow) : set to 1 of overflow occurs C (carry) : set to 1 if there are carry out result 22 . there are : N (negative) : set to 1 if the result is negative.

STATUS REGISTER 23 .

24 . Add. If N then End. Zin 6.Conditional Brach : Branch on Negative Pcout. ADD. PCin. do step 5 and 6 1. if N= 0 then End. Wait_for_MFC 3. Set carry-in to ALU. Step 4 : N is cheked. if N=1. Clear Y. Address_field_of_IRout. Yin. PCin. Zin 2. 5. IRin 4. MDRout. MARin. Zout. End. Zout. Read. PCout.

Generating control signal to execute instructions    2 categories : A) Hardwired B) Microprogrammed Control 25 .

Hardwired Control  The main part are decoder/encoder. simpy a combinational circuit to generate signal control. depending on the state of all its input :    Contents of control counter contents of instruction register Contents of condition code and other status flags 26 .

Hardwired Control 27 .

PCout etc.)   For any instruction loaded into IR.Hardwired (cont. 28 . one of the output lines INS1 to INSm is set to 1 All input signal to encoder block will be combined to generate individual control signal as Yin.

BR + …. End = T7.N + T4..ADD + T6.BRN + …. 29 .Encoder Zin = T1 + T6..ADD + T5.BR + (T6.N).

Microprogrammed Control    Control signal are generated by a program similar to machine language program Each control signal is represent by individual bit stored in μprogrammed memory/control store Control unit generate control signal by reading sequentially control word from control store using μPC 30 .

Basic Organization of Microprogrammed Control Unit 31 .

Example of Microinstruction in µprogrammed memory 32 .

.919165.963  .

511.963 :5.:5 #6.7..650619/360233/ 064/51.6536.55:.115.6% 656 .3..6 3357..:5.0  .3.6. 69.90..35:!&.6!&4::.659.9191 065.3065.

50619 5' '  ' %  51'  ' %  ' ! ' ! %!   .

69 65.0967969.15:85..053.69:5#  .963691964 065.963:5.959.963:5.64.3:979:5.065.59.:.69157969.3/ 9.963:.0065.4 :43.4414469065.5.9.963:5./511..1/..7969.33065.963 65.44165.7969.4 .9635.3.963 :.3 /.

 ...656 0967969.9635.44165.:0"9.5.

4736 0965:.4414469  ..655 7969.90.

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