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Chapter 2: System Interconnection

Phm Tun Sn

Source: Computer Organization and Architecture 6th Edition - William Stallings

Content Interconnection Structure Bus Interconnection

Interconnection Structure
All the modules (components) must be connected:
Memory Input/Output CPU Computer
Central Processing Unit Main Memory

Interconnection structure includes collection of paths connecting various modules The design of interconnection structure depends on the exchanges between modules

Systems Interconnection

Input Output

Types of Exchange of Computer Modules

Memory Connection Receives and sends data Receives addresses (of locations) Receives control signals
Read Write Timing

Input/Output Connection
Similar to memory from computers viewpoint
Write (Output)
Receive data from computer Send data to peripheral

Read (Input)
Receive data from peripheral Send data to computer

Receive control signals from computer Send control signals to peripherals Receive addresses from computer
e.g. port number to identify peripheral

Send interrupt signals (control) to the processor

CPU Connection Reads instruction and data Writes out data (after processing) Sends control signals to other units Receives (& acts on) interrupts

Bus Interconnection
A communication pathway connecting two or more devices Usually broadcast Must insure only 1 device places information onto a bus at any given time Typical buses consist of 50-100 lines Often grouped
A number of channels in one bus e.g. 32 bit data bus is 32 separate single bit channels

Data Bus Carries data

Remember that there is no difference between data and instruction at this level

Width is a key determinant of performance

8, 16, 32, 64 bit

Address bus Identify the source or destination of data

e.g. How CPU can read a word of data from a given location in memory ?

Bus width determines maximum memory capacity of system

e.g. 8080 has 16 bit address bus giving 64k address space

Control Bus Controls access to and use of the address and data bus Control and timing information
Memory read/write signal Interrupt request Clock signals

Single Bus Problems Lots of devices on one bus leads to:

Propagation delays
Long data paths mean that co-ordination of bus use can adversely affect performance

If aggregate data transfer approaches bus capacity

Most systems use multiple buses to overcome these problems

High-speed limited access buses close to the processor Slower-speed general access buses farther away from the processor

Traditional (ISA) (with cache)

High Performance Bus

Elements of Bus Design Bus Width Bus Types Method of Arbitration Data Transfer Type Timing

Bus Types Dedicated

Separate data & address lines

Shared lines Address valid or data valid control line Advantage - fewer lines Disadvantages
More complex control Reduce performance

Bus Arbitration (1) Process of insuring only 1 devices places information onto the bus at a time More than one module controlling the bus
e.g. CPU and DMA controller

Only one module may control bus at one time Arbitration may be centralized or distributed

Bus Arbitration (2) Centralised

Single hardware device controlling bus access
Bus Controller Arbiter

May be part of CPU or separate

Each module may claim the bus Control logic on all modules

Master - slave mechanism

Master is given control of the bus and can place information onto it Slave receives the information from the master

Data Transfer Type

Timing Co-ordination of events on bus Synchronous

Events determined by clock signals Control Bus includes clock line A single 1-0 is a bus cycle (clock cycle) All devices can read clock line Usually sync on leading edge Usually a single cycle for an event E.g. PCI bus

Synchronous Timing Diagram

Asynchronous Timing The occurrence of one event follows and depends on the occurrence of a previous event More flexible than synchronous bus but more complicated as well Accomodates wider range of device speeds

Asynchronous Timing Read Diagram

Asynchronous Timing Write Diagram

PCI Bus Peripheral Component Interconnection High-bandwidth bus Intel released to public domain 32 or 64 bit 50 lines 66 MHz ~ 4.224 Gbps

PCI Bus Lines (required) Systems lines

Including clock and reset

Address & Data

32 time mux lines for address/data Interpret & validate lines

Interface Control Arbitration

Not shared Direct connection to PCI bus arbiter

Error lines

Typical Desktop System

Excercises (1)
1. Consider a hypothetical microprocessor having 16-bit address bus. What is the maximum memory address space that the processsor can directly if it connected to a 16-bit memory? 2. A microprocessor is clocked at a rate of 5 GHz
a. How long is a clock cycle? b. What is the duration of a synchronous memory read operation in the lesson?

3. Consider a microprocessor with a 16-bit external data bus, driven by an 8 MHz input clock. Assume that this microprocessor has a bus cycle whose minimum duration equals 4 input clock cycle. What is the maximum data transfer rate across the bus that this microprocessor can sustain, in bytes/s?

Exercises (2)
4. For a synchronous read operation (in the lesson), the memory module must place the data on the bus sufficiently ahead of the falling edge of the Read signal to allow for signal settling. Assume a microprocessor bus is clocked at 10 MHz and the Read signal begins to fall in the middle of the second half of T3
a. Determine the length of the memory read instruction cycle b. When, at the latest, should memory data be place on the bus? Allow 20 ns for the settling of the data lines

4. Consider the microprocessor that has a memory read timing as shown in the lesson. Affter some analysis, a designer determine that the memory fall short of providing read data on time by about 180 ns. How many waiting states (clock cycles) need to be inserted for the proper system operation if the bus clock rate is 8 MHz?