Review Quiz

Chapter 4 The Processor 1

If we would like to add the ORI instruction, what extensions should we include in the datapath ?

Chapter 4 The Processor 2

A zeroextended unit + mux

If we would like to add the sltiu instruction, what extensions should we include in the datapath ?

Chapter 4 The Processor 3

A zeroextended unit + mux

Pipelining is an implementation technique that can

1) Reduce the operation latency 2) Increase the instruction throughput 3) Reduce the cost of the processor 4) Simplify the control 5) Reduce the power consumption of the processor
Answer: 2
Chapter 4 The Processor 4

Compare to the single cycle implementation, what has been added to the data path in the pipelined implementation?
1) More memory units 2) Pipelined registers 3) More multiplexers 4) More general purpose registers 5) More instruction fetch units
Answer: 2,3
Chapter 4 The Processor 5

Why a 5-stage pipelined implementation does not give a 5x increase in instruction throughput over a single cycle implementation?
1) Stages may not be perfectly balanced 2) Overhead from pipelined registers 3) Data hazards 4) Control hazards 5) Imprecise interrupts
Answer: 1,2,3,4
Chapter 4 The Processor 6

How can we reduce the performance penalty of data hazards?

1) 2) 3) 4) 5) Use data forwarding Use data bypassing Stall the machine Inserting bubbles Re-schedule the instructions

Answer: 1, 2, 5
Chapter 4 The Processor 7

Which of the following C statements have high data hazards?

1) A = B + C + D + E + F*G (all variables are FP) 2) A = B [ C [ D[i] ] ]; (all variables are integers) 3) for (i=0; i<n; i++) a[i] = b[i]+1; 4) A = a->b->c->d; 5) for (i=0; i<1000; i++) sum += a[i]; (sum and a[] are unsigned integers)

Answer: 1, 2, 4
Chapter 4 The Processor 8

The following loop does not get much speed up from a pipelined processor. Why?

while (a > 0) a = *a -> next;

1) Intensive data hazards 2) Intensive control hazards 3) Intensive structure hazards 4) Compiler should schedule the code 5) Not enough pipelined stages
Answer: 1, 2
Chapter 4 The Processor 9

Which of the following are part of the architecture state ?

1) PC 2) General purpose registers 3) FP registers 4) Pipelined registers 5) Branch Prediction Table

Answer: 1,2,3
Chapter 4 The Processor 10

Which of the following instructions are more likely to cause structure hazards?
1) Integer divide 2) Integer add 3) Shift 4) FP add 5) FP divide

Answer: 1,5
Chapter 4 The Processor 11