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# Digital System Design Using HDL

## High Level System Design

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Goals
To learn the high level system design

Design flow
Design methodology To model digital systems at various abstraction levels using HDL To learn synthesizable subset of VHDL and Verilog To learn tools that support VHDL and Verilog Simulation and Synthesis To introduce students to ASIC and FPGA design process
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## Combinational Vs Sequential Circuits

Digital circuits can generally be divided into combinational circuits and sequential circuits. Combinational (combinatorial) circuits are those whose outputs are functions of current inputs only. Sequential circuits are those whose outputs depends not only on current inputs, but also previous inputs. Combinational circuit: Outputs = F (current inputs) Sequential circuit: Outputs = F (current inputs, past inputs)
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Sequential Circuits

## Input Present State

Combinational Logic

Memory
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## Sequential Circuits cntd

Mathematical abstraction of sequential system is called FSM, an FSM is a system comprising states, inputs and outputs. It models time as discrete instants at which input or output can change. If the states and output transitions are constrained to occur at pre-defined times such as clock edges, the FSM is known as synchronous. If the states and outputs change in response to input changes, which can occur at any time, the FSM is known as asynchronous.5 IZ 4/29/2012

## FSM consists of three blocks.

Combinational Logic for the output. Combinational Logic for the next state. Memory block

## FSM are of two types.

Mealy FSM Moore FSM
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Mealy Machine
O/P Combinational Logic Next State Combinational Logic Memory
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Output

Input

Moore Machine
O/P Combinational Logic

Output

Input

## Next State Combinational Logic Memory

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Analysis of FSM

Analysis of FSM is to determine the job perform by the machine Literal analysis:
Symbolic Analysis

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Literal Analysis

Mealy Machine
Initialize the system Apply a set of inputs Propagate the set of inputs to the output and next state values Observe the outputs Apply the clock and update the present state values Return to second step Note:-inputs and outputs are valid immediately before the clock pulse

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Mealy Machine
S

Q C

D Clk

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Literal Analysis

Moore Machine
Initialize the system Apply a set of inputs Propagate the set of inputs to the output and next state values Apply the clock and update the present state values and propagate the new present state to the o/p. Observe the outputs Return to second step Note:-inputs are valid during the clock pulse and outputs are valid following the the clock pulse

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Moore Machine
Z

Q C

D Clk

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Symbolic Analysis
Generate switching algebra expression describing o/p and I/p to memory device (flip-flop). Generate next state equation for each flip-flop, using its switching algebra expression and characteristic equation. Generate next state K-Map for each FF, using its characteristic equation, and K-Map for each o/ps Generate a sate table Generate state diagram

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Mealy Machine

X QB Clk J A K Q

X Z

QA
X

QA_BAR QB_BAR

Q B

Clk
QB K

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