Moore’s Law

Gordon Moore: co-founder of Intel.  Predicted that number of transistors per chip would grow exponentially (double every 18 months).  Exponential improvement in technology is a natural trend: steam engines, dynamos, automobiles.

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

Moore’s Law plot

FPGA-Based System Design: Chapter 1

Copyright  2004 Prentice Hall PTR

The cost of fabrication
Current cost: $2-3 billion.  Typical fab line occupies about 1 city block, employs a few hundred people.  New fabrication processes require 6-8 month turnaround.  Most profitable period is first 18 months-2 years.

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR

design costs may swamp all manufacturing costs.Cost factors in ICs  For large-volume ICs: – packaging is largest cost.  For low-volume ICs. – testing is second-largest cost. – $10 million-$20 million. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR .

000 300. line width 1.000 700.000 500.000 100.Mask cost vs.18 micron .09 micron mask cost ($) FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR .000 400.13 micron .000 900.000 0 .000 200.000 600.25 micron .000 800.000.

LE LE LE Interconnect network LE LE LE Copyright  2004 Prentice Hall PTR FPGA-Based System Design: Chapter 1 . – Provide multi-level logic.Field-programmable gate arrays  FPGAs are programmable logic devices: – Logic elements + interconnect.

FPGAs and VLSI  FPGAs are standard parts: – Pre-manufactured. – Generally lower power consumption. – Don’t worry (much) about physical design. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR .  Custom silicon: – Tailored to your application.

FPGAs have no manufacturing delay. custom  Do you build your system with an FPGA or with custom silicon? – – – – FPGAs have shorter design cycle. FPGAs reduce inventory. FPGAs are slower.Standard parts vs. more power-hungry. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR . larger.

 Short design time: Late products are often irrelevant.  Multiple and conflicting constraints: low cost and high performance are often at odds.Challenges in system design Multiple levels of abstraction: logic to CPUs.  FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR .

circuit design. FPGA-based system design FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR .  Major levels of abstraction:  – – – – – specification.The system design process May be part of larger product design. logic design. architecture. layout.

Elements of an FPGA fabric Logic.  Interconnect.  I/O pins.  IOB LE LE LE IOB IOB … LE LE interconnect LE … LE LE LE FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR .

 CLB: combinational logic block = logic element (LE).  LUT: Lookup table = SRAM used for truth table.  FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR .Terminology Configuration: bits that determine logic function + interconnect.  I/O block (IOB): I/O pin + associated logic and electronics.

 May provide specialized logic. – Adder carry chain. – Typically 4 inputs.   Coarser-grained than logic gates. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR .Logic element  Programmable: – Input connections. Generally includes register. – Internal function.

Example logic element  Lookup table: a 0 b 0 1 0 out 0 0 1 0 1 0 0 1 a b 0010 0 out memory 1001 1 1 FPGA-Based System Design: Chapter 1 1 Copyright  2004 Prentice Hall PTR .

Logic synthesis How do we break the function into logic elements?  How do we implement an operation within a logic element?  FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR .

Placement  Where do we put each piece of logic in the array of logic elements? LE LE LE LE LE … LE LE LE LE Copyright  2004 Prentice Hall PTR FPGA-Based System Design: Chapter 1 .

– Many wires per channel. Connections between wires made at programmable interconnection points.  Must choose: – Channels from source to destination. – Wires within the channels. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR .Programmable wiring   Organized into channels.

Programmable interconnection point D Q FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR .

Programmable wiring paths FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR .

Choosing a path LE LE Copyright  2004 Prentice Hall PTR FPGA-Based System Design: Chapter 1 .

FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR .Routing problems    Global routing: – Which combination of channels? Local routing: – Which wire in each channel? Routing metrics: – Net length. – Delay.

Segmented wiring Length 1 Length 2 FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR .

Offset segments FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR .

– Slew rate.I/O Fundamental selection: input. – Voltage levels. output. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR . threestate?  Additional features:  – Register.

– Similar to SRAM but using flash memory. – Can be programmed many times.   Antifuse. Flash. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR . – Programmed once.Programming technologies  SRAM. – Must be programmed at power-up.

Configuration  Must set control bits for: – LE. – At power-up (SRAM). – Separate burn-in step (antifuse). FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR .  Usually configured off-line. – I/O blocks. – Interconnect.

memory CPU FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR . add r1. programming  FPGA configuration: – Bits stay at the device they program. – A configuration bit controls a switch or a logic bit.  CPU programming: – Instructions are fetched from a memory. r2 addIR r2 r1.Configuration vs. – Instructions select complex operations.

– A few clock cycles.Reconfiguration  Some FPGAs are designed for fast configuration. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR . not thousands of clock cycles.  Allows hardware to be changed on-the-fly.

FPGA fabric architecture questions  Given limited area budget: – How many logic elements? – How much interconnect? – How many I/O blocks? FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR .

What register features? Copyright  2004 Prentice Hall PTR FPGA-Based System Design: Chapter 1 . etc.Logic element questions How many inputs?  How many functions?  – All functions of n inputs or eliminate some combinations? – What inputs go to what pieces of the function?   Any specialized logic? – Adder.

Interconnect questions How many wires in each channel?  Uniform distribution of wiring?  How should wires be segmented?  How rich is interconnect between channels?  How long is the average wire?  How much buffering do we add to wires?  Copyright  2004 Prentice Hall PTR FPGA-Based System Design: Chapter 1 .

I/O block questions  How many pins? – Maximum number of pins determined by package type. Are pins programmed individually or in groups?  Can all pins perform all functions?  How many logic families do we support?  FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR .

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