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Perancangan Sistem Elektronika (dgn VHDL

TE – FTIK – UHT Djogi Lubis

About VHDL
• VHDL = VHSIC Hardware Description Language, VHSIC = Very High Speed Integrated Circuit • Describes the behavior of an electronic circuit and system, and attained (implemented) the physical circuit and system • IEEE 1076 Standard, and IEEE 1164 Standard • Circuit synthesis and simulation (not all construct are synthesizable) • Application:
– PLD (Programmable Logic Devices) : CPLD (Complex PLD), and FPGA (Field Programmable Gate Array) – ASICs (Application Specific Integrated Circuit)

• Statement are inherently concurrent (parallel), referred as a code rather than program • Only statements inside PROCESS, FUNCTION, or PROCEDURE are execute sequentially

Design Flow file with the extension .vhd and the same name as its ENTITY’s name .

. • There are several EDA (Electronic Design Automation) tools available for circuit synthesis. which describes the circuit at the Register Transfer Level (RTL). and simulation using VHDL. – Compilation is the conversion of the high-level VHDL language. • The second step is optimization. into a netlist at the gate level.• The first step in the synthesis process is compilation. the design can be simulated. which is performed on the gate-level netlist for speed or for area. implementation. – At this stage. • Finally. a place-and-route (fitter) software will generate the physical layout for a – PLD/FPGA chip or – will generate the masks for an ASIC.

Menterjemahkan Rangkaian ke Kode VHDL atau sebaliknya Full-adder diagram and truth table. .

Contoh VHDL code for the full-adder unit .

cin.b + a. which describes how the circuit should function. • there are several ways of implementing the equations described in the ARCHITECTURE . which is a description of the pins (PORTS) of the circuit. and of an • ARCHITECTURE. • sum bit is computed as s  a  b  c  cin • cout is obtained from cout = a.cin + b.• ENTITY.

then two possible results (among many others) for cout are illustrated in figures (b)~(c) (in both. if our target technology is an ASIC.cin).if our target is a programmable logic device (PLD or FPGA ).b + a. of course.cin + b. then a possible CMOS implementation. is that of figure (d) (which makes use of MOS transistors and clocked domino logic). cout = a. at the transistor level. .

the input pins (characterized by an inward arrow with an 1 marked inside) 2.Hasil simulasi dari desain VHDL 1. and the output pins (characterized by an outward arrow with an 0 marked inside) are those listed in the ENTITY .

work. Placing such pieces inside a library allows them to be reused or shared by other designs. – ARCHITECTURE: Contains the VHDL code proper. dan selanjutnya di compile kedalam library destinasi . or COMPONENTS. which describes how the circuit should behave (function). std. etc. ENTITY.Code Structure • comprise a piece of VHDL code: LIBRARY declarations. yang ditempatkan dalam PACKAGES. and ARCHITECTURE. PROCEDURES. – ENTITY: Specifies the I/O pins of the circuit. – A LIBRARY is a collection of commonly used pieces of code. • Fundamental VHDL units – LIBRARY declarations: Contains a list of all libraries to be used in the design. For example: ieee. – code biasanya ditulis dalam bentuk FUNCTIONS.

• LIBRARY library_name.package_name. . to make it visible to the design) two lines of code are needed. • USE library_name. and the other a use clause.Library Declarations • To declare a LIBRARY (that is. one containing the name of the library. as shown in the syntax below.package_parts.

from three different libraries.• At least three packages. standard (from the std library). are usually needed in a design: ieee. . and work (work library).std_logic_1164 (from the ieee library).

Fundamental sections of a basic VHDL code .

Fundamental parts of a LIBRARY. .

the end of a statement or • LIBRARY std. -. -.standard. -.all.declaration. -.dash (--) indicates a comment.std_logic_1164.all. while a double • USE std. • only the ieee library must be explicitly written • only necessary when the STD_LOGIC (or STD_ULOGIC) data type is employed in the design . • LIBRARY work. • USE work.all.• Their declarations are as follows: • LIBRARY ieee.) indicates • USE ieee.A semi-colon (.

which allow one type to be converted into another: conv_integer(p). • std_logic_unsigned: Contains functions that allow operations with STD_LOGIC_VECTOR data to be performed as if the data were of type UNSIGNED. • std_logic_signed: Contains functions that allow operations with STD_LOGIC_VECTOR data to be performed as if the data were of type SIGNED. b). It also contains several data conversion functions. . conv_unsigned(p. b). • std_logic_arith: Specifies the SIGNED and UNSIGNED data types and related arithmetic and comparison operations. b). conv_std_logic_vector(p. conv_signed(p.• the ieee library contains several packages • std_logic_1164: Specifies the STD_LOGIC (8 levels) and STD_ULOGIC (9 levels) multi-valued logic systems.

Its syntax . . • Signal modes.ENTITY • ENTITY is a list with specifications of all input and output pins (PORTS) of the circuit.

being two inputs (a and b. mode OUT). • • • • • • Arti dari ENTITY tersebut adalah: the circuit has three I/O pins. b : IN BIT.NAND gate. END nand_gate. ENTITY nand_gate IS PORT (a. x : OUT BIT). . The name chosen for the entity was nand_gate. All three signals are of type BIT. mode IN) and one output (x.

where signals and constants (among others) are declared. • Its syntax is the following: ARCHITECTURE architecture_name OF entity_name IS [declarations] BEGIN (code) END architecture_name. and – the code part (from BEGIN down).ARCHITECTURE • ARCHITECTURE is a description of how the circuit should behave (function). the name of an architecture can be basically any name (except VHDL reserved words). • Like in the case of an entity. including the same name as the entity’s. . • an architecture has two parts: – a declarative part (optional).

• x).• Contoh : architecture NAND gate ARCHITECTURE myarch OF nand_gate IS BEGIN x <= a NAND b. • In this example. there is no declarative part. . The name chosen for this architecture was myarch. and the code contains just a single assignment. END myarch. • Architecture mempunyai arti sbb: • the circuit must perform the NAND operation between the two input signals (a. b) and • assign (‘‘<=’’) the result to the output pin (x).

. regardless of clk. the output must be turned low.DFF with asynchronous reset. D-type flip-flop (DFF). q <=d) at the moment when clk changes from ‘0’ to ‘1’ (that is. when an upward event occurs on clk). Otherwise. triggered at the rising-edge of the clock signal (clk). When rst = ‘1’. and with an asynchronous reset input (rst). the output must copy the input (that is.

• There are several ways of implementing the DFF of figure 2. is that VHDL is inherently concurrent (contrary to regular computer programs. as shown below. .5. which are sequential). • This can be done using a PROCESS. one being the solution presented below. • One thing to remember. however. • So to implement any clocked circuit (flip-flops. for example) we have to ‘‘force’’ VHDL to be sequential.

--------------------------------------ARCHITECTURE behavior OF dff IS BEGIN PROCESS (rst. END PROCESS.all. USE ieee. 17. 14. 4. 8.1.std_logic_1164. 7. 5. 15. 6. 19. 18. clk) BEGIN IF (rst='1') THEN q <= '0'. rst: IN STD_LOGIC. 9. --------------------------------------ENTITY dff IS PORT ( d. 16. --------------------------------------- . END behavior. --------------------------------------LIBRARY ieee. clk. 2. q: OUT STD_LOGIC). END IF. 12. 13. 21. ELSIF (clk'EVENT AND clk='1') THEN q <= d. 11. END dff. 10. 3. 20.

Line 12: The PROCESS is executed every time a signal declared in its sensitivity list changes. Lines 11–19: Code part of the architecture (from word BEGIN on).• • • • • • • • • • • • Lines 2–3: Library declaration (library name and library use clause). All ports in an entity are signals by default. INOUT. and 21: Commented out (recall that ‘‘. plus clk has changed (an EVENT occurred on clk). . In this example. Lines 16–17: If rst is not active. Recall that the other two indispensable libraries (std and work) are made visible by default. ‘‘:=’’ would be used for a VARIABLE. Here. Lines 10–20: Architecture behavior.-’’ indicates a comment). Lines 14–15: Every time rst goes to ‘1’ the output is reset. Lines 1. 9. plus such event was a rising edge (clk = ‘1’). 4. then the input signal (d) is stored in the flip-flop (q <= d). Line 6: Input ports (input mode can only be IN). In this example. all input signals are of type STD_LOGIC. regardless of clk (asynchronous reset). In contrast. Lines 12–19: A PROCESS (inside it the code is executed sequentially). or BUFFER). Used only to better organize the design. the output is also of type STD_LOGIC. Line 7: Output port (output mode can be OUT. Lines 5–8: Entity dff. every time rst or clk changes the PROCESS is run. Lines 15 and 17: The ‘‘<=’’ operator is used to assign a value to a SIGNAL.

Simulation results: .

Latihan & Tugas 1. DFF + NAND Gate & Hasil simulasinya .

. but it should be ‘0’ or Z (high impedance) if sel = ‘‘00’’ or sel = ‘‘11’’. respectively.• the output should be equal to one of the inputs if sel = ‘‘01’’ (c = a) or sel ¼ ‘‘10’’ (c = b).

3. 26. USE _________________________ . END _________ . IF (sel = "00") THEN 16. --------------------------------------2. 19.1. _____ (sel = "10") THEN 20. LIBRARY ieee. PROCESS (a. c <= a. __ : ___ STD_LOGIC_VECTOR (7 DOWNTO 0). ENTITY mux IS 6. 17. 9. 25. ELSIF (__________) THEN 18. --------------------------------------5. c <= "00000000". BEGIN 15. 23. c <= __. 24. END _________ . 8. --------------------------------------- . END ___ . ____ ) 14. 4. END _____ . sel : IN ____________________________ . c <= (OTHERS => '__'). 10. --------------------------------------11. 7. ELSE 22. ARCHITECTURE example OF _____ IS 12. BEGIN 13. ___ : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)). b. PORT ( __ . 21.

Terima Kasih Any question ? .

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