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DEPARTMENT OF TECHNICAL EDUCATION

ANDHRA PRADESH
Name : A Rajeswara Rao
Designation : Head
Branch : Computer Engg
Institute : GMR Polytechnic, Karimnagar
Year/Semester : III Semester
Subject : Computer Architecture
Subject Code : CM-303
Topic : Information Representation,Arithmetic

operations
Duration : 100 Mts
Sub. Topic : Comparison of two fixed pointnumbers vide

sign and magnitude


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Teaching Aids to be use : Animation clips & images


Objective

On completion of this period, you would be able to


know

• The steps for multiplication of numbers in signed

magnitude representation.

• Explanation with the help of flow chart.

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RECAP

In the previous class, you have learnt about


• Fixed point addition/subtraction of two number

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Multiplication
• Multiplication of two fixed point binary numbers in
signed magnitude representation is done by a process
of successive and shift operations.
• Initially ,the multiplicand is in register B and the
multiplier in Q.
• The sum of A&B forms a partial product which is
transferred to the EA register.
• Both partial product and multiplier are shifted to the
right

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Example:
Consider multiplication Similarly for binary numbers
Of decimal nos. Qn
12 * 34 SC B= 1001 *1011
48 Initial partial
36 product 0000 1011
408 4 Qn=1 Add B 1001
1001 1011
Shift 0100 1101
3 Qn=1 Add B 1001
1101 1101
Shift 0110 1110
2 Qn=0
Shift 0011 0111
1 Qn=1 Add B 1001
1100 0111
Shift 0110 0011
0 stop
The final product of 1001B(9D) and 1011B(11D)
is 0110 0011B=63H=99D CM303.26to27 5
Multiplication
Contd..

In the above example we can observe the following


1. Initial partial product is set to 0000 1011 where 1011
is multiplier
2. Sequence counter is set to 4 (the no. of bits in

Multiplier)
3. 0000 is assumed to be present in Reg A and

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Multiplier(1011) in Reg. Q and
Multiplication
Contd..

4. Now the last bit Qn is checked


if Qn=1 B is added to Reg A (partial product inA.Q)
and then A.Q is right shifted
if Qn=0 A.Q is right shifted and SC is reduced by 1

5. The above
prep steps
ending arefirst
0 into repeated for four
bit position times (till SC
of A

falls to
When 0)SC is 0,
the
A.Q contains the final product
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Multiplication Contd..
The above computation may clearly be written as
Assume B=Multiplicand 1001
Q=Multiplier 1011
So SC=4(Noof bits in Mxr)
SC Action E A Q Qn
4 Initial partial
product 0 0000 1011 1
4 Qn=1 Add B 1001
0 1001 1011 1
Shift E.A.Q 0 0100 1101 1
3 Qn=1 Add B 1001
0 1101 1101 1
Shift E.A.Q 0 0110 1110 0
2 Qn=0
Shift E.A.Q 0 0011 0111 1
Qn=1 Add B 1001
0 1100 0111 1
Shift 0110 0011 1
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0 stop
Multiplication
Contd..
The sign of the product:
we can observe that
Sign of Sign of Sign of product
Multiplicand Multiplier
Bs Qs
+ + +
+ - -
- + -
- - +

In signed magnitude representation + is shown by 1


and - is shown by 0
Hence we can infer sign of product as Bs ⊕ Qs

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MULTIPLY OPERATION

MULTIPLICAND IN BR Q
MULTIPLIER IN QR n
EA A+B

As ⊕ Bs
Qs SHR EAQ
Qs
A

Qs
0
Bs SC SC-1

E 0
SC n-1
>0
SC

=0

END
(PRODUCT IN As.A.Q)
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Multiplication
Contd..

Multiplication can be performed by successive add


and shift operations
Also sign of result is exclusive or
result of the operand’s sign bits
Depending on these rules the flow chart
Above represents the multiply operation of two
fixed point numbers.

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Multiplication
Contd..

The assumptions for operand registers are


• Register AR is As.A where As stores
sign bit,
A stores n bit magnitude(A1 to An)
• Register BR is Bs.B where Bs stores
sign bit,
B stores n bit magnitude(B1 to Bn)
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Multiplication
Contd..

• Register QR is Qs.Q where Qs stores sign


bit and Q stores n bit magnitude(Q1 to Qn)

• Also BR stores multiplicand


And
QR stores multiplier before multiplication

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Summary
In this class , you have learnt …

1. How to derive signs of product from signs


of multiple and & multiplier.
2. How to multiply two binary numbers
3. The steps for multiplication of two
numbers in signed magnitude
representation

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Frequently asked questions

1. Draw flow chart for fixed point number


multiplication
2. With an example explain the fixed point
multiplication of two numbers

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Quiz

• During fixed point multiplication if Q n=1, the


following is to be preformed.
b) Register B is added to A
c) Register A is added to B
d) Register B is added to A and A.Q is right
shifted.
e) Register B is added to A and A.Q is left shifted.

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