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Pertemuan 7
Bahasa Rakitan: III
Matakuliah : T0324 / Arsitektur dan Organisasi Komputer
Tahun : 2005
Versi : 1

2
Learning Outcomes
Pada akhir pertemuan ini, diharapkan mahasiswa
akan mampu :
Mendemonstrasikan penggunaan bahasa
rakitan dalam instruksi mesin ( C3 ) ( No
TIK : 3 )
3
Chapter 2.

Assembly Language: III
(OFC1)
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Mo v e #A VEC,R1 R1 p oin ts to v ector A.
Mo v e #BVEC,R2 R2 p oin ts to v ector B.
Mo v e N,R3 R3 serv es as a coun ter.
Clear R0 R0 accum ulates the dot pro duct.
LOOP Mo v e (R1)+,R4 Compute the pro duct of
Multiply (R2)+,R4 next comp onen ts.
Add R4,R0 Add to previous sum.
Decremen t R3 Decremen t the coun ter.
Branc h
> 0
LOOP Loop again if not done.
Mo v e R0,DOTPR OD Store dot pro duct in memory .
Figure 2.33. A program for computing the dot product of two vectors.
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for (j = n 1; j > 0; j = j 1)
{ for ( k = j 1; k > = 0; k = k 1 )
{ if (LIST[ k ] > LIST[ j ])
{ TEMP = LIST[ k ];
LIST[ k ] = LIST[ j ];
LIST[ j ] = TEMP;
}
}
}
Mo v e #LIST,R0 Load LIST in to base register R0.
Mo v e N,R1 Initialize outer lo op index
Subtract #1,R1 register R1 to j = n 1.
OUTER Mo v e R1,R2 Initialize inner lo op index
Subtract #1,R1 register R2 to k = j 1.
Mo v eByte (R0,R1),R3 Load LIST( j ) in to R3, whic h holds
current maxim um in sublist.
INNER CompareByte R3,(R0,R2) If LIST( k ) [R3],
Branc h 0 NEXT do not exhange.
Mo v eByte (R0,R2),R4 Otherwise, exchange LIST( k )
Mo v eByte R3,(R0,R2) with LIST( j ) and load
Mo v eByte R4,(R0,R1) new maxim um in to R3.
Mo v eByte R4,R3 Register R4 serv es as TEMP .
NEXT Decremen t R2 Decremen t index registers R2 and
Branc h 0 INNER R1, whic h also serv e
Decremen t R1 as lo op coun ters, and branc h
Branc h > 0 OUTER bac k if lo ops not finished.
(b) Assembly language program for sorting
Figure 2.34. A byte-sorting program using a straight-selection sort.




s
s
>
(a) C-language program for sorting
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Record 1
(a) Linking structure
Record 2 Record k
Link address
Head T ail
0
Record 2
Record 1
Ne w record
(b) Inserting a new record between Record 1 and Record 2
Figure 2.35. Linked-list data structure.
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Record 1
(a) Linking structure
Record 2 Record k
Link address
Head T ail
0
Record 2
Record 1
Ne w record
(b) Inserting a new record between Record 1 and Record 2
Figure 2.35. Linked-list data structure.
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Figure 2.36. A list of student test scores organized as a linked list in memory.
First
28106 1200 1040
1 word 1 word 3 words
Head
(ID) (Test scores)
Memory
address
Key
field
Link
field
Data
field
record
27243 1040 2320
40632 1280 2720
28370 2880 1200
47871 0 1280
Second
record
Third
record
Second last
Last
record
record
Tail





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INSER TION Compare
Branch>0
Mo v e RNEWREC, RHEAD
Return
Compare (RHEAD), (RNEWREC)
Branch>0 SEARCH
Mo v e RHEAD, 4(RNEWREC)
Mo v e RNEWREC, RHEAD
Return
Mo v e RHEAD, RCURRENT
Mo v e 4(RCURRENT), RNEXT
Compare
Branch=0 T AIL
(RNEXT), (RNEWREC)
Branch<0
#0, RNEXT
Compare
HEAD
not empty
#0, RHEAD
HEAD
INSER T
Mo v e RNEXT , RCURRENT
Mo v e
Branch
RNEXT , 4(RNEWREC)
Mo v e RNEWREC, 4(RCURRENT)
Return
SEARCH
insert ne w record
some where after
current head
LOOP
insert ne w record in
an interior position
ne w record becomes ne w tail
INSER T
T AIL
LOOP
ne w record
becomes a
one-entry list
ne w record
becomes
ne w head
Figure 2.37. A subroutine for inserting a new record into a linked list.
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DELETION Compare (RHEAD), RIDNUM
Branch>0 SEARCH
Mo v e 4(RHEAD), RHEAD
Return
Mo v e RHEAD, RCURRENT
Mo v e 4(RCURRENT), RNEXT
Compare (RNEXT), RIDNUM
Branch=0 DELETE
Mo v e RNEXT , RCURRENT
Branch
Mo v e 4(RNEXT), R TEMP
R TEMP , 4(RCURRENT)
Return
LOOP
Mo v e
not the head record
SEARCH
LOOP
DELETE
Figure 2.38. A subroutine for deleting a record from a linked list.
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OP code
Figure 2.39. Encoding instructions into 32-bit words.
Source Dest Other info
8 7 7 10
(b) Two-word instruction
Memory address/Immediate operand
OP code
(c) Three-operand instruction
R i R j Other info R k
OP code Source Dest Other info
(a) One-word instruction
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T able 2.1
Generic addressing modes
Name Assem bler syn tax Addressing function
Immediate #V alue Op erand = V alue
Register R i EA = R i
Absolute (Direct) LOC EA = LOC
Indirect (R i ) EA = [R i ]
(LOC) EA = [LOC]
Index X(R i ) EA = [R i ] + X
Base with index (R i ,R j ) EA = [R i ] + [R j ]
Base with index X(R i ,R j ) EA = [R i ] + [R j ] + X
and offset
Relative X(PC) EA = [PC] + X
Autoincremen t (R i )+ EA = [R i ] ;
Incremen t R i
Autodecrement (R i ) Decremen t R i ;
EA = [R i ]
EA = effectiv e address
V alue = a signed n um b er

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Pertemuan 8
Bahasa Rakitan: IV
Matakuliah : T0324 / Arsitektur dan Organisasi Komputer
Tahun : 2005
Versi : 1

14
Learning Outcomes
Pada akhir pertemuan ini, diharapkan mahasiswa
akan mampu :
Mendemonstrasikan penggunaan bahasa
rakitan dalam instruksi mesin ( C3 ) ( No
TIK : 3 )
15
Chapter 2.

Assembly Language: IV
(OFC2)
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Fi gure D.1. IA-32 i nstructi on format.
Pref ix
1 to 4
OP code ModR/M SIB Displacement Immediate
by tes
1 or 2
by tes
1
by te
1 or 4
by tes
1
by te
1 or 4
by tes
Addressing mode
(a) General f ormat
7 6 5 4 0 3 2 1
Mod Reg/OPcode R/M
(b) ModR/M by te
7 6 5 4 0 3 2 1
Scale Index Base
(c) SIB by te
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# include < stdio.h >
v oid main(void)
{
long NUM1[5];
long SUM;
long N;
NUM1[0] = 17;
NUM1[1] = 3;
NUM1[2] = 51;
NUM1[3] = 242;
NUM1[4] = 113;
SUM = 0;
N = 5;
asm {
LEA EBX,NUM1
MO V ECX,N
MO V EAX,0
MO V EDI,0
ST AR T ADD: ADD EAX,[EBX + EDI*4]
INC EDI
DEC ECX
JG ST AR T ADD
MO V SUM,EAX
}
printf ("The sum of the list v alues is %ld \ n", SUM );
}
Figure D.2. IA-32 Program in Figure 3.40a encapsulated in a C/C++ program.

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Machine instructions Assembly language instructions
(hexadecimal)
03 04 BB STARTADD: ADD EAX,[EBX + EDI*4]
47 INC EDI
49 DEC ECX
7F F9 JG ST AR T ADD
(a) Loop body encoding
OP code ModR/M byte SIB byte
03 04 BB
00000011 00 000 100 10 111 011
ADD (see T able D.2) (see Figure D.1 c )
(doubleword
(b) ADD instruction
OP code Offset
7F F9
01111111 111111001
JG 7
(short offset)
(c) JG instruction
Figure D.3. Encoding of the loop body in Figure D.2.
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T ABLE D.1
Register field enco ding
in IA-32 instructions
Reg/Base/Index* Register
field
0 0 0 EAX
0 0 1 ECX
0 1 0 EDX
0 1 1 EBX
1 0 0 ESP
1 0 1 EBP
1 1 0 ESI
1 1 1 EDI
*ESP (100) cannot be used as an
index register.
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T ABLE D.2
IA-32 addressing modes selected by the ModR/M and SIB bytes
ModR/M b yte Addressing mode
Mod R/M
field field
b
7
b
6
b
2
b
1
b
0
0 0 Reg Register indirect
EA = [Reg]
0 1 Reg Base with 8-bit displacement
EA = [Reg] + Disp8
1 0 Reg Base with 32-bit displacement
EA = [Reg] + Disp32
1 1 Reg Register
EA = Reg
Exceptions
0 0 1 0 1 Direct
EA = Disp32
0 0 1 0 0 Base with index (uses SIB b yte)
EA = [Base] + [Index] Scale
When Base = EBP the addressing mo de is:
Index with 32-bit displacement
EA = [Index] Scale + Disp32
0 1 1 0 0 Base with index and 8-bit displacement (uses SIB b yte)
EA = [Base] + [Index] Scale + Disp8
1 0 1 0 0 Base with index and 32-bit displacemet (uses SIB b yte)
EA = [Base] + [Index] Scale + Disp32




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T ABLE D.3
Scale field encoding
in IA-32 SIB b yte
Scale field Scale
0 0 1
0 1 2
1 0 4
1 1 8
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T ABLE D.4
IA-32 instructions
Mnemonic Size Operands Operation CC flags
(Name) performed affected
dst src S Z O C
ADC B,D reg reg dst [dst] + [src] + [CF] x x x x
(Add with reg mem
carry) mem reg
reg imm
mem imm
ADD B,D reg reg dst [dst] + [src] x x x x
(Add) reg mem
mem reg
reg imm
mem imm
AND B,D reg reg dst [dst]
^
[src] x x 0 0
(Logical reg mem
AND) mem reg
reg imm
mem imm
BT D reg reg bit# = [src]; x
(Bit test) reg imm8 CF bit# of [dst]
mem reg
mem imm8
BTC D reg reg bit# = [src]; x
(Bit test and reg imm8 CF bit# of [dst];
complement mem reg complement bit#
mem imm8 of [dst]
BTR D reg reg bit# = [src]; x
(Bit test reg imm8 CF bit# of [dst];
and reset) mem reg clear bit# of [dst] to 0
mem imm8
Table D.4 page 1






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Table D.4 page 2
T ABLE D.4
( Continued )
Mnemonic Size Operands Operation CC flags
(Name) performed affected
dst src S Z O C
BTS D reg reg bit# = [src]; x
(Bit test reg imm8 CF bit# of [dst];
and set) mem reg set bit# of [dst] to 1
mem imm8
CALL D reg ESP [ESP] 4;
(Subroutine mem [ESP] [EIP];
call) EIP EA of dst
CLC CF 0 0
(Clear carry)
CLI IF 0
(Clear int. flag)
CMC CF [CF] x
(Compl. carry)
CMP B,D reg reg [dst] [src] x x x x
(Compare) reg mem
mem reg
reg imm
mem imm
DEC B,D reg dst [dst] 1 x x x
(Decrement) mem
DIV B,D reg for B: ? ? ? ?
(Unsigned mem [AL]/[src];
divide) AL quotient;
AH remainder
for D:
[EAX]/[src];
EAX quotient;
ED X remainder















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T ABLE D.4
( Continued )
Mnemonic Size Operands Operation CC flags
(Name) performed affected
dst src S Z O C
HL T Halts execution un til
(Halt) reset or external
in terrupt o ccurs
IDIV B,D reg for B: ? ? ? ?
(Signed mem [AL]/[src];
divide) AL quotient;
AH remainder
for D:
[EAX]/[src];
EAX quotient;
ED X remainder
IMUL B,D reg (double-length product) ? ? x x
(Signed mem for B:
m ultiplication) AX [AL] [src]
for D:
ED X,EAX [EAX]
[src]
D reg reg (single-length pro duct) ? ? x x
reg mem reg [reg] [src]
IN B,D dst = AL AL or EAX [src]
(Isolated or EAX
input) src = imm8
or [D X]
INC B,D reg dst [dst] + 1 x x x
(Increment ) mem
INT D imm8 Push EFLA GS;
(Software Push EIP;
in terrupt) EIP address
(determined b y imm8)
Table D.4 page 3











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T ABLE D.4
( Continued)
Mnemonic Size Operands Operation CC flags
(Name) performed affected
dst src S Z O C
IRET D P op EIP; x x x x
(Return from P op EFLA GS
in terrupt)
LEA D reg mem reg EA of src
(Load effectiv e
address)
LOOP D target ECX [ECX] 1;
(Lo op) If ( [ECX] = 0 )
EIP target
LOOPE D target ECX [ECX] 1;
(Lo op on If ( [ECX] 0
equal/zero)
^
[Z] = 1 )
EIP target
LOOPNE D target ECX [ECX] 1;
(Lo op on If ( [ECX] 0
not equal/
^
[Z] 1 )
not zero) EIP target
MO V B,D reg reg dst [src]
(Mo v e) reg mem
mem reg
reg imm
mem imm
MO VSX B reg reg reg sign extend [src]
(Sign extend reg mem
b yte in to
register)
Table D.4 page 4












=
=
=
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T ABLE D.4
( Continued)
Mnemonic Size Operands Operation CC flags
(Name) performed affected
dst src S Z O C
MO VZX B reg reg reg zero extend [src]
(Zero extend reg mem
b yte in to
register)
MUL B,D reg (double-length pro duct) ? ? x x
(Unsigned mem for B:
m ultiplication) AX [AL] [src]
for D:
ED X,EAX [EAX]
[src]
NEG B,D reg dst 2's-complement x x x x
(Negate) mem [dst]
NOP alias for:
(No op eration) X CHG EAX,EAX
NOT B,D reg dst [dst ]
(Logical mem
complement)
OR B,D reg reg dst [dst] v [src] x x 0 0
(Logical OR) reg mem
mem reg
reg imm
mem imm
OUT B,D dst = imm8 dst [AL] or [EAX]
(Isolated or [D X]
output) src = AL
or EAX
Table D.4 page 5









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T ABLE D.4
( Continued)
Mnemonic Size Operands Operation CC flags
(Name) performed affected
dst src S Z O C
POP D reg dst [[ESP]];
(Pop off mem ESP [ESP] + 4
stack)
POPAD D Pop eight doublewords
(Pop off off stack in to
stack in to EDI, ESI, EBP , discard,
all registers EBX, EDX, ECX, EAX;
except ESP) ESP [ESP] + 32
PUSH D reg ESP [ESP] 4;
(Push on to mem [ESP] [src]
stac k) imm
PUSHAD D Push contents of
(Push all EAX, ECX, EDX, EBX,
registers ESP , EBP , ESI, EDI
on to stack) on to stack;
ESP [ESP] 32
R CL B,D reg imm8 See Figure 2.32 b ; ? x
(Rotate left reg CL src operand is
with C flag) mem imm8 rotation count
mem CL
R CR B,D reg imm8 See Figure 2.32 d ; ? x
(Rotate righ t reg CL src operand is
with C flag) mem imm8 rotation count
mem CL
RET EIP [[ESP]];
(Return from ESP [ESP] + 4
subroutine)
Table D.4 page 6










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T ABLE D.4
(Continued)
Mnemonic Size Operands Operation CC flags
(Name) performed affected
dst src S Z O C
R OL B,D reg imm8 See Figure 2.32 a ; ? x
(Rotate left) reg CL src operand is
mem imm8 rotation count
mem CL
R OR B,D reg imm8 See Figure 2.32 c ; ? x
(Rotate righ t) reg CL src operand is
mem imm8 rotation count
mem CL
SAL B,D reg imm8 See Figure 2.30 a ; x x ? x
(Shift reg CL src operand is
arithmetic mem imm8 shift count
left) mem CL
same as SHL
SAR B,D reg imm8 See Figure 2.30 c ; x x ? x
(Shift reg CL src operand is
arithmetic mem imm8 shift count
right) mem CL
SBB B,D reg reg dst [dst] [src] x x x x
(Subtract reg mem [CF]
with b orrow) mem reg
reg imm
mem imm
SHL B,D reg imm8 See Figure 2.30 a ; x x ? x
(Shift reg CL src operand is
left) mem imm8 shift count
same as SAL mem CL
Table D.4 page 7


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T ABLE D.4
(Continued)
Mnemonic Size Operands Operation CC flags
(Name) performed affected
dst src S Z O C
SHR B,D reg imm8 See Figure 2.30 b ; x x ? x
(Shift reg CL src operand is
righ t) mem imm8 shift coun t
mem CL
STC CF 1 1
(Set carry
flag)
STI IF 1
(Set in terrupt
flag)
SUB B,D reg reg dst [dst] [src] x x x x
(Subtract) reg mem
mem reg
reg imm
mem imm
TEST B,D reg reg [dst]
^
[src]; x x 0 0
(T est) mem reg set flags based
reg imm on result
mem imm
X CHG B,D reg reg [reg] [src]
(Exchange) reg mem
X OR B,D reg reg dst [dst] [src] x x 0 0
(Exclusive reg mem
OR) mem reg
reg imm
mem imm
Table D.4 page 8





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T ABLE D.5
IA-32 conditional jump instructions
Mnemonic Condition Condition code
name test
JS Sign (negative) SF = 1
JNS No sign (positive

or zero) SF = 0
JE/JZ Equal/Zero ZF = 1
JNE/JNZ Not equal/Not zero ZF = 0
JO Overflow OF = 1
JNO No overflow OF = 0
JC/JB Carry/Unsigned below CF = 1
JNC/JAE No carry/Unsigned above or equal CF = 0
JA Unsigned above CF ZF = 0
JBE Unsigned below or equal CF ZF = 1
JGE Signed greater than or equal SF OF = 0
JL Signed less than SF OF = 1
JG Signed greater than ZF (SF OF) = 0
JLE Signed less than or equal ZF (SF OF) = 1
v

v
v
v