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Basic Crystal Structures

Atomic Order
Crystal Structure Amorphous Structure

Miller Indices of Crystal Planes


Y X (100) X




Silicon Crystal Structure

Silicon has the basic diamond crystal structure two merged FCC cells offset by a/4 in x, y and z.

Basic FCC Cell

Merged FCC Cells

Omitting atoms outside Cell

Bonding of Atoms

Various types of defects can exist in a crystal (or can be created by processing steps). In general, these cause electrical leakage and results in poorer device qualities.
(Extra plane of atoms)

Point Defects

Vacancy defect

Interstitial defect

Frenkel defect

Line Defect

1 dimensional Edge dislocation missing row of atoms (or extra halfplane of atoms) Caused by thermal stresses within crystal or due to excess interstitials Damages electrical properties need to be avoided during thermal processing

Extra half plane

Area defect: 2 Dimensional.

Stacking faults.

Volume Defect: 3 Dimensional.



Czochralski growth

Technique for producing crystals from which semiconductor wafers are cut. Developed by Czochralski in 1918. Main process: solidification of a crystal from a melt. Material used: Electronic Grade Polycrystalline Silicon.

Electronic Grade Silicon

Step1: Metallurgical grade Si from SiO2 (quartzite) Quartzite is heated with coke, charcoal, etc in an electric arc furnace to give 98% pure Si

6 to 8hr process (2350C)

SiO2 (s) + 2C (s) = Si (l) + 2CO

Step 2: Si is treated with anhydrous HCl at 300C to form trichloro Silane (SiHCl3) Si + 3HCl = SiHCl3 + H2 Step 3: Fractional distillation of SiHCl3 to remove unwanted impurities SiHCl3 is a liquid at room temperature with a boiling point of 32C

Step 4: Reduction of SiHCl3 in Hydrogen to form Electronic Grade Si (EGS) SiHCl3 + H2 = Si + 3HCl
Impurity in ppb range. Polycrystalline Si obtained. 99.999999% pure.

Czochralski Growth

Heat EGS around 15000C. Insert single crystal seed. Rotate and pull the seed. Pull rate initially fast. Then slowed down. Atom layer with same orientation as that of seed is developed. Diameter vary with speed of pulling.

Pure Si ingots

Solidification: by reduction in temperature Increased pull rate: material cannot solidify as heat will not be conducted away. Material near melt has higher density of point defects. Hence cool quickly to prevent agglomeration of defects. Point defects agglomerate and form most commonly dislocation loops.

During the process

Considerable O2 is released from silica. 95% escape from surface as SiO. Reduction of O2 concentration: grow boule under magnetic confinement. Field directed along the length of boule. Creates Lorentz force (qvB) which will change the motion of ionized impurities in the melt in such a manner so as to keep them away from liquid-solid interface.

Dopant addition

Dopant may be introduced in the melt. Wafer with desired resistivity. Boron and Phosphorous commonly for Si Complicated since impurities tend to segregate at solid-liquid interface. Segregation co-efficient, k = CS/CL CS,CL impurity concentration at solid & liquid sides

Impurity concentration in the solid (Cs) at any point can be obtained as a function of initial liquid concentration Co, distribution coefficient k as: where X is the fraction of liquid solidified. This assumes well-mixed liquid. However, in reality, the liquid is not well mixed due to existence of re-circulation cells.

The ends of the boule are richer in impurities because of segregation effects. When the final amount of liquid solidifies, all the remaining impurities are trapped.

Float-Zone Process/Zone refining

Makes use of the segregation effect intentionally. Basic principle: A molten metal when gradually cooled, crystallizes into ultra pure metal. The impurities continue to be in the molten state and flow away from the crystallized metal.

Zone refining consists of repeated passes through the solid by a liquid zone. When the final amount of liquid solidifies, all the remaining impurities are trapped. After each pass the impurity levels in the front end of the rod keeps reducing while that of the final solidifying part keeps increasing.

Seed crystal is injected into the top of the molten rod. RF coil passed along the length. Molten silicon retained by surface tension and supported by the solid part. Since no crucible is used, contamination from crucible is avoided.

Gas inlet (inert) Chuck Polysilicon rod RF Molten zone Travel ing RF coil

Seed crystal Inert gas out


Thin neck: ~3 mm diameter and 10-20 mm long is pulled. Pull rate and temperature lowered to shoulder the crystal to larger diameter. Can be used for boules with less weight (molten region should support the weight of entire rod).

Disadvantage: difficult to introduce uniform concentration of dopants.

Challenges associated with growth of GaAs:

Vapor pressure of Ga is 0.001atm while that of As is ~ 10atm at melting point (1238C). Arsenic evaporates and maintaining stoichiometry will be difficult. The thermal conductivity of GaAs (0.07W/cm-K) is 1/3rd of that of silicon (0.21W/cm-K) Heat dissipation is more difficult Critical resolved shear stress for creating dislocation is very small (1/4th of silicon) at mp Very easy to create dislocations in GaAs

GaAs is typically grown by LEC or Bridgman methods Bridgman technique : widely used LEC for larger diameter ingots.

Liquid encapsulated Czochralski

A sealant material such as B2O3 is used on top of GaAs to prevent out diffusion of Arsenic. B2O3 melts at ~400C and seals GaAs. Seed crystal is inserted through sealant on to GaAs. Crystal growth occurs usually at ~20atm (high pressure LEC). Graphite crucible used. Segregation coefficient similar to that of Si.

Liquid encapsulated Czochralski

Sealant should have following properties:

Less Ox contamination; but B gets incorporated As B2O3 increases heat transfer, increased chances for defects

Impervious to As diffusion Chemical resistance to GaAs Optically transparent Lower density than molten GaAs (1.5gm/cc to 5.7gm/cc for GaAs) B2O3, CaCl2, BaCl2

Annealing or alloying with Indium reduces defects

Bridgman technique

Solid Ga and As are fused into a graphite ampoule, which is later sealed. Separate As chamber sometimes included in quartz tube with small orifice to maintain stoichiometry Tube furnace is made to pass through trough containing ampoule (ampoule kept stationary to minimize disturbance). Smaller temperature gradients result in lower dislocation densities

Wafer Finishing

Boule characterized for resistivity and crystal perfection Mechanically trimmed into proper diameter Flats are introduced over the entire length of the boule Etching in HF-HNO3 to remove damage from grinding

Wafer finishing

Wafer slicing: critical step determines flatness Lapping (using Al2O3 + glycerin slurry) grind both sides, flatness ~2-3 mm Edge profiling Chemical etching to remove surface damaged layer Polishing chemical-mechanical polish, SiO2/NaOH slurry cleaning and inspection