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Packaging and circuit boards
• Single IC can not form complete digital system • It need packaging for inter IC communications for input/ output displays and other devices • IC is bonded into single package which serve several purposes. It protects the IC from moisture and airborne contaminants, provides electrical connections and removes heat • Several IC packages with different physical, electrical and thermal properties are available • The choice of package depends on the number of connections required and the environment in which the product is to operate, among other factors.
• This consists of layers of fiberglass or other insulating material separating layers of metal wiring. similar to that used· in manufacturing ICs. called vias. and then etched using a photolithographic process.Printed circuit board • The packaged ICs and other components in a system are assembled together on a printed circuit board (PCB). . Small holes are drilled through the layers and coated with metal to form connections. • The completed PCB contains all the circuit wiring needed for the product. • Several layers are sandwiched together. between the layers. • The metal is deposited in a layer on a fiberglass sheet.
Types of PCB • Through hole PCB: • Surface mount PCB .
Dual in-line packages (DIPs) have two rows of pins with 0.1 inch spacing • Pin grid array (PGA) – 400 and above – minimum spacing • Advantage . • Disadvantage -.they can be manually assembled.Fails if pin count increases . • DIP – up to 48 pin configuration 0.Through hole PCB • Includes additional metal-coated holes into which IC package pins are inserted. • Use insertion-type packages. since the component sizes are manageable.1-inch spacing. .
The ball grid array (BGA) package.Surface-mount PCB • • • Components are mounted on the surface rather than being inserted in holes. forming the connection. < 100 pins 0.4mm increased pin count. Connections can be made between adjacent chips by metal contacts. This has the advantage of reduced manufacturing cost (for higher-volume products).65mm for the higher pin-count packages. –200 pin s 0. up to nearly 400 pins. multichip modules (MCMs) attach the base chips to a ceramic substrate chip stacking involves -.1800 pins . • • • • . finer feature sizes and increased circuit density. The spacing between pins varies from 1 mm for the packages with fewer pins. Solder paste is applied between each pin and pad and subsequently melted. Different surface mounting packages. Quad flat-pack (QFP) -. and between chips and the containing package by bond wires.placing two or more chips in a vertical stack. Surface mounting IC packages have pins or connection points that come into contact with a metal pad on the PCB.pins along all four sides. ICs with up to 200 pins. – high pin count -.
Explain different PCB mount technologies for ICS .1. How does flip-chip IC packaging differ from previous packaging technologies? 2.
into the receiver. – an abstraction. • Along path several influences can cause signal to distort by noise .through the pin.through the bond wire-. lead frame and bond wire of the destination IC.Interconnections and Signal Integrity • Signals changes between low and high logic levels instantaneously. • Consider signal propagation between a source and a destination within a circuit and different IC. • In reality signals take time to change and time to propagate along signal wires varies. – problems path may be from the source driver-.package lead and from pin of the source IC along the PCB trace. -.-.
Since this is a complex area. i. • Signal integrity is important in implementing a design in an ASIC. We must assume that the designers of the IC and package have done due diligence to maintain signal integrity.e 150mm per nanosecond as a good rule of thumb for signal propagation along a PCB trace. • In common PCB materials. This causes a change in the electric and magnetic fields around the trace. we do not have cntrol over the path within the IC package.Signal integrity : “It is the degree to which effects along the path are minimized. • A change in a signal value causes a change in the current flowing through the PCB trace. • Propagation of those fields determines the speed of propagation of the signal change along the trace. . For low speed designs and small PCBs.” • If we are using off-the-shelf lCs or PLDs. the maximum propagation speed is approximately half the speed of light in a vacuum. this element of total path delay is insignificant.
If a clock signal is routed through paths of different lengths to different ICs. it may be necessary to tune the timing of the system by adding to the length of some PCB traces to match propagation delays.• However. particularly for signals on critical timing paths. and may be incorrectly sampled at the destination's receiver. it is significant. changes in elements of the bus may not arrive concurrently.. Parallel bus signals -. • Two cases 1.if different signals within a parallel bus are routed along paths of different lengths. . for high-speed designs. • In these cases. we may introduce clock skew 2. The routing of clock signals -.
Noise . Ground bounce 2. High slew rate signals -.Signal integrity issues in PCB 1.
the power supply can source the transient current without distortion. It can also cause transient shifting of the threshold voltage of receivers on the IC causing false transitions at those receivers. possibly causing false transitions in the receivers to which they are connected.SI issue – Ground bounce It arises when one or more output drivers switch logic levels. there is inductance in both the power and the ground connections. Ideally. however. and transient current flows from the power supply to ground. as shown in fig The inductance causes voltage spikes in the power supply and ground on the IC. . This can cause voltage spikes on other output drivers. The effect is particularly pronounced when multiple drivers switch concurrently. In reality. During switching. both of the transistors in the driver's output stage are momentarily on.
First.01pF to 0.Reduction in Ground Bounce . we can use separate PCB layers for the ground and power supply. we can place bypass capacitors between power and ground at strategic places around a PCB.] Second. This gives a low-inductance path for the power supply current and its ground return . These capacitors hold a reserve of charge that can quickly supply the needs of switching drivers[ Values of 0.1pF are common.
These actions limit the rate of change of current. This is a case where a trade-off between speed of operation and noise immunity may be required. consequently requiring a reduction in clack rate. . we can !imit the rate of voltage change (the slew rate) and limit the drive current of the output drivers. limiting slew rate may increase propagation delay through circuits. and so limit the inductive effect of the change. Of course. as illustrated in Figure Hence. reducing the slew rate means that a signal takes longer to change from one logic level to the other.Third.
as well as the source impedance of the driver and the terminating indepedance of the receiver. Depending on the relationships between these values. the transition is affected by reflections at the driving and receiving ends of the path . A full analysis of the effects requires knowledge of the characteristic impedance of the path. overshoot. the signal may suffer from partial transitions. When the time for a transition between logic levels is similar to or shorter than the propagation delay along a signal path. undershoot and ringing shown in Figure .Slew rate Another signal integrity issue for high-slew rate signals is noise due to transmission-line effects.
. we can run a trace over just one plane. we can adopt circuit designs and layouts that avoid placing receivers along the PCB trace.• The main design techniques for managing transmission-line effects involve appropriate layout and proper termination of PCB traces. we can include termination resistors to ensure proper matching of drivers and receivers to the characteristic impedance of the transmission line. • For critical signals. creating a microstrip transmission line.. • By running a trace of specific dimensions at a controlled distance between two ground or power planes in the PCB. we create a strip/line transmission line with a controlled characteristic impedance • Where the transmission line effects are less critical. we may need to include resistors as discrete components adjacent to IC pins. including FPGAs. the drivers include termination resistors on the IC. In other cases. • Finally. . • In high performance modern components. or that group them together at the receiving end .
we sense the voltage difference between the two signals. is based on the idea of reducing a system's susceptibility to interference. if S_P . Such common-mode noise is cancelled out when we sense the voltage difference. Rather than transmitting a bit of information as a single signal S.Differential Signalling • The techniques for maintaining signal integrity that we have discussed so far are based on reducing the amount of interference induced on signal wires.S_N is a positive voltage. • Another technique.S_N is a negative voltage. • The assumption behind the differential signalling approach is that noise is induced equally on the wires for both S_P and S_N. • At the receiving end. we transmit both the positive signal S_P and its negation S_N. use of differential Signalling. If S_P . then S is received as O. then S is received as the value 1. At the receiver. we sense the voltage . suppose a noise voltage VN is induced equally on the two wires. To show this.
Differential Signalling Signal on B is inverse of A Difference between VA and VB is 2X the amplitude Improved noise rejection. distance and reliability (A+Vn)-(-B+Vn) = A+B . speed.
Differential Cancels Noise Noise and external interference has equal impact on each wire in the pair A-B differential cancels out noise Common-mode offset (ground shift) is also cancelled out .
Comparison of PROFIBUS and RS-485 .
21 .All signals are balanced.36 – Modems spec.Serial Communication Standards ITU-T • V.10 – Single Ended electrical circuits for data communication at up to 100 kbps • V. • V.28 .11 for the differential signals. for synchronous data transmission using 60-108 kHz group band circuits • X. while the control signals remain single ended.21 signals are thesame as RS-422 • EIA-530 defines pin out on a 25 pin connector • RS-449 defines the pin out on a 37 pins connector .Differential electrical circuits for data communication at up to10 Mbps • V.specifications from V. Electrically the X.electrical characteristics for single ended double-current interchange circuits • V.35 ..11 .
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