Sequential Circuit Synthesis - II

Virendra Singh Indian Institute of Science Bangalore
IEP on Digital System Synthesis, IIT Kanpur

Incompletely Specified Machine
 The specified behaviour of a machine with partially specified transitions can be described by another machine whose state transitions are completely specified The transformation is accomplished by replacing all the dashes in the next state entries by T and adding a terminal state T whose output are unspecified
PS X=0 A B C B, 1 --, 0 A, 1 NS, z X=1 --, -C, 0 B, 0
Sequential@iitk

PS X=0

NS, z X=1

A
B C T

B, 1
T, 0 A, 1 T, --

T, -C, 0 B, 0 T, -2

Dec 14,2007

2007 Sequential@iitk 3 .t. respectively.Compatible States   State Si of M1 is said to cover. for every state Sj in M2. there is a corresponding state Si in M1 s. or contain. results in identical output sequences whenever the outputs of M2 are specified Machine M1 is said to cover machine M2 if and only if. and its application to both M1 and M2 when they are initially in Si and Sj. state Sj of M2 if and only if every input sequence applicable to Sj is also applicable to Si. Si covers Sj Dec 14.

Compatible States    Two states Si and Sj of machine M are compatible. the same output sequence will be produced whenever both outputs are specified and regardless of whether Si or Sj is the initial state Si and Sj are compatible. are the same or also compatible. ….. Sj. identical when specified) and their Ii-successor. A set of states (Si.2007 Sequential@iitk 4 . if and only if.) is called compatible if all its members are compatible Dec 14. for every Ii for which both are specified. if and only if.e. for every input sequence applicable to to both Si and Sj. their outputs are not conflicting (i. Sk.

Compatible States   A compatible Ci is said to be larger than. every state in Cj is also contained in Ci A compatible is maximal if it is not covered by any other compatible Dec 14.2007 Sequential@iitk 5 . if and only if. another compatible Cj. or to cover.

β D. 0 NS. z X=1 α. z X = 0 X= 1 C. 1 E. 0 X= 0 β. 1 A C NS. 1 A. 1 C. 0 E. 0 Dec 14. 1 D E PS AE . 0 α.Compatible States PS PS A B C D NS.α BCD . -E.2007 Sequential@iitk . 1 β. 1 B. 1 A. 1 A. 0 E. 0 D. -B. 1 A. 1 6 E D. z X = 0 X=1 C. 1 E. 0 D.

0 B. 0 B’. 0 B. 1 B’’ C B+. 0 X=1 C. 0 B’. 1 A. z X=0 A.Compatible States  A set of states is compatible if and only if every pair of the states in that set is compatible PS A B NS.2007 Sequential@iitk 7 . -- C B. z X=0 A. 0 B’’. 0 A. 0 X=1 C. 1 Dec 14. -- PS A B’ NS. 0 B+.

1 X=1 β. 0 Dec 14.β B+ = B” B+ = B’ X= 0 (AB’) – α (B”C) – β α. 0 α. 0 α. 0 α. z X= 0 (AB’) – α (B’’C) . 1 α.2007 Sequential@iitk 8 . 0 β. 0 X=1 β. z PS NS.Compatible States PS NS.

0 Dec 14. 1 A. 0 B. 0 B.2007 C. 0 ----C. which will form the basis of state reduction leading to minimum machine A B C D E F --E. 0 --- E. 1 ------D. 0 F. 1 C.Merger Graph PS I1 I2 NS. z I3 I4 •Transforming into fully specified machine may not be optimal one • First generate the entire set of compatibles •Select an appropriate subset. 1 --F. 1 ----B. 1 --F. 1 Sequential@iitk 9 .

then (Sp Sq) said to be implied by (SiSj) • (SpSq) are referred as implied pair Dec 14. respectively.2007 Sequential@iitk 10 .Merger Graph • A set of states is compatible if and only if every pair of states in that set is compatible • It is sufficient to consider pair of states and use them to generate entire set • Compatible pair of states is referred as compatible pairs • Let the Ik-successors of Si and Sj be Sp and Sq.

If for a pair of states (Si Sj) the corresponding outputs under all inputs are not conflicting. and then implied pairs are entered in the space Dec 14. For each pair of states (Si Sj) in M whose next state and output entries are not conflicting. an interrupted arc is drawn between Si and Sj. an undirected arc is drawn between vertices Si and Sj 3.Merger Graph Merger graph is undirected graph 1. each of which corresponds to a state of M 2. but successors are not the same.2007 Sequential@iitk 11 . It consists of n-vertices.

z I2 C.Merger Graph PS I1 A B --E. 1 A. 1 --F. 1 --F (AB) (CD) (BE) (CF) (CF) A B (EF) C C D E F F. 1 E D Dec 14. 0 ----C. 0 F. 0 NS. 0 ----C. 1 --I4 B.2007 Sequential@iitk 12 . 1 --I3 E. 0 --- --B. 0 D. 1 B.

(BC). (AC). (AD). (BC). (AC).2007 Sequential@iitk 13 . (CF). (CD). (BE). (BE). (BC) are compatible => (ABC) compatible Find minimal set of compatible {(ABCD). (EF) (AB). (DE)} Dec 14. (BD).Merger Graph Merger graph is undirected graph Nine compatible pairs (AB).

0 δ. 0 I3 δ. for every compatible contained in the set. 1 δ. 0 I4 α. 1 δ. 0 Sequential@iitk . 0 14 δ.  A closed set of compatibles which contains all the sates of M is called closed covering  A set {(AD). (BE). 0 β.Merger Graph  A set of compatible (for machine M) is said to be closed if.β (EF) . all its implied also contained in the set. 1 --Β. z I1 (AB) .2007 I2 β.α (CD) . 1 α. (CD)} is a closed covering PS NS.δ Dec 14. 1 α.

Compatible Graph  The compatible graph is a directed graph whose vertices corresponding to all compatible pairs.2007 Sequential@iitk 15 . and arc leads from vertex (Si Sj) to vertex (Sp Sq) if and only if (Si Sj) implies (Sp Sq)  It is a tool which aids in the search for a minimal closed covering  Compatible pairs are obtained from merger graph Dec 14.

1 B. 0 D (AB) (DE) C Merger Graph Dec 14. 1 --- --- A. 0 D. -- C.B. 0 --- E. 1 B.Compatibility Graph PS I1 A B --C. 0 --B. z I2 --A. 0 I4 ----E (AE) (BC) (BC) (AD) A (CF) (BE) (BC) B C D E C. 0 NS. 1 I3 E.2007 Sequential@iitk 16 . -.

2007 Sequential@iitk BE (AD) BC CD 17 .Compatibility Graph A (CF) (BE) E (AE) (BC) B AD AC (BC) (BC) D (AB) (DE) C DE Merger Graph Dec 14.

2007 Sequential@iitk 18 .e. i.Minimization using Network Model  Behaviour of sequential circuit can be described by traces.. sequence of inputs and outputs  Various approaches to optimize  Ignore registers and optimize the combinational logic  Retiming – move position of registers only Dec 14.

2007 Sequential@iitk 19 . so that the critical paths they embrace are as short as possible  Moving registers may increase or decrease the number of regsisters Dec 14.Retiming  Minimize cycle time or the area of synchronous circuits by changing the position of the registers  Cycle time is bounded from below by the critical path delay in the combinational circuit  Retiming aims at placing the registers in the appropriate position.

2007 Sequential@iitk 20 .Retiming + Host δ δ δ + + Dec 14.

Dec 14.2007 Sequential@iitk 21 .

Dec 14.2007 Sequential@iitk 22 .

Example Machine M2 PS A E. 0 P0 = (ABCDEFG) P1 = (ABCDFG) (E) P2 = (AF) (BCDG) (E) P3 = (AF) (BD) (CG) (E) P4 = (A) (F) (BD) (CG) (E) P5 = (A) (F) (BD) (CG) (E) B C D E F G C. 0 B. 0 Dec 14. 0 G. 0 D. 0 G. 0 A. 1 E. 0 NS. z X=0 X=1 C. 0 B. 0 F.2007 Sequential@iitk 23 . 0 A. 0 D. 0 G.

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