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Nima Afraz
Advisor : Dr. M Ersali
QIAU 2011

A Energy Efficient Scheduling Base on Dynamic Voltage and Frequency Scaling for Multi-core Embedded Real-Time System
Xin Huang, KenLi Li, and RenFa Li School of Computer and Communication, Hunan University, Changsha, 410082 Hunan province, P.R. China


has emerged as the #1 limiter of design performance beyond the 65nm generation.


Voltage and Frequency Scaling is a technique in computer architecture whereby the frequency of a microprocessor can be automatically adjusted "on the fly," either to conserve power or to reduce the amount of heat generated by the chip. Dynamic frequency scaling is commonly used in laptops and other mobile devices, where energy comes from a battery and thus is limited.

Goal : reducing power consumption

for multi-core embedded real-time system. Limitations : all cores must run at the same performance level and implemented Dynamic voltage and frequency scaling (DVS).


mobile real-time systems grow more common, the demand for high-performance processors will also grow. seems likely that in the future, the throughput of processors will be improved mainly by increasing the number of integrated cores.


What is proposed in this paper ?

a novel scheduling algorithm use Earliest

Deadline First (EDF) to guarantee meeting the deadlines of all real time task sets for each core and to make DVS more efficiency.Meanwhile, they considered about leakage power as well.

What is EDF ?
Earliest deadline first (EDF) is a dynamic scheduling algorithm used in real-time operating systems. It places processes in a priority queue. Whenever a scheduling event occurs (task finishes, new task released, etc.) the queue will be searched for the process closest to its deadline. This process is the next to be scheduled for execution.


utilization ui of task i is defined by (7). A proportion ui of the total number of cycles of a core will be dedicated to executing i : ui = wi / pi (7)

Wi =WCET(Worst Case Execution Time) Pi = Predefined Period

Simple Power-Aware Scheduling

Initial state: both cores are switched off Filling cores: applies when there is a ready task T Step1: Is there any core empty? If so, if core A is empty then launch T to core A, otherwise launch T to core B If not, go to step 2. Step2: Launch T to the core less loaded, If both cores are equally loaded then increase frequency and launch T to core A. Reducing frequency: applies when a task T finishes Step3: Are both cores equally loaded? If so, reduce frequency

Initial state: all cores are switched off Loop: Filling cores: applies when there is a ready task i Is there any core empty? If so, launch i to empty core Cempty, update Uempty If not, Launch i to the core has minimum Umini, update Umini If Umini >1,Increase frequency to guarantee Umini=1,update all the Un Else If Umax<1, Calculate the frequency ftry which can make Umax=1,
If ftry > fcritical, reduce frequency, update all the Un applies when a task f on Cf finishes, update Uf end Loop


shown in Fig.1, when the Vdd is lower then 0.75V, the leakage power is more then the dynamic power consumption . it means there should a critical frequency fcritical which make DVS scheduling makes no energy efficiency when reduce frequency less than it .

What happend as result?


DVS-EDF algorithm that proposed in this paper can save energy more than Simple PowerAware Scheduling algorithm ranging from 3% to 12%.

[1] Huang X, L. K. L. R. (2009). A energy efficient scheduling base on dynamic voltage and frequency scaling for multi-core embedded real-time system.Lecture Notes in Computer Science including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics, 5574 LNCS, 137-145. [2]Chen, J.-J., & Kuo, C.-F. (2007). Energy-Efficient Scheduling for Real-Time Systems on Dynamic Voltage Scaling (DVS) Platforms. 13th IEEE International Conference on Embedded and RealTime Computing Systems and Applications RTCSA 2007, 0(Rtcsa), 28-38. Ieee. [3] A. Mohsen and R. Hofmann, "Near Optimal and Energy-Efficient Scheduling for Hard RealTime Embedded Systems", in Proc. EUC, 2005, pp.234-244.

Fig.1 [1]