Chap.

7 Microprogrammed Control(Control Unit) 

7-1

7-1 Control Memory 
Control Unit  Initiate sequences of microoperations
» Control signal (that specify microoperations) in a bus-organized system 

groups of bits that select the paths in multiplexers, decoders, and arithmetic logic units 

Two major types of Control Unit
» Hardwired Control : in Chap. 5 


The control logic is implemented with gates, F/Fs, decoders, and other digital circuits + Fast operation, - Wiring change(if the design has to be modified) The control information is stored in a control memory, and the control memory is programmed to initiate the required sequence of microoperations + Any required change can be done by updating the microprogram in control memory, - Slow operation

» Microprogrammed Control : in this Chapter   

Control Word  The control variables at any given time can be represented by a string of 1¶s and 0¶s.  Microprogrammed Control Unit  A control unit whose binary control variables are stored in memory (control memory).
Computer System Architecture

Chap. 7 Microprogrammed Control

Dept. of Info. Of Computer

7-2  Microinstruction : Control Word in Control Memory  The microinstruction specifies one or more microoperations  Microprogram  A sequence of microinstruction » Dynamic microprogramming : Control Memory = RAM   RAM can be used for writing (to change a writable control memory) Microprogram is loaded initially from an auxiliary memory such as a magnetic disk Control words in ROM are made permanent during the hardware production. 7-1  1) Control Memory » A memory is part of a control unit : Microprogram » Computer Memory (employs a microprogrammed control unit)   User Program Machine Instruction Microprogram Microinstruction Microoperation Main Memory : for storing user program (Machine instruction/data) Control Memory : for storing microprogram (Microinstruction)  2) Control Address Register » Specify the address of the microinstruction  3) Sequencer (= Next Address Generator) » Determine the address sequence that is read from control memory » Next address of the next microinstruction can be specified several way depending on the sequencer input : p. » Static microprogramming : Control Memory = ROM   Microprogrammed control Organization : Fig. 217. and 4] Computer System Architecture Chap. 3. [1. Of Computer . 7 Microprogrammed Control Dept. of Info. 2.

7-3  4) Control Data Register (= Pipeline Register ) » Hold the microinstruction read from control memory » Allows the execution of the microoperations specified by the control word simultaneously with the generation of the next microinstruction  RISC Architecture Concept  RISC(Reduced Instruction Set Computer) system use hardwired control rather than microprogrammed control : Sec. of Info. 7 Microprogrammed Control Dept. Of Computer . 8-8  7-2 Address Sequencing  Address Sequencing = Sequencer : Next Address Generator  Selection of address for control memory Subroutine : program used by other ROUTINES  Routine  Microinstruction are stored in control memory in groups  Mapping  Instruction Code Address in control memory(where routine is located)  Address Sequencing Capabilities : control memory address  1) Incrementing of the control address register  2) Unconditional branch or conditional branch. depending on status bit conditions  3) Mapping process ( bits of the instruction address for control memory )  4) A facility for subroutine return Computer System Architecture Chap.

7-2  Multiplexer CAR Increment JMP/CALL Mapping Subroutine Return  S ta tus bits Bra nc h lo g ic MUX s e lec t Multiple xe rs S ub ro utine re g is e r (S BR) Clo c k Co ntro l a d dre s s re g is te r (CAR) Ins truc tio n c o d e Ma pp ing lo g ic CAR : Control Address Register » CAR receive the address from 4 different paths 1) Incrementer 2) Branch address from control memory 3) Mapping Logic 4) SBR : Subroutine Register Inc re me nte r Co ntro l me mo ry  SBR : Subroutine Register » Return Address can not be stored in ROM » Return Address for a subroutine is stored in SBR S e le c t a s tatus bit Bra nc h a ddre s s Mic ro o pe ratio ns Computer System Architecture Chap. Of Computer .7-4  Selection of address for control memory : Fig. of Info. 7 Microprogrammed Control Dept.

4 Microinstruction )   Mapping Function : Implemented by Mapping ROM or PLD Control Memory Size : 128 words (= 27) Chap. 7-8  Mapping of Instruction : Fig. of Info. 7-4) Opcode : Fig.  Status Bit Test » 4 X 1 Mux Branch Logic Input Logic(Tab. 7 Microprogrammed Control Dept.7-5  Conditional Branching  Status Bits » Control the conditional branch decisions generated in the Branch Logic  Branch Logic » Test the specified condition and Branch to the indicated address if the condition is met . otherwise. Of Computer Computer System Architecture . 7-3  Computer Instruction Mapping bits Microinstruction Address 1 0 1 1 0 x x x x 0 1 0 1 1 0 0 0 0 Address   4 bit Opcode = specify up to 16 distinct instruction Mapping Process : Converts the 4-bit Opcode to a 7-bit control memory address » 1) Place a ³0´ in the most significant bit of the address » 2) Transfer 4-bit Operation code bits » 3) Clear the two least significant bits of the CAR ( . the control address register is just incremented.

and Data read from memory can go only to DR  4 CPU Register and ALU : DR. or Memory (selected by MUX) AR can receive information from PC or DR (selected by MUX) PC can receive information only from AR ALU performs microoperation with data from AC and DR ( AC )  2 Control Unit Register : SBR.0111111)  Subroutine must have a provision for » storing the return address during a subroutine call » restoring the address during a subroutine return  Last-In First Out(LIFO) Register Stack : Sec. 228. 1000000 . Control memory(microprogram) » Data written to memory come from DR. 7-4  2 Memory : Main memory(instruction/data). Of Computer Computer System Architecture .7-6  Subroutine  Subroutines are programs that are used by other routines » Subroutine can be called from any point within the main body of the microprogram  Microinstructions can be saved by subroutines that use common section of microcode »   ) Memory Reference Operand Effective Address Subroutine p. CAR Chap. ALU » » » » DR can receive information from AC. 7-2 INDRCT ( FETCH Subroutine ORG 64. PC. AR. 8-7  7-3 Microprogram Example  Computer Configuration : Fig.1111111 INDRCT Subroutine) q(Routine 0000000 . Tab. AC. PC. 7 Microprogrammed Control Dept. of Info.

7-1 3 microoperation 3 . of Info. F2. 7-5(b) » 16 4  Microinstruction Format : Fig. Of Computer . 7-6  3 bit Microoperation Fields : F1.7-7  Instruction Format  Instruction Format : Fig. 000(no operation) 6 S BR 0 6 CAR 0 15 DR 0 » two or more conflicting microoperations can not be specified simultaneously  Co ntro l me m o ry 128×20 ) 010 001 000 Clear AC to 0 and subtract DR from AC at the same time stand for a transfer from DR to AC (T = to) Arithm e tic lo g ic a nd s hift unit Co ntro l unit 15 AC 0 » Symbol DRTAC(F1 = 100)  Computer System Architecture Chap. 7-5(a) » I : 1 bit for indirect addressing » Opcode : 4 bit operation code » Address : 11 bit address for system memory  MUX 10 AR Addre s s 10 PC 0 Me m o ry 2048×16 0 Computer Instruction : Fig. 7 Microprogrammed Control Dept. F3 » » 21  MUX Microoperation : Tab.

or Z BR Field : JMP. CAR(0. S. two. Z = AC = 0  2 bit Branch Fields : BR » 00 : JMP   Condition = 0 : Condition = 1 : Condition = 0 : Condition = 1 : 1 CAR n CAR  1 2 CAR n AD Save Return Address 1 CAR n CAR  1 2 CAR n AD. U = 1 01 : Indirect address bit. RET.7-8  2 bit Condition Fields : CD » » » » 00 : Unconditional branch. I. 6) n 0 » 01 : CALL   » 10 : RET » 11 : MAP  7 bit Address Fields : AD » 128 word : 128 X 20 bit  Symbolic Microinstruction Label Field : Terminated with a colon ( : ) Microoperation Field : one. of Info. CALL. or three symbols. SBR n CAR  1 Restore Return Address 3 CAR n SBR 4 CAR(2  5) n DR(11  14). or MAP Computer System Architecture Labe l FETCH: Mic ro o pe rat ORG 64 PCTAR READ. S = AC(15) 11 : Zero value in AC. INCPC DRTAR CD U U U BR JMP JMP MAP AD NEXT NEXT 0 Chap. Of Computer . 1. separated by commas CD Field : U. 7 Microprogrammed Control Dept. I = DR(15) 10 : Sign bit of AC.

of Info. Of Computer . Tab. Symbol ³RET´ or ³MAP´ : AD field = 0000000  ORG : Pseudoinstruction(define the origin. 7 Microprogrammed Control Dept. Symbolic Address : Label ( = Address ) b. INDRCT)  Microinstruction for FETCH Subroutine » AR n PC » DR n M [ AR]. 6) n 0 Operand Address Mapping 15 14 Opcode Fetch Opcode Decode Instruction Format 11 10 «. CAR(2  5) n DR(11  14). CAR(0. 7-3 » Address 0 to 63 : Routines for the 16 instruction( 4 instruction) » Address 64 to 127 : Any other purpose( Subroutines : FETCH. PC n PC  1 » AR n DR(0  10).7-9 AD Field a. « 0  Fetch Subroutine : address 64 » Labe l FETCH: Mic ro o pe rat ORG 64 PCTAR READ. INCPC DRTAR CD U U U BR JMP JMP MAP AD NEXT NEXT 0 I Opcode Address Computer System Architecture Chap. 7-2. or first address of routine)  Fetch (Sub)Routine  Memory Map(128 words) : Tab. 1. Symbol ³NEXT´ : next address c.

7-5(b) ) Process CAR = 0 0000 00 2) ADD Address 0 CD Indirect = 1 INDRCT subroutine Effective Address AR Return . Computer System Architecture Chap. 60 )  Indirect Address : I = 1 » Indirect Addressing : AR n M [AR ]  AR Mic ro o pe rat READ DRTAR DR CD U U . 7 Microprogrammed Control Dept. 7-2  The execution of MAP microinstruction in FETCH subroutine » Branch to address 0xxxx00 (xxxx = 4 bit Opcode)     ADD : 0 0000 00 = 0 BRANCH : 0 0001 00 = 4 STORE : 0 0010 00 = 8 EXCHANGE : 0 0011 00 = 12. 3) ADD Address 1 AR Memory DR . « . 4) ADD Address 2 AC + DR AC . MAP MAP branch ( Opcode = 0000. Fig. Of Computer . ( 16. FETCH subroutine Branch 1) PC Fetch MAP Routine Address Branch . 20. BR JMP RET AR AD NEXT 0 » INDRCT subroutine Labe l INDRCT: DR n M [ AR ] AR n DR  Execution of Instruction » ADD instruction     1) ADD FETCH subroutine Opcode fetch . of Info.7-10  Symbolic Microprogram : Tab.

7-11 » BRANCH instruction  1) BRANCH Indirect 2) BRANCH  Address 4 ARTPC . 7 Microprogrammed Control Dept. 7-3  Symbolic microprogram(Tab. 7-2) must be translated to binary either by means of an assembler program or by the user  Control Memory » Most microprogrammed systems use a ROM for the control memory   Cheaper and faster than a RAM Prevent the occasional user from changing the architecture of the system  7-4 Design of Control Unit  Decoding of Microinstruction Fields : Fig. FETCH PC FETCH PC Branch » STORE instruction » EXCHANGE instruction  Binary Microprogram : Tab. 7-7  F1. of Info. F2. Of Computer . CD Bit Address Sign = 0 Sign(S) = 1 Address 6 Branch . Address 4 . and F3 of Microinstruction are decoded with a 3 x 8 decoder  Output of decoder must be connected to the proper circuit to initiate the corresponding microoperation (as specified in Tab. 7-1) Computer System Architecture Chap.

10) 1 AC Multiplexe rs Lo a d AR Clo c k Computer System Architecture Chap.7-12 F1 »  F2 3×8 de c o de r 7 6 5 4 3 2 1 0 F3 3×8 de c o de r 7 6 5 4 3 2 1 0 ) F1 = 101 (5) : DRTAR F1 = 110 (6) : PCTAR Output 5 and 6 of decoder F1 are connected to the load input of AR (two input of OR gate) Multiplexer select the data from DR when output 5 is active Multiplexer select the data from AC when output 5 is inactive 3×8 de c o de r 7 6 5 4 3 2 1 0 From DR AND ADD DRTAC   Arithme tic lo g ic s hift unit  Arithmetic Logic Shift Unit » Control signal of ALU in hardwired control : p. 7 Microprogrammed Control Dept. ADD. Of Computer . and DRTAC. of Info. PCTAR DRTAR Lo a d Fro m PC 0 S e le c t Fro m DR(0. 20 » Control signal will be now come from the output of the decoders associated with the AND. Fig. 164. 5-19.

Of Computer . of Info. 1 I S Z MUX 2 S elec t Tes t Inc reme nte r Clo c k CAR  MUX 2 » Test a status bit and the result of the test is applied to an input logic circuit » One of 4 Status bit is selected by Condition bit (CD) Co ntro l me mory Mic ro o ps CD BR AD  Design of Input Logic Circuit » Select one of the source address(S0. 7 Microprogrammed Control Dept.7-13  Microprogram Sequencer : Fig. 7-8  Microprogram Sequencer select the next address for control memory  MUX 1 » Select an address source and route to CAR CAR + 1 JMP/CALL Mapping Subroutine Return » JMP   Exte rna l (MAP) Io Input I1 lo g ic T L 3 S1 S0 2 1 0 S BR Lo ad MUX 1 CALL JMP : AD MUX 1 2 CAR CALL : AD MUX 1 2 CAR . S1) for CAR » Enable the load input(L) in SBR Computer System Architecture Chap. CAR + 1(Return Address) LOAD SBR .

7-14  Input Logic Truth Table : Tab. Of Computer . 7-4 » Input :   I0. of Info. I1 from Branch bit (BR) T from MUX 2 (T) MUX 1 Select signal (S0. S1) S1 = I1I0¶ + I1I0 = I1(I0¶ + I0) = I1 S0 = I1¶I0¶T + I1¶I0T + I1I0 = I1¶T(I0¶ + I0) + I1I0 = I1¶T + I1I0 SBR Load signal (L) L = I1¶I0T 0 0 0 0 1 1 BR Field 0 0 1 1 0 1 I1 0 0 0 0 1 1 » Output :  Input I0 0 0 1 1 0 1 MUX 1 T 0 1 0 1 x x S1 0 0 0 0 1 1 S0 0 1 0 1 0 1 Load SBR L 0 0 0 1 0 0 CAR + 1 JMP CAR + 1 CALL MAP RET  CALL Computer System Architecture Chap. 7 Microprogrammed Control Dept.