Microprocessors

8086/8088 Hardware Specifications (Chapter 8)

ACOE255

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‡ The clock at the CLK pin provides the basic timing to the microprocessor. ACOE255 8088 CPU Vcc GND CLK RESET READY NMI INTR INTA' AD0 HOLD HLDA MN/MX' TEST' SS0' ALE DEN' DT/R' RD' WR' IO/M' A15 A8 AD7 A19/S6 A18/S5 A17/S4 A16/S3 2 . it begins executing instructions at memory location FFFF0H. ‡ Power is supplied between the Vcc and the GND pins. ‡ The microprocessor is reset if the RESET pin is held high for at least four clock periods. to enable the communication between the microprocessor and slower memory or peripheral devices. ‡ The READY signal is used to insert wait states. INTR (Interrupt Request) and INTA (Interrupt Acknowledge). ‡ Interrupts are supported by the signals NMI (Non-Maskable Interrupt). The clock must have a 33% duty cycle. The voltage at Vcc should be +5V ±10%.Whenever the microprocessor is reset.8088 pin outs and the pin functions ‡ The 8088 microprocessor is housed in a 40-pin DIP chip. ‡ The HOLD and HLDA (Hold Acknowledge) signals are used to enable DMA (Direct Memory Access).

‡ The address lines A0. ‡ The IO/M signal is used to select between I/O and memory devices.8088 pin outs and the pin functions ‡ The 8088 can operate in a minimum mode (MN/MX=1) or in a maximum mode (MN/MX=0).D7 on the pins AD0..AD7. ACOE255 8088 CPU Vcc GND CLK RESET READY NMI INTR INTA' HOLD HLDA MN/MX' TEST' SS0' A19/S6 A18/S5 A17/S4 A16/S3 A15 A8 AD7 AD0 ALE DEN' DT/R' RD' WR' IO/M' 3 . ‡ The 8088 has a 20 bit address bus and an 8-bit data bus. ‡ The address lines A16. ‡ The DEN (Data Enable) signal is used to enable the external data bus buffers.A19 are multiplexed with status lines...AD7 pins carry the addresses A0.. The maximum mode is used in multiprocessor applications or when a math coprocessor is used. the AD0.. ‡ If the ALE (Address Latch Enable) signal is activated (logic 1).A7 are multiplexed with the data lines D0. ‡ The RD and WR signals are used in the Read and Write cycles. ‡ The DT/R (Data Transmit/Receive) signal is used to specify the direction of the external data bus buffers.A7..

. The IO/M signal is inverted in the 8086 microprocessor. while an I/O device is enabled if the IO/M signal is low.D15 on the pins AD0. ‡ The main differences between the 8088 and the 8086 are: The 8086 has a 16-bit data bus... that is a memory is enabled if the IO/M is high.8086 pin outs and the pin functions ‡ Most of the 8086 pins/signals function the same way as the 8088 pins/signals. 8086 CPU Vcc GND CLK RESET READY NMI INTR INTA' HOLD HLDA MN/MX' TEST' BHE' AD15 A19/S6 A18/S5 A17/S4 A16/S3 AD0 ALE DEN' DT/R' RD' WR' IO'/M ACOE255 4 .A15 are multiplexed with the data lines D0.AD15.D15) during a read or write operation.. The address lines A0. The BHE (Bus High Enable) signal is used to enable the most significant data bus bits (D8 .

Clock/Reset/Ready Circuit ‡ The 8284 chips serves three purposes: Generates the main clock (CLK) for the processor (fc/3 with 33% duty cycle) and the clock for the peripheral devices (fc/5). 8284 X1 15MHz OSC X2 +5V On/Off 10K 100 RES Reset 10uF READY RDY READY RESET RESET CLK 5MHz CLK PCLK 15MHz 3MHz 8086/8088 Wait State Circuit ACOE255 5 . Provides the Reset pulse according to the state of the RC circuit connected at the RES input. Provides the Ready signal to insert wait states whenever the processor is accessing slow memory or peripheral I/O ports.

‡ Resistor R1 is used to reduce the current through C1 when the Reset button is pressed. the Reset signal goes to logic 0. thus avoid damaging C1. the capacitor is discharged through the switch. The diode is used to short circuit R1 during switch off. the Reset signal is at logic 1. When power is switched on. ‡ If the Reset button is pressed. When the voltage across the capacitor becomes equal to the minimum High voltage of the 8284 (2V). The capacitor starts charging with time constant (10K*10uF).Operation of the Reset Circuit +5V On/Off R2:100 Reset R1 10K VRES Reset C1 10uF VRES Switch ON Reset Button Pressed Reset Button Released Switch OFF ‡ Initially the capacitor is uncharged. the capacitor starts charging as before. thus discharge C1 fast. ACOE255 6 . When the Button is released.

VOLmax) .4 mA -0.0/0. Failure to do so might result in malfunctions or even damages on some components. before connecting anything on the microprocessors pins. The noise immunity of the 8088 is 0.6 mA -0. ‡ The Fan-Out is limited by the current sink of the device (Fan-Out = IOLmax/IILmax) For example the IOLmax of the 8088 is 2 mA and the IILmax of the 74LS family is 0. Thus the fan out is 2.45 V VOHmin = 2.1 mA -0.45=0. ‡ Fan-Out of a device is the maximum number of similar devices that can be connected on the output of that device without any problems.8-0. Input Characteristics of the 8086/8088 Logic 0 1 Voltage VILmax = 0.4 V Current IOLmax = 2.8 V VIHmin = 2. ‡ The Fan-Out is also limited by the noise immunity (VILmax.DC Characteristics and Fan Out ‡ It is essential to examine the DC characteristics of any devices involved in a microprocessor design. This reduces the maximum fan out to 10.0 mA IOHmax = -400 uA Recommended Fan-Out of the 8086/8088 Family TTL (74) TTL (74LS) TTL (74ALS) TTL (74F) CMOS (74HC) CMOS (CD4) NMOS ISINK -1.35V.0 V Current IILmax = 10 uA IIHmax = 10 uA Output Characteristics of the 8086/8088 Logic 0 1 Voltage VOLmax = 0.4 = 5.5 mA -10 uA -10 uA -10 uA ISOURCE 40 uA 20 uA 20 uA 25 uA 10 uA 10 uA 10 uA Fan-Out 1 5 10 10 10 10 10 ACOE255 7 .4 mA.

.Bus Demultiplexing ‡ The processor loads on the address bus (AD0 to AD7 and A8 to A19) the address to be used. The DEN enables the buffers of the 74LS245..A15 A8. and sets the ALE.A7 D0... Thus the address signals A0 to A7 are latched on the 74LS373.D7 ALE D7 D6 D5 D4 D3 D2 D1 D0 RD' DT/R' DEN' Timing Diagram for a Memory Read Cycle Read Data DIR G DT/R' DEN' ACOE255 8 .. ‡ On the next clock the processor resets the ALE and the AD0 to AD7 lines are used to carry data (D0 to D7). while the DT/R specifies the direction (read/write) AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ALE LS245 LS373 D Q EN 8088 CPU EN OE A7 A6 A5 A4 A3 A2 A1 A0 CLK A8.A15 Float AD0.AD7 A0.

They also provide the necessary buffering for the A0 to A7 and the D0 to D7 lines. ‡ The rest of the address lines (A8 to A15) as well as control lines (RD. WR. 8088 CPU A15 A14 A13 A12 A11 A10 A9 A8 LS244 4 4 E1 E2 A15 A14 A13 A12 A11 A10 A9 A8 LS244 RD WR IO/M' 4 RD WR IO/M' 4 E1 E2 ACOE255 9 .Bus Buffering ‡ The 74LS373 and the 74LS245 are used to demultiplex the AD0 to AD7 lines. and IO/M) need to be buffered using the 74LS244 octal buffer.

IO/M 4 E2 ACOE255 10 . WR.A7 RDY1 LS245 x8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 LS164 (Shift Reg. . .) CLK CLR SI HLDA D0 . A19 CLK LS244 4 4 A8 . A15 E1 E2 LS373 D Q EN x8 EN OE CS from memory devices 7w 6w 5w 4w 3w 2w 1w 0w A0 . . . D7 '1' MN/MX' TEST' SS0' NMI INTR INTA' DT/R' DEN' DIR G LS244 RD' WR' IO/M' E1 4 RD.A fully buffered/demultiplexed 8088 system 8088 CPU 8284 15MHz On/Off +5V 10K 100 Reset 10uF READY RDY2 AEN1 READY AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ALE HOLD RESET RES RESET X1 PCLK OSC X2 CLK 3MHz 15MHz 5MHz Vcc GND A19/S6 A18/S5 A17/S4 A16/S3 A15 A14 A13 A12 A11 A10 A9 A8 LS373 D Q EN x8 EN OE A16 .

‡ The main difference with the 8086 processor is that it has a 16-bit data bus multiplexed with the 16 lower address lines. A15 READY LS373 D Q EN x8 EN OE A0 . IO/M 4 E1 E2 ACOE255 11 . A19 A fully buffered/demultiplexed 8086 system Thus the 16-bit data bus (AD0 to AD7 and AD8 to AD15) must be demultiplexed. .A7 LS245 x8 D0 . CLK LS373 D Q EN x8 EN OE RESET A8 . . . . 8086 CPU Vcc GND A19/S6 A18/S5 A17/S4 A16/S3 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ALE HOLD HLDA LS373 D Q EN x8 EN OE A16 . . WR. D7 MN/MX' DT/R' TEST' SS0' NMI INTR INTA' DIR G DIR G DEN' LS245 RD' WR' IO'/M x8 D8 .D15 LS244 4 RD.

one bus cycle lasts 800 ns ACOE255 12 .BASIC BUS OPERATION ‡ The 8086/88 processors use the memory and I/O in periods called bus cycles ‡ Each bus cycle equals four system-clocking periods (T1-T4) ‡ For a 5 MHz clock.

and data appear on the bus ‡In T4 all bus signals are deactivated in preparation for the next bus cycle. and the ALE. ACOE255 13 .SIMPLIFIED 8086/88 WRITE BUS CYCLE ‡During the first clocking period (T1). DT/R and IO/M or M/ signals are also output ‡During T2 the WR . and the WR signal returns to logic 1. the address is sent to the address and address/data connections. DEN are asserted.

and the ALE. to allow time to the memory to access data ‡The bus is sampled at the end of T3 ‡Finally. the RD signal is deactivated ACOE255 14 .SIMPLIFIED 8086/88 READ BUS CYCLE ‡During the first clocking period (T1). DT/R and IO/M or M/ signals are also output ‡During T2 the RD . DEN are asserted ‡In T3 the READY signal is sampled and if low. the address is sent to the address and address/data connections. T3 becomes a wait state.

to lengthen the bus cycle. ACOE255 15 . inserted between T2 and T3. ‡ At the end of T2 is sampled on the falling clock edge. allowing slower memory and I/O components to respond. ‡ The READY input is sampled at the end of T2.THE READY SIGNAL AND WAIT STATES ‡ A wait state (Tw) is an extra clocking period. while in the middle of Tw. if necessary in the middle of Tw. it is sampled on the rising clock edge. If READY is µ0¶ then a Tw is inserted. and again.

Wait state generator circuit ‡ Wait states are extra clock pulses pulses inserted when the processor is accessing slow memory or I/O devices.) SI CLR CS from memory devices 0w 1w 2w 3w 4w 5w 6w 7w Ready CLK 8088 8086 RD' WR' INTA' ACOE255 16 . ‡ The 8088/8086 allow approximately 3 clock pulses for a memory read or memory write. RDY1 AEN1 RDY2 8284 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CLK Ready '1' CLK LS164 (Shift Reg. ‡ The circuit shown adds 1 wait state in each memory read or write cycle. If the access time of the memory (including the delays inserted by the bus buffers and address decoders) is longer than the access time of the processor (3/f) then wait states are needed. The number of wait states can be changed by changing the position of the jumper on the outputs of the 74LS164 shift register.

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