VLSI Physical Design Automation

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VLSI Physical Design Automation

Attribution Non-Commercial (BY-NC)

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You are on page 1of 42

dpan@ece.utexas.edu

Office: ACES 5.434

11/20/08 1

Objective of this Lecture

❁ To review the materials used in fabrication of VLSI

devices.

❁ To review the structure of devices and process

involved in fabricating different types of VLSI circuits

❁ To review the basic algorithm concepts

❁ To level-set everyone so that we can get into serious

Physical Design topics in the next lecture

2

Wafer, Die and Package

3

Fabrication Materials

copper

4

Electron and Holes

Silicon

atom

Free

Electron

+Ion

Hole

http://researchweb.watson.ibm.com/resources/press/strainedsilicon/

❁ Material can be enriched in holes or electrons by introducing impurities

❁ Holes in crystals can be enriched by embedding some boron atoms

❁ Electrons in crystals can be enriched by embedding phosphorus atoms

❁ Recent breakthroughs: strained silicon (IBM) to stretch silicon such that

electrons experience less resistance and flow up to 70% faster

5

The Three Regions in a n-p Junction

Carrier-depletion

zone

Electron

Interface Hole rich

rich

Silicon dioxide

insulator

Mask

Phosphorous

Depletion

zone

Substrate

(a) (b) (c)

be created on a certain layer. Masks are used to create a

specific patterns of each material in a sequential manner

and create a complex pattern of several layers

6

A nMOS Transistor

Enhancement Mode

(a) (b)

Gate

Source Drain

Vg<Vt Vg≥Vt

Vs Vd Vs Vd

(c)

7

Fabrication of VLSI Circuits

1. Create

2. Define

3. Etch Silicon wafers

diffusion or implantation

Pattern definition by

photolithography

Etch

8 to 10 iterations

8

Photolithographic Process

UV Radiation

Silicon dioxide

Photoresist (Negative )

Silicon

Shadow of

opaque feature

mask feature

(a) (b)

Hardened

Photoresist

Silicon dioxide

(c)

(d) etched where

Photoresist exposed

stripped

(e)

9

Details of Fabrication Processes

Crystal growth & wafer preparation

Epitaxy

Oxidation

Diffusion

Ion implantation

Lithography

Etching

Packaging

10

Basic Design Rules

1. Size Rules

2. Separation Rules

3. Overlap Rules

Diffusion Region Width 2λ

Polysilicon Region Width 2λ

Diffusion-Diffusion Spacing 3λ

Poly-Poly Spacing 2λ

Polysilicon Gate Extension 2λ

Contact Extension λ

Metal Width

3λ

11

Size and Separation Rules

Diffusion Poly

Metal

Diffusion

Channel

Short

Poly

12

Overlap Rules for Contact cuts

(a) (b)

13

Layout of Basic Devices

❁nMOS Inverter

❁CMOS Inverter

❁nMOS NAND Gate

❁CMOS NAND Gate

❁nMOS NOR Gate

❁CMOS NOR Gate

14

A CMOS Inverter

15

A CMOS NAND Gate

16

A CMOS NOR Gate

17

Additional Fabrication Factors

❁ Scaling

❁ Parasitic Effects

❁ Yield Statistics and Fabrication Costs

❁ Delay Computation

❁ Noise and Crosstalk

❁ Power Dissipation

18

Mini Summary

❁ The three types of materials are insulators, conductors and

semiconductors

❁ A VLSI chip consists of several layers of different materials on

a silicon wafer.

❁ Each layer is defined by a mask

❁ VLSI fabrication process patterns each layer using a mask

❁ Complex VLSI circuits can be developed using basic VLSI

devices

❁ Design rules must be followed to allow proper fabrication

❁ Several factors such as scaling, parasitic effects, yield

statistics and fabrication costs, delay computation, noise and

crosstalk and power dissipation play a key role in fabrication

of VLSI chips

19

Design Styles

Complexity of

VLSI circuits

20

Full Custom Design Style

Pad Metal Via Metal 2

Data Path

I/O

PLA

ROM/RAM

Random logic

A/D Converter

21

Standard Cell Design Style

Cell Feedthrough

VDD Metal 1 Metal 2 GND

D C C B

A C C

D C D B

C C C B

Cell A Cell B

22

Gate Array Design Style

A

C

B

23

FPGA Design Style

24

Field-Programmable Gate-Arrays (FPGAs)

❁ Programmable logic

❁ Programmable interconnects

❁ Programmable inputs/outputs

25

Comparisons of Design Styles

style

cell size variable fixed height * fixed fixed

cell type variable variable fixed programmable

cell placement variable in row fixed fixed

interconnections variable variable variable programmable

26

Comparisons of Design Styles

style

compact

Area compact moderate large

to moderate

high

to moderate

layers layers

27

Packaging Styles

Packaging

PCB MCM WSI (SOC)

Area

Performance, cost

are driving the development of more advanced VLSI packaging and

interconnection approaches.

28

History of VLSI Layout Tools

Year Design Tools

1950 - 1965 Manual Design

Automatic routers( for PCB)

Efficient partitioning algorithm

Well Defined phases of design of circuits

Significant theoretical development in all phases

Parallel algorithms for physical design

Significant development in underlying graph theory

Combinatorial optimization problems for layout

centric design, physical-logical codesign

for design closure (timing, noise, power, P/G/clock,

manufacturability)

29

Now You Need Algorithms

• To put devices/interconnects together into VLSI chips

• Fundamental questions: How do you do it smartly?

• Definition of algorithm in a board sense: A step-by-

step procedure for solving a problem. Examples:

– Cooking a dish

– Making a phone call

– Sorting a hand of cards

• Definition for computational problem: A well-defined

computational procedure that takes some value as

input and produces some value as output

30

Example: Selection Sort

• Input: An array of n numbers D[1]…D[n].

• Output: An array of n numbers E[1]…E[n] such that

E[1]≥E[2]≥ … ≥E[n].

• Algorithm:

1. For i from 1 to n do

2. Select the largest remaining no. from D[1..n].

3. Put that number into E[i].

31

Some Algorithm Design Techniques

• Greedy

• Divide and Conquer

• Dynamic Programming

• Network Flow

• Mathematical Programming (e.g., linear programming,

integer linear programming)

32

Reduction

• Idea: If I can solve problem A, and if problem B can be

transformed into an instance of problem A, then I can

solve problem B by reducing problem B to problem A

and then solve the corresponding problem A.

• Example:

– Problem A: Sorting

– Problem B: Given n numbers, find the i-th largest numbers.

33

Analysis of Algorithm

• There can be many different algorithms to solve the

same problem.

• Need some way to compare 2 algorithms.

• Usually the run time is the criteria used.

• However, difficult to compare since algorithms may be

implemented in different machines, use different

languages, etc.

• Also, run time is input-dependent. Which input to use?

• Big-O notation is used.

34

Big-O Notation

• Consider run time for the worst input

=> upper bound on run time.

• Express run time as a function input size n.

• Interested in the run time for large inputs.

• Therefore, interested in the growth rate.

• Ignore multiplicative constant.

• Ignore lower order terms.

• 3n2+6n+2.7 is O(n2).

• n1.1+10000000000n is O(n1.1).

• n1.1 is O(n2).

35

Effect of Multiplicative Constant

800

700

n2

600

Run time

500

400

10n

300

200

100

0

0 10 20 n

36

Growth Rates of some Functions

O ( log n ) < O (log2 n ) < O ( n ) < O( n)

Polynomial

Functions

< O ( n log n ) < O ( n log2 n ) < O ( n1.5 ) < O ( n 2 )

< O (n 3 ) < O (n 4 )

< O (n ) = O (2 )

Exponential

log2 n

Functions

log n

n n n

n

37

Problem of Exponential Function

• Consider 2n, value doubled when n is increased by 1.

n 2n 1µs x 2n

10 103 0.001 s

20 106 1s

30 109 16.7 mins

40 1012 11.6 days

50 1015 31.7 years

60 1018 31710 years

• If you borrow $10 from a credit card with APR 18%, after

40 yrs, you will own $12700!

38

NP-Complete

• The class NP-Complete is the set of problems which

we believe there is no polynomial time algorithms.

• Therefore, it is a class of hard problems.

• NP-Hard is another class of problems containing the

class NP-Complete.

• If we know a problem is in NP-Complete or NP-Hard,

there is no hope to solve it efficiently.

39

Solution Type of Algorithms

• Polynomial time algorithms

• Exponential time algorithms

• Special case algorithms

• Approximate algorithms

• Heuristic algorithms

40

Before Next Class

• If you need to refresh your Algorithms:

– Introduction to Algorithms, Ch.1, 2

– Sherwani Ch. 4 to get a glimpse

• Don’t worry if you don’t totally remember or understand

• We will come back when we cover each physical design topic

• Circuit partitioning in the next few classes

– Sait & Youssef (SY) Ch.2

• Easier to follow

– Or Sherwani Ch.5

• More literature context

41

Further Reading

• Details of Fabrication Processes

– www.infras.com/Tutorial/sld001.htm

– www.engr.sjsu.edu/~dparent/ee129/index.htm

– people.seas.harvard.edu/~jones/es154/lectures/lecture_4/pdfs/

upenn_pdfs/EE560_ICFab01.pdf

• Details of nMOS, pMOS operations

– www.cs.utah.edu/classes/cs6710/slides/cs6710-MOSx6.pdf

– users.ece.utexas.edu/~adnan/vlsi-05-backup/lec4MosEqns.ppt

42

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