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Programmable Peripheral interface -8255
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Designed by Intel to interface with 8,16 bit & higher capability microprocessor with I/O peripherals It has 24 i/o lines which may be programmed in to two groups of 12 lines or three groups of 8 lines The two group i/o pins named as GROUP A and GROUP B Each group contains a two sub group of 8 bit i/o lines & 4 bit i/o lines Group A contains an 8 bit port A along with a 4 bit port C called Cupper Group B contains an 8 bit port B along with a bit port C called Clower
8255 Pin diagram
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PA7-PA0 buffered/latched i/o 8 bit PORT A PB7-PB0 buffered/latched i/o 8 bit PORT B PC7-PC4 Upper nibble of PORT C PC3-PC0 Lower nibble of PORT C RD ²Read WR-Write CS-Chip Select A0-A1 Address Lines D0-D7 Data Lines carries DATA or Control Word to/from processor RESET Clears control word registers
8255 internal Architecture
issues commands to both of the Control Groups . ` Read/Write and Control Logic This block is to manage all of the internal and external transfers of both Data and Control words It accepts inputs from the CPU Address and Control busses and in turn. Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control words information is transferred through the data bus buffer.` Data Bus Buffer This bi-directional 8-bit buffer is used to interface the 8255 to the system data bus.
` (CS) Chip Select A "low" on this input pin enables the communication between the 8255 and the CPU ` (RD) Read A "low" on this input pin enables 8255 to send the data or status information to the CPU on the data bus ` (WR) Write A "low" on this input pin enables the CPU to write data or control words into the 8255 .
` (A0 and A1) Port Select 0 and Port Select 1 These input signals. in conjunction with the RD and WR inputs. control the selection of one of the three ports or the control word register .
Control Word Register .
Each of the Control blocks (Group A and Group B) accepts "commands" from the Read/Write Control logic. "bit set". receives "control words" from the internal data bus and issues the proper commands to its associated ports There are 2 basic modes of operations I/O Mode (Mode 0.Mode1 & Mode2) Bit Set ² Reset mode (BSR) ` . etc. "bit reset".` Group A and Group B Controls The CPU "outputs" a control word to the 8255 The control word contains information such as "mode".
D2 & D3 of the control word register .BSR Mode ` ` In this mode any of the 8 bit of port C can be set or reset depending on D0 of the control word The bit to be set or reset is selected by D1.
` Eg: If the 5th bit (PC5) of port C has to be "SET". then what is the control word? 1. 3. 2. D0 = '1'. 4. D5. assume them to be '0'. . we get the control word as "0B (hex)". hence. D1 = '1'. D2 = '0'. Applying the above values to the format for BSR mode. PC5 has to be set. D3 = '1'. Since it is BSR mode. D6 are not used. hence. Since D4. PC5 has to be selected. D7 = '0'.
Input ports are not latched A maximum of four ports are available so that overall 16 I/O configuration are possible. All these modes can be selected by programming the Control word register.The two 4-bit ports can be combinedly used as a third 8-bit port. Any port can be used as an input or output port Output ports are latched.Mode 0(Basic I/O mode) ` Features of this mode Two 8-bit ports ( port A and port B )and two 4-bit ports (port C upper and lower ) are available. CWR has two formats one for BSR mode and I/O modes .
Mode 1 (Strobed I/O mode) ` ` ` ` In this mode hand shaking signals controls the i/o operation Port C lines PC0. indicates data loaded into latches ( Acknowledgement ) .PC6 & PC7 provides the handshake signals for port A PC4 & PC5 can be used as independent I/O lines Input Control Signal Definitions ` STB(Strobe input) : when it is low. data from the data lines are loaded into the latches ` IBF (Input buffer full):if it rises high.PC1 & PC2 provides the handshake signals for port B Port C lines P3.
` ` INTR (Interrupt Request ):used to interrupt the CPU and to get the service by the input device INTE is the internal flag controlled by the bit set/reset mode either PC4 or PC2 as below .
Mode 1 Strobed Input Data Transfer .
Output control signal definition OBF(output buffer full):if low. . indicates that CPU has written data to output ACK:acts as ack given by the output device INTR (Interrupt request ):used to interrupt the CPU when output device ack the data receipt.
Control word of A & Control word of B .
Mode 1 Strobed output data transfer .
Mode 2(Strobed bi directional I/O) ` ` ` ` Only 8 bit in group A is available The 8 bit port A is bidirectional & have 5 bit port control lines(PC3-PC7) 3 I/O lines are available at port C (PC2-PC0) Inputs and outputs are both latched .
indicates the ack for the received byte INTE1(Flag associated with OBF):controlled by PC6 .Control signal definition in mode 2 ` INTR(Interrupt request):used to interrupt the CPU to ask for data transfer Control signal for output operations ` ` ` OBF(output buffer full):If it is low .indicates CPU has written data to port A ACK:If it is low .
Note: WR must occur before ACK and STB must be activated before RD. ` . raises to 1 indicates data has been received by the receiver.Control signal for input operations STB(strobe input) :if Low. indicates the data into the input latches ` IBF(Input buffer full):when data is loaded into input buffer.
Mode 2 control word & Pins .
Half duplex and full duplex Synchronous or asynchronous In synchronous transmission data is sent in blocks at constant rates. start and the end of blocks are identified with specific bytes or bit pattern In asynchronous transmission each data character has a bit which identifies its start and 1 or 2 bits which identity its end .Serial I/O Interface -8251 ` Introduction To begin with serial I/O there are certain terms and acronyms has to be explained they are Simple .
Given as 1/(time between signal transmission) Serial data transmission are slow when compared to parallel data transmission Parallel data transmission requires more wires which makes difficult for transmitting data over a long distance Intel introduced 8251 a programmable synchronous or asynchronous communication offen called as universal synchronous asynchronous receiver and transmitter or USART ` ` ` .` Baud Rate.indicates the rate at which serial data is being transferred.
` Microcomputer always deals with parallel data. telephone lines were used For this the digital data has to converted into audio frequency signal which can transmit through phone lines The device used for conversion is called a modem ` ` ` . Hence before doing serial communication the data has to converted into serial data For sending serial data over a long distance.
` Data and handshaking signals in sequence When the terminal is switched on.Terminal has a character ready to send. It asserts Data-Terminal-Ready(DTR) to tell the modem it is ready Modem asserts Data-Set-Ready (DSR) to the terminal Modem dials the remote computer . it will assert Request-To-Send (RTS) signal The modem will send Carrier-Detect signal to the terminal indicating a connection establishment The modem will assert a Clear-To Send signal (CTS) back to the terminal .if it is available.
8251 block diagram .
RD & RESET are connected to the system signals TXC. a control address(FFF2H) which is selected when C/D is high and a data address (FFF0H)when the C/D is low RD.RXC transmitter clock and receiver clock for shifting the data.WR.PIN Description ` ` ` ` ` ` ` ` D7-D0 ²connect system bus to device CS-used for address decoding 8251 has two internal addresses. used to select the frequency signal 1.indicates serial-data output RXD-indicates serial-data input .16 or 64 times the baud rate CLK ²system clock signal TXD.
Command word 3. Mode word 2.` ` ` ` TXE-Transmitter buffer empty TXRDY ² Transmitter ready (ready for char from CPU) RXRDY-Receiver ready (has a character for CPU) SYNDET/BD-Sync detect /Break detect CONTROL WORDS There are two types of control word and a status word 1.Status word It is possible to see the internal status of the 8251 by reading the Status word .
Mode Word-Asynchronous .
Mode Word ²Synchronous .
Command Word .
Status Word ` ` ` ` ` ` ` ` D0-Indicates USART is ready to accept a data character or command D1-indicates USART has received the Character and ready to transfer it to the CPU D2-indicates parallel to serial converter is empty D3-Parity error D4-Over Run error-Indicates CPU does not read a character before the next one becomes available D5-Framing Error-Set when valid stop is not detected D6-Sync Detect-Indicates that the character sync has been achieved D7-used to test modem condition .
DMA controller 8257 ` Direct Memory Access--the ability of an I/O subsystem to transfer data to and from a memory subsystem without processor intervention. DMA Controller--a device that can control data transfers between an I/O subsystem and a memory subsystem in the same manner that a processor can control such transfers ` .
DMA Controller Interfaced with the CPU .
Features of 8257 ` ` It is programmable.4 channel direct memory access controller Each channel can programmed individually Each channel has a pair of 16 bit registers viz DMA address register and terminal counter registers Address register gives the address of the memory location & counter specifies the number DMA cycles to be performed It maintains a DMA cycle count for each channel and activates the TC signal to indicate the peripheral that specified DMA cycles are completed ` ` ` .
Pin Configuration ` It has priority logic that resolves the peripheral request. Can be programmed in two modes either fixed or rotating mode D0-D7( Bidirectional pins connected to system bus Address Bus(A0-A3 & A4-A7) ` ` ` Address Strobe (ADSTB)-used to demultiplex higher byte address and data using external latch .
IOW) Chip Select(CS) Hold Request-it is used for requesting the CPU to get the control of the system bus Hold Ack(HLDA) -indicates that CPU has granted the system bus ` ` ` ` ` .` Address Enable (AEN)-indicates available of higher address on the latches Memory Read/Memory Write(MEMR.MEMW) I/O Read / I/O Write (IOR.
` ` ` .` DREQ0 ²DREQ3 -these are DMA request DACK0-DACK3 ²these are the ack for DMA request Terminal Count ² it indicates the completion of DMA cycle MARK ²notifies the peripherals that current DMA cycle is 128th cycle since the previous MARK.
Architecture of 8257 .
it is used to transfer data between CPU and internal registers of 8257 In master mode. it is used to send higher byte address on the data bus DMA Channels: 8257 has 4 separate channels CH0 to CH1. In slave mode.each channel has a pair of 2 16 bit registers.` ` Data buffers-there is a 8 bit buffer which interface the 8257 to system bus. Also there are two common register for all the channels namely mode set & status registers CPU selects one of these 10 registers using address lines A0-A3 .
` DMA address register.used to store the starting address of the memory location ` Terminal Count registers ²lower 14 bits are used count the required number of DMA cycles .
` T1 & T2 indicates the type of DMA operation ` Mode Register .
is set enables rotating priority otherwise normal B6 (TC) -bit is set selected channel is disabled after the terminal count condition is reached & further prevents any DMA cycle on the channel If the TC stop bit is set to zero the channel is not disabled even after the count reaches zero ` ` ` .` B0-B3 bits enable one of the four DMA channels B4(Rotating priority) .
auto load bit is set enables channel 2 for repeat block chaining operation. ` ` .` B7.used while interfacing with slow devices.if set then extends the duration of MEMW and IOW. Channel 2 register are reloaded with the corresponding channel 3 register for the next block transfer B6 (Extended write).
Status Register .
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